• Aucun résultat trouvé

Low temperature noise spectroscopy of p-channel SOI FinFETs

N/A
N/A
Protected

Academic year: 2021

Partager "Low temperature noise spectroscopy of p-channel SOI FinFETs"

Copied!
3
0
0

Texte intégral

(1)

HAL Id: hal-00994397

https://hal.archives-ouvertes.fr/hal-00994397

Submitted on 22 Jul 2014

HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci- entific research documents, whether they are pub- lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers.

L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Low temperature noise spectroscopy of p-channel SOI FinFETs

H. Achour, Bogdan Cretu, E. Simoen, Jean-Marc Routoure, Régis Carin, Rachida Talmat, A. Benfdila, M. Aoulaiche, C. Claeys

To cite this version:

H. Achour, Bogdan Cretu, E. Simoen, Jean-Marc Routoure, Régis Carin, et al.. Low temperature

noise spectroscopy of p-channel SOI FinFETs. 10th Workshop of the Thematic Network on SOI

Technology, Devices and Circuits, Jan 2014, tarragona, Spain. 2 p. in USB Key. �hal-00994397�

(2)

Low temperature noise spectroscopy of p-channel SOI FinFETs

H. Achour

1,4

, B. Cretu

2,3

, E. Simoen

5

, J.-M. Routoure

1,3

, R. Carin

1,3

, R. Talmat

1,4

, A. Benfdila

4

, M. Aoulaiche

5

, C. Claeys

5,6

1University of Caen Basse-Normandie, UMR 6072 GREYC, F-14050 Caen, France

2ENSICAEN, UMR 6072 GREYC, F-14050 Caen, France

3CNRS, UMR 6072 GREYC, F-14032 Caen, France

4GRMNT, Mouloud Mammeri University of Tizi-Ouzou, Algeria

5Imec, Kapeldreef 75, B-3001 Leuven, Belgium

6E.E. Dept. KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium

1. Abstract

The aim of this study is to use the excess low frequency noise versus the temperature in order to characterize the traps in the depleted silicon film of p-channel FinFETs on standard and strained substrates. An important number of identified traps related to boron and carbon can be observed, in particular for the strained substrate devices.

2. Introduction

It is already known that the multi-gate FinFETs are considered as strong contenders for the nano MOS device structures, mainly because the 3D geometry, through a better electrostatic control of the gate over the conduction channel, leads to an improved control of the short-channel effects and provides an enhanced mobility due to the undoped channel [1]. The performance enhancement can be further obtained without adding major process complexity by the use of the strain engineering: biaxial strain (sSOI) or of the uniaxial strain, implemented by contact etch stop layers (CESL) [2]. Furthermore, the integration of SiGe in the source and the drain regions, realized by selective epitaxial growth (SEG), leads to a reduction of the access resistances [3].

One of the methods used for material characterization is provided by the study of the generation–recombination (GR) noise, corresponding to a Lorentzian type of spectra and allowing to do the so-called noise spectroscopy when performed as a function of temperature at fixed biasing [4]. The low frequency noise at different temperatures as a function of the applied gate voltages was already studied for the p- channel FinFET devices in order to investigate the 1/f noise [5,6].

This work is focused on the study of the Lorentzian noise contributions on the total low frequency noise versus temperature as a diagnostic tool to characterize the traps located in the depleted Si film (fin) of p-

channel FinFETs devices.

2. Experimental

The investigated devices are p-channel tri-gate FinFETs processed in a 32 nm technology with standard and strained SOI substrates. The gate oxide consists of a high-k dielectric (HfSiON) on top of a 1 nm interfacial SiO2 resulting in an equivalent oxide thickness (EOT) of 1.5 nm. The metal gate consists of 10 nm TiN covered by 100 nm polysilicon. The devices have a fin width of 25 nm, fin height of 65 nm, 5 fins in parallel. The tested devices are p-channel FinFETs whit fixed mask gate length of 1 µ m on standard SOI and strained sSOI substrates combined with compressive uniaxial strain (CESL) using SEG in the drain and source regions.

The low frequency noise measurements were performed directly at wafer-level using a Lakeshore TTP4 prober.

The noise measurement set-up allows to bias the devices by choosing the VGS and VDS voltages, and also to measure the total dynamic resistance between drain and source (rT) and the transconductance (gm) by applying a small signal at the source and gate nodes, respectively.

3. Low frequency noise spectroscopy

Fig. 1 illustrates an example of the frequency normalized noise spectral density versus the temperature.

Considering white noise, 1/f and Lorentzian noise contributions, the total low frequency noise can be perfectly modeled (equation in the inset of Fig. 1). The different noise parameters, in particular the plateau (Ai) and the characteristic frequency (f0i) values of the different Lorentzians contributions, can be clearly identified. According to [7], if the characteristic frequency of a Lorentzian does not change with the applied gate voltage, this Lorentzian can be assigned to a trap located in the depletion film. In this case the characteristic frequency should vary with the temperature [8] (Fig. 2). Only Lorentzians which satisfy

(3)

these two conditions were taken into account.

The variation of the characteristic time constant of the Lorentzians (τi = (2πf0i)-1) as a function of the temperature allows to plot an Arrhenius diagram;

according to [6] from the slope and the y-intercept of the evolution of ln(τiT) versus (kBT)-1 one can extract the energy difference between the appropriate band energy and the trap energy (i.e. ∆E = ET-EV) and the capture cross section σp of the trap, respectively. The physical nature of these traps can be identified by comparing the energy level and the capture cross section of the traps with data in the literature.

The Arrhenius diagram for a standard SOI device is plotted in Fig. 3. Three traps can be clearly identified:

one is related to hydrogen (V2H) [9]; the second one to the interstitial carbon – interstitial oxygen complex (CiOi) [10,11], and the last to interstitial boron (Bi) [11,12]. The identified traps and the associated effective trap densities for all the investigated p-channel devices on different strained substrates with can be observed are plotted in the Fig. 4.

The traps related to hydrogen may be present due to hydrogen residues after annealing. All the studied devices have received a boron halo implantation in order to reduce the short channel effects. This may explain the presence of an important number of identified traps related to boron. A contamination due to the SiC liner deposition step can explain the important number of traps related to carbon. The presence of the divacancies (V-P) could be related by the evolution to a stable state of the unstable defects like Frenkel pairs, which could be generated during the implantation.

The estimated surface densities of the identified traps have the same order of magnitude to those identified on n-channels FinFET [13].

4. Conclusions

The analysis of the temperature evolution of the Lorentzian time constant allowed to identify traps in the silicon film. Three traps were identified for devices in a standard substrate. Using strain or SEG leads to an increase in the number of identified traps for a given technology. The nature of the identified traps suggests that the implantation and the SiC liner process are mainly responsible for all the observed traps. The nature of one trap was not identified. However, it can originate from dry-etching or implantation damage.

References

[1] Colinge JP. Microelectron Eng 2007;84:2071–6.

[2] Claeys C et al. Solid-State Electron. 2008;52:1115-26.

[3] Ning XJ et al. Mater Sci Eng B 2006;134:165–71.

[4] Grassi V et al. IEEE Trans Electron Devices 2001;48:2899–905.

[5] Achour H et al. C. Solid-State Electron. 2013;90:160-165.

[6] Achour H et al. 14th International Conference on Ultimate

Integration on Silicon (ULIS) 2013;

doi:10.1109/ULIS.2013.6523529

[7] Murray DC et al. IEEE Trans Electron Devices 1991;38:407.

[8] Lukyanchikova N. In: Balandin A, editor. Noise and fluctuations control in electronic devices (2002), American Scientific, Riverside, CA; 2002. p. 201.

[9] Hallen A et al. Journal of Applied Physics 1996; 79 (8) : 3906 - 3914.

[10] van Vechten J.A. Physical Review B 1978, 35(2), p. 864- 870.

[11] Claeys C and Simoen E, Radiation effects in Advanced Semiconductor Material and Devices, Spinger Verlag, 2002 [12] Bains S.K and Banbury P.C. Semiconductor Science and Technology 1987; 2 (1): 20-29.

[13] Talmat R et al. C. Solid-State Electron. 2012;70:20-66 .

Fig. 1: Modelling of a noise spectrum Fig. 2: SVG·f versus all investigated temperatures

Fig. 3: Arrhenius plot for a standard device on SOI substrate

a) b) c)

Fig. 4: Arrhenius plot for a) SOI +SEG; b) sSOI+CESL; c) sSOI+CESL+SEG

100 101 102 103 104 105

10-10 10-9 10-8

( )2

0 0

( )

G 1

f N i

V

i i

K A

S f B

f = f f

= + +

+

Kf= 310-10(V²) B= 710-14(V²/Hz)

f01= 1800 Hz A01= 410-13(V²/Hz)

p-channel SOI FinFET LG = 1µm; Wfin = 25 nm T = 240 K VDS = 20 mV ID = 1µA

experimental model

SVG⋅⋅⋅⋅f (V²)

f (Hz) f01= 6 Hz

A01= 1.210-10(V²/Hz) equation model

100 101 102 103 104

10-11 10-10 10-9 10-8 10-7

f (Hz)

300 K 100 K

SVG⋅f (V2)

T (K)

40 50 60 70 80 90 100 110

0 2 4 6 8

10 ∆∆E = 0.43 eV σ σσ

σp = 7⋅⋅⋅⋅10-17(cm2)

∆∆

E = 0.339 eV σ σσ σp = 6.6⋅⋅⋅⋅10-16(cm2)

∆∆

E = 0.13 eV σ σσ σp = 2.5⋅⋅⋅⋅10-19(cm2)

p-channel SOI FinFET V2H (Neff = 3.2⋅⋅⋅⋅1011 cm2) CiOi (Neff = 2.2⋅⋅⋅⋅1011 cm2) Bi (0/+) (Neff = 4⋅⋅⋅⋅1011 cm2)

ln (ττττ⋅⋅⋅⋅T2) (K2⋅⋅⋅⋅s)

(kB⋅⋅⋅⋅T)-1(eV-1)

40 50 60 70 80 90 100 110

0 2 4 6 8 10

∆∆

E = 0.38 eV σ σσ σp = 1.2⋅⋅⋅⋅10-14 (cm2)

∆∆

E = 0.155 eV σσσ σp = 3⋅⋅⋅⋅10-20 (cm2)

∆∆

E = 0.3 eV σ σσ σp = 1⋅⋅⋅⋅10-17 (cm2)

∆∆

E = 0.43 eV σ σσ

σp = 6⋅⋅⋅⋅10-17 (cm2)

(kB⋅⋅⋅⋅T)-1(eV-1) ln (ττττ⋅⋅⋅⋅T2) (K2⋅⋅⋅⋅s)

SOI+SEG pFinFET V2H (Neff = 4⋅⋅⋅⋅1011 cm2) BiBs (Neff = 2⋅⋅⋅⋅1011 cm2) CiPs (0/-) (Neff = 1.2⋅⋅⋅⋅1011 cm2) not identified (Neff = 5.1⋅⋅⋅⋅1010 cm2)

40 50 60 70 80 90 100 110

0 2 4 6 8 10

∆∆

E = 0.10 eV σ σσ σp = 3⋅⋅⋅⋅10-19 (cm2)

∆∆

E = 0.13 eV σσσ σp = 2.7⋅⋅⋅⋅10-19 (cm2)

∆∆

E = 0.27 eV σ σσ σp = 3.6⋅⋅⋅⋅10-17 (cm2)

∆∆

E = 0.29 eV σ σσ σp = 3.3⋅⋅⋅⋅10-18 (cm2)

∆∆

E = 0.43 eV σσσ σp = 3.7⋅⋅⋅⋅10-17 (cm2)

p channel sSOI+CESL FinFET V2H (Neff = 1.9⋅⋅⋅⋅1011 cm2) BiCs (Neff = 2.3⋅⋅⋅⋅1011 cm2) Ci (+/0) (Neff = 4.5⋅⋅⋅⋅1011 cm2) Bi (0/+) (Neff = 2.5⋅⋅⋅⋅1011 cm2) Ci (0/-) (Neff = 3.7⋅⋅⋅⋅1011 cm2)

ln (ττττ⋅⋅⋅⋅T2) (K2⋅⋅⋅⋅s)

(kBT)-1(eV-1)

40 50 60 70 80 90 100 110

0 2 4 6 8 10

∆∆

E = 0.1 eV σ σσ σp = 7.5⋅⋅⋅⋅10-19 (cm2)

∆∆

E = 0.339 eV σ σσ σp = 4.5⋅⋅⋅⋅10-16 (cm2)

∆∆

E = 0.44 eV σ σσ σp = 5.5⋅⋅⋅⋅10-16 (cm2)

p-channel sSOI+SEG+CESL FinFET V-P (Neff = 4.3⋅⋅⋅⋅1011 cm2) CiOi (Neff = 2⋅⋅⋅⋅1011 cm2) BiOi (Neff = 3.4⋅⋅⋅⋅1011 cm2) CiCs (Neff = 2.8⋅⋅⋅⋅1011 cm2) Ci (0/-) (Neff = 4.7⋅⋅⋅⋅1011 cm2)

ln (ττττ⋅⋅⋅⋅T2) (K2⋅⋅⋅⋅s)

(kB⋅⋅⋅⋅T)-1(eV-1)

∆∆

E = 0.26 eV σσσ σp = 0.4⋅⋅⋅⋅10-14 (cm2)

∆∆

E = 0.17 eV σ σσ σp = 1.7⋅⋅⋅⋅10-17 (cm2)

Références

Documents relatifs

In this work, low frequency noise measurements versus temperature are used as a device characterization tool in order to evaluate the quality of the gate oxide

The aim of this work is to investigate the low frequency excess noise sources (1/f and Lorentzian spectra) versus temperature as a diagnostic tool in order to characterize the

The aim of this work is to investigate the low frequency excess noise sources (1 f and Lorentzian spectra) versus temperature as a diagnostic tool in order to characterize the

A reasonable correlation between the front-channel LF noise PSD and the front-channel electron mobility has been observed for a set of UTBOX SOI nMOSFETs, which

In this work, low frequency noise measurements versus temperature are used as a device characterization tool in order to identify the defects present in the

Better behaviour of the strained devices has been observed for many electrical parameters at 10 K operation: lower threshold voltage, smaller access

The increase of the noise from weak to strong inversion can be modeled (solid line in Fig. 3) by the carrier number fluctuation correlated to mobility fluctuations (ΔN+Δμ) and

Finally, it can be shown that for an RTS due to a trap in the gate oxide, the analysis of the time constant ratio versus gate voltage [8,17] or drain voltage [18] yields