MAGNETIC TAPE COUPLER INSTRUCTION MANUAL

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MODEL DQ130

MAGNETIC TAPE COUPLER INSTRUCTION MANUAL

January 1984

O I

DISTRI. BUTEO LOGIC CORPORATION

L mm

~5~~ :~xS~~~~ir Street Anaheim. California 92806

I Telephone: (714) 937.5700 Telex: 6836051

Part Number 30002·3

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1 DESCRInION ... 1-1 INTRODUCTION ... 1-1 COUPLER CHARACTERISTICS ... 1-1 LSI-II Q BUS INTERFACE ... 1-2 FORMATTER INTERFACE ... 1-2 TAPE FORMAT COMPATIBILITY ... 1-2 INTERRUP'f ... 1-2 COUPLER SPECIFICATIONS ... 1-4 2 INSTALLATION ... 2-1 INSPECTION ... ~ ... 2-1 PRE-INSTALLATION CHECKS ... , .2-1 INSTALLATION ... 2-1 3 OPERATION ... 3-1 INTRODUCTION ... 3-1 TAPE FORMAT ... 3-1 BOOTING FROM MAGNETIC TAPES ... 3-1 4 PROGRAMMING ... 4·1 PROG RAMMING DEFINITIONS ... 4-1 TAPE COUPLER FUNCTIONS AND REGISTERS ... 4-1 Status Register (MTS) ... 4·2 Command (MTC) ... 4-4 Byte Record Counter (MTBRC) ... 4-5 Current Memory Address (MTCMA) ... 4-5 Data Buffer (MTD) ... 4-6 Tape Read Lines (MTRD) ... ~ .4-6 5 TROUBLESHOOTING AND THEORY ... 5-1 BASIC SYSTEM TROUBLESHOOTING ... 5-1 COUPLER SYMPTOMS ... 5·1 PHYSICAL LAYOUT ... 5-1 TERM LISTING ... ; .... 5-1 THEORY ... '~ .. ; ... 5-5 Computer Interface ... 5·5 Microprocessor ... 5-8 Peripheral Interface ... 5-12 LOGICS

iii

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ILLUSTRATIONS

Figure Page

I-I Tape System With Two Embedded-Formatter Tape Drives ... I-I 1-2 Tape System (Maximum Configuration) Two Embedded-Formatter Tape Drives With Three

Slave Tape Drives Each ... 1-2 2-1 Coupler Configuration ... 2-2 4-1 Controller Register Configurations ... 4-2 5-1 Board Layout ... 5-3 5-2 Simplified Block Diagram ... 5-6 5-3 DATI-Slave, Q Bus ... 5-7 5-4 DATO-Slave, Q Bus Transfers ... 5-7 5-5 DATI-Q Bus DMA Transfers ... 5-8 5-6 DATO-Q Bus DMA Timing ... 5-9 5-7 Interrupt Sequence Timing ... 5-10 5-8 Microinstruction Word ... 5-11

Table I-I 1-2 1-3 1-4 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8

iv

TABLES

Page Coupler/Q-Bus Interface Lines ... 1-3 Coupler Connector J1 to Formatter Interface Lines ... 1-4 Coupler Connector J2 to Formatter Interface Lines ... 1-4 Coupler to Formatter Connector Correlation ... 1-4 Function Codes ... 4-1 Coupler Symptoms ... 5-2 Term Listing ... 5-4 Coupler Buses ... 5-10 Coupler Register Storage ... 5-10 Control Inputs To 2901 . . . 5-11 Status Register Bits ... 5-11 Address Modification Conditions ... 5-12 Information Sources to D Bus ... 5-12

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SECTION 1 DESCRIPTION

INTRODUCTION

This manual describes the installation. operation.

programming. troubleshooting and theory of operation of Distributed Logic Corporation (DILOG) Model DQ130 Magnetic Tape Coupler. The coupler interfaces DEC· LSI-II based computer systems to Industry-Standard formatted magnetic tape drives.

The coupler and the drive comprise a complete LSI -11 compatible 9-track magnetic tape subsystem. Magnetic tape drives from manufacturers other than DEC can be used while still retaining software and format compatibility with the DEC TM-ll Tape System. Data transfers are via the DMA facility of the LSI·l1. Transfer rates vary.

depending upon the density and speed of the drives included in the system, between 10,000 and 200,000 characters per second. The complete coupler occupies one quad module in the backplane.

COUPLER CHARACTERISTICS

Up to two embedded-formatter tape drives or external stand-alone tape formatters may be connected to the coupler. Each embedded-formatter tape drive is capable of handling an additional three slave drives. All Industry-Standard. external stand- alone formatters are capable of handling up to four drives. The coupler can accommodate up to eight

-DEC is a registered trademark of Digital Equipment Corporation.

CONTROL 22

DATA ADDRESSl16

EXTENDED ADDRESS/2 POWER·GROUND

w o

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oLi.

-0::

-w

~

o 0::

en en w o

o 0::

Q, o

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TAPE COUPLER

drives. Figures 1-1 and 1-2 illustrate two configura tions.

The optimal usage of the coupler is in situations where 9-track. dual density, 800/1600/3200 bpi tape recording capabilities are required; however, the coupler is compatible with single density 800, 1600 or 3200 bpi embedded-formatter tape drives or stand-alone external formatters.

The primary functions of the coupler in a magnetic tape subsystem are to buffer and interlock data and status transfers between the computer 110 bus and the tape formatter. and to translate CPU commands into tape formatter control signals such as Start, Stop, Rewind, Generate IR Gap, Generate EOF Gap. The primary function of the formatter is to control tape motion, establish data format, and perform error checking. The overall tape control function is a combination of the coupler functions, which are related to the LSI-II, and the formatter functions, which are related to the tape drives.

A microprocessor is the sequence and timing center of the coupler. The control information is stored as fumware instructions in Programmable Read-Only Memory (PROM) on the coupler board.

One section of the PROM contains a diagnostic program that tests the functional operation of the coupler. This self-test is performed automatically each time power is applied or whenever an INIT command is issued on the CPU I/O bus. A green

FORMATTER I/O BUS

EMBEDDED FORMATTER TAPE DRIVE .1

EMBEDDED FORMATTER TAPE DRIVE .2

LSI·11

a BUS Figure 1-1. Tape System With Two Embedded-Formatter Tape Drives

I-I

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~ ~

~ _ CONTROL 22 •

%- -

~

~ DATA ADDRESS/16 ~

~- 2 ^~~

~ ~

~ _ EXTENDED ADDRESS/2 •

% -- --=.J

~ POWER·GROUND J

a: o en en

W U o

a: Cl.

o a:

u ~

T APE COUPLER a:w Wu

I-c(

I-I.L

c(a:

a: ~w I-

Oz I.L-

~ ~

~

' - - - _ . _ - - - _ . __ ._-- LSI·l1

a BUS

FORMAnER 110 BUS

, I

EMBEDDED EMBEDDED

FORMAnER FORMAnER

~ - - - -+- ~ - - - --14-

MASTER MASTER

TAPE DRIVE TAPE DRIVE

SLAVE en SLAVE en

TAPE ~ ^::;) ^TAPE ~ ^::;)

DRIVE ^CD DRIVE ^CD

g g

W W

> >

Ii Ii

SLAVE ⁰ SLAVE ⁰

TAPE f+- ^Cl.^W ^TAPE ^f4- ^W^Cl.

DRIVE ^c(l - DRIVE ^c(I-

SLAVE SLAVE

TAPE _~ TAPE 4-

DRIVE DRIVE

Figure 1-2. Tape System (Maximum Configuration) Two Embedded-Formatter Tape Drives With Three Slave Tape Drives Each

diagnostic indicator on the board lights if self-test passes. If self-test fails. the coupler has an auto- matic data protect feature that stops the CPU from interacting with the tape formatter. and thus pre- vents writing erroneous information into critical data base areas.

Two additional indicators on the coupler board display dynamic operating conditions to an operator. The conditions displayed are Coupler Busy and Coupler Transferring Data (DMA Busy).

LSI-II Q BUS INTERFACE

Commands. data and status transfers between the coupler and the computer are executed via the parallel 110 bus (Q Bus) of the computer directly to memory. via the DMA facility of the Q Bus.

Coupler/Q Bus interface signals are listed in Table I-I.

FORMATTER INTERFACE

The coupler interfaces with the formatted tape drives through two 50-pin nat cable connectors at the top of the coupler board. The maximum cable length between coupler and formatter is 25 feet.

Coupler/formatter interface signals are listed in Tables 1-2 and 1-3.

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Table 1-4 lists some manufacturers and connector correlations.

CAUTION

Cable cunnections and interface signals .'lhould be checked from the drive manu- facturers' manuals to ensure the latest configurations are installed currectly. In- correct cabling may cause damage to the coupler or the drive.

TAPE FORMAT COMPATIBILITY

The coupler can cause the formatter to create a tape in an IBM format. By cutting an etch. the high byte will be written first followed by the low byte.

With a jumper (etch) installed. the format will be low byte first followed by the high byte. The tape can be created on the DEC system and run and read on another system.

INTERRUPT

The interrupt vector address is factory set to address 224, which is compatible with TM-ll software. Interrupts are generated when processor attention is required or when an error occurs.

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Table 1·1. Coupler/Q·Bus Interface Lines

Controller InputJ

Bus Pin Mnemonic Output Description

AJ1, AM1, Rn, BJ1, BM1, GND 0 Signal Ground and DC return.

BT1, BC2, CJ1. CM1, CT1.

CC2. DJ1, DM1. DT1. DC2

AN1 BDMR L a Direct Memory Access (DMA) request from coupler: active low.

AP1 BHALT L N/A Stops program execution. Refresh and DMA are enabled.

Console operation is enabled.

AR1 BREF L N/A Memory Refresh.

BA1 BDCOK H I DC power OK. All DC voltages are normal.

BB1 BPOK H N/A Primary power OK. When low activates power fail trap sequence.

BN1 BSACK L 0 Select Acknowledge. Interlocked with BDMGO indicating

coupler is bus master in a DMA sequence.

BR1 BEVNT L N/A External Event Interrupt Request.

BV1.AA2.BA2.CA2,DA2 +5 I + 5 volt system power.

AD2. BD2 + 12 N/A + 12 volt system power.

AE2 BDOUT L 110 Data Out. Valid data from bus master is on the bus. Interlocked with BRPLY.

AF2 BRPLY L 110 Reply from slave to BDOUT or BDIN and during IAK.

AH2 BDIN L 110 Data Input. Input transfer to master (states master is ready for data). Interlocked with BRPLY.

AJ2 BSYNC L I/O Synchronize: becomes active when master places address on bus: stays active during transfer.

AK2 BWTBT L 110 Write Byte: indicates output sequence to follow (DATa or DATOB) or marks byte address time during a DATOB.

AL2 BIRO L 0 Interrupt Request.

AM2 BIAK11 L I Serial Interrupt Acknowledge input and output lines routed from AN2 BIAK10 L 0

o

Bus. through devices, and back to processor to establish an

CM2 BIAK21 L I interrupt priority chain.

CN2 BIAK20 L 0

AT2 BINIT L I Initialize. Clears devices on ·110 bus.

AU2. AV2. BE2. BF2. BH2. BDALO L

BJ2. BK2. BL2, BM2. BN2. through 110 Data/address lines. 0·15 BP2. BR2. BS2. BT2. BU2. BDAL15 L

BV2

AR2 BDMG11 L I DMA Grant Input and Output. Serial DMA priority line from AS2 BDMG10 L 0 computer. through devices and back to computer.

CR2 BDMG21 L I

CS2 BDMG20 L 0

AP2 BBS7 L I Bank 7 Select. Asserted by bus master when address in upper 4K bank is placed on the bus.

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Table 1-2. Coupler Connector Jl Formatter Interface Lines

J1 J1

Signal Return Mnemonic Description

1 FRDP Read Data Parity

2 FRDO Read Data 0

3 FRD1 Read Data 1

4 FLOP Load Point

6 5 FRD4 Read Data 4

12 11 FHER Hard Error

14 13 FFMK File Mark

16 15 FCC Gil 0 CCG/IDENT

18 17 FFEN Formatter Enable

22 21 FEOT End of Tape

24 23 FOFL Off Line

26 25 FNRZ NRZI

28 27 FRDY Ready

30 29 FRWD Rewinding

32 31 FFPT File Protect

34 33 FRSTR Read Strobe 36 35 FDWDS Demand Write Data

Strobe

38 37 FDBY Data Busy

40 39 Not Used

42 41 FCER Corrected Error

44 43 FONL On·Line

46 45 FTAD1 Transport Address 1 48 47 FFAD Formatter Address 50 49 FDEN Speed/Density Select

Table 1-3. Coupler Connector J2 to Formatter Interface Lines

J2 J2

Signal Return Mnemonic Description

2 1 FFBY Formatter Busy

4 3 FLWD Last Word

6 5 FWD4 Write Data 4

8 7 FGO Initiate Command

10 9 FWDO Write Data 0

14 13 Not Used

16 15 FLOL Load on Line

18 17 FREV Reverse/Forward

20 19 FREW Rewind

22 21 FWDP Not Used

34 33 FWRT Write/Read

36 35 FRTH2 Read Threshold 2 FLGAp·

38 37 FEDIT Edit

40 39 FERASE Erase

42 41 FWFM Write File Mark 44 43 FRTH1 Read Threshold 1

(SPARE)

46 45 FTAOO Transport Address 0

50 49 FR03 Read Data 3

·Signal applicable to CDC Keystone drives.

1-4

Table 1-4. Coupler to Formatter Connection Correlation

Coupler Connector J1 to:

Manufacturer Model Connector

CDC 9218X J5

Cipher F880 P2

F100X, F900X P5 (Adapter required)

Digi·Data Formatted JD

lOT 1012 J2

1050 J125

Kennedy 6809 Streamer J2

Formatted J1

Pertec Formatted P5

External Formatter P5 (Adapter required)

Coupler Connector J2 to:

Manufacturer Model Connector

CDC 9218X J4

Cipher F880 P1

F100X. F900X P4 (Adapter required)

Oigi·Data Formatted JC

lOT 1012 J1

1050 J124

Kennedy 6809 Streamer J1

Formatted J5

Pcrtec Formatted P4

External Formatter P4 (Adapter required)

COUPLER SPECIFICATIONS·

Data Format

• Industry-Standard non-return-to-zero (NRZ) or Phase Encoded (PE) recording.

• 9 tracks

Recording densities:

• 800 characters per inch

• Interrecord gap 0.60 inch min.

• Tape parity marks: LPC. CRC. LRC Media Characteristics

Type

• 1/2 " wide mylar base. oxide coated, magnetic tape.

Reel Size

• 7", Blf2", or 10lf2" diameter tape reels containing 600, 1,200 and 2,400 feet of tape

respectively.

Data Capacity (megabytes)

• Assumes aproximate BO% recording efficiency:

600 Ft.

1.200 Ft.

2.400 Ft.

BOO CPI 1600 CPI 3200 CPI 5.75

11.5 22.0

11.5 23.0 44.0

23.0 46.0 BB.O

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Data Transfer Rate (Characters/Second)

800 CPI 1600 CPI 3200 CPI 12.5 ips

=

^10,000 ^20,000 ^20,000

25.0 ips

=

^20,000 ^40,000 ^40,000

37.5 ips

=

^30,000 ^60,000 ^60,000

45.0 ips

=

^36,000 ^72,000 ^72,000

75.0 ips

=

^60,000 ^120,000 ^120,000

125.0 ips

=

^100,000 ^200,000 ^200,000

Register Address

• Status (MTS) 772 520

• Command (MTC) 772 522

• Byte Record Counter (MTBRC) 772 524

• Current Memory Address (MTCMA) 772 526

• Data Buffer (MTD) 772 530

• Tape Read Lines (MTRD) 772 532 Computer Interface

• Interrupt Vector Address 224. DMA data transfer. 1 bus load all lines.

Coupler/Formatter Interface

• Coupler is compatible with formatters manu- factured by Pertec, Kennedy, Tandberg, Cipher, CDC, Digi-Data.

Packaging

• The coupler is completely containedonone quad module 10.44 inches wide by 8.88 inches deep.

Documentation

• One instruction manual is supplied' with the coupler.

Software

• One diagnostic routine with object listing is supplied with a coupler (or the first of a series of couplers).

Power

• +5, ±0.25 VDC at 3.6 amps, from computer backplane.

Environment

• Operating temperature 40°F to 140°F

• Operating humidity 10% to 95% non- condensing.

Note

The quality of recording and reading information on magnetic tape is affected by temperature and humidity. The area where the tape is used should be main- tained within the following limits:

. Temperature: 60 of to 90 of

Humidity: 20% to 80%

Shipping Weight

• 5 pounds including documentation.

·Specifications subject to change without notice.

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SECTION 2 INSTALLATION

INSPECTION

The padded shipping carton that contains the coupler board also contains an instruction manual and cables to the magnetic tape drives (if this option is exercised). The coupler is completely contained on one quad-size printed circuit board. The drive (or drives). if supplied. is contained in a separate shipping carton. Inspect the coupler and cable(s) for damage.

CAUTION

If damage to any of the components is noted, do not instalL Immediately inform the carrier and DILDO.

Installation instructions for the tape drive are contained in the tape drive manual. Before install- ing any components of the magnetic tape system.

read Sections 1. 2 and 3 of this manual. Figure 2-1 illustrates the configuration of the coupler.

PRE-INSTALLATION CHECKS

There are various LSI-II configurations for LSI -11 based systems. Certain configurations require minor modifications before operating the magnetic tape system. These modifications are as follows:

A. If the system contains a REVIl-C module. it must be placed closer to the processor module (higher priority) than the coupler if the DMA refresh logic on the REVll-C is enabled.

B. If the 4K memory on the DKll-F is not used and the memory in the system does not require external refresh. the DMA refresh logic on the REV ll-C should be disabled by removing jumper W2 on the REVll-C

module. .

C. If the system contains a REVll-A module.

the refresh DMA logic must be disabled since the module must be placed at the end of the bus (REVII-A contains bus terminator).

D. If the REVll-C module is installed, cut the etch to pin 12 on circuit D30 (top of board)

and add a jumper between pin 12 and pin 13 of D30.

E. If the system requires more than one backplane. place the REV-II terminator in the last available location in the last backplane.

INSTALLATION

To install the coupler module. proceed as follows:

CAUTION

Remove DC power from mounting assem- bly before inserting or removing the coupler module.

Damage to the backplane assembly may occur if the coupler module is plugged in backwards.

1. Select the backplane location into which the coupler is to be inserted.

There are several backplane assemblies available from DEC and other manufacturers. Figure 2-2 shows typical backplane configurations. Note that the processor module is always installed in the first location of the backplane or in the first location in the first backplane of multiple backplane systems.

It is important that all option slots between the processor and the coupler be filled to ensure that the daisy-chained interrupt (BIAK) and DMA (BDMG) signals be complete to the coupler slots. If there must be empty slots between the coupler and any option board, the following backplane jumpers must be installed:

FROM TO SIGNAL

CO x NS CO x M2 BIAKlILO CO x S2 CO x R2 BDMGlILO

t ^t

Last Full Coupler Slot Option Slot

2. Ensure the switch and jumpers are as shown in Figure 2-1.

2-1

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2·2

PIN 1

A711 _...-

NON·STREAM

1 _ 1

- - - -

... _ ... - - - 10.5

V1

BUSY~ _DMA~ ^??

DIAG

OE5- E13 0 E6

A1

-When jumper is installed at E13. coupler writes DEC Format (low byte first. high byte second).

When jumper is removed at E13. coupler writes IBM format (high byte first. low byte second).

LOCATION A7

Stream Switch OFF Stream Switch ON-

Logical Physical Logical Physical

Unit Formatter Drive Unit Drive

Addressed Addressed Addressed Addressed Mode Addressed

0 0 0 0 Stop/Start 0

4 1 0 4 Streaming 0

5 1 1 5 Streaming 1

6 1 2 6 Streaming 2

7 1 3 7 Streaming 3

- Formatter Addressed Always O.

Older coupler boards (Rev. E and earlier) contain Jumpers El. E2. E3 and E4 at Location A7. rather than the STREAM switch (Rev. F and later). The older boards operated only in an 18-bit addressing mode: the newer ones are capable of 22-bit addressing. For the older boards to operate in the Streamer mode. the following changes must be made:

Factory Set Start/Stop Mode:

To Operate In Streamer Mode:

El 0

?

^E3

E2

r/

⁰ E4

Figure 2·1. Coupler ComiguratioD

8.9

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LOCATION A

E

2 3 4

PREFERRED COUPLER LOCATION

B C

OPTION 2 OPTION 3 OPTION 6

D

OPTION 1 OPTION 4 OPTION 5

PROCESSOR MODULE ,.

." .

COMPONENT SIDE

t

SOLDER SIDE

!

H9270 MODULE INSERTION SIDE

POWER TERMINA BLOCK

+12V

-

0

-5V

..iL

+5V

~-

+5VB 0

GND g

-:...-

GND ~

-12V ~

L /

PREFERRED

COUPLER LOCATION A

OPTION 2 OPTION 3 OPTION 6 OPTION 7 OPTION 10 OPTION 11 OPTION 14 OPTION 15

B C 0

OPTION 1 OPTION 4 OPTION 5 OPTION 8 OPTION 9 OPTION 12 OPTION 13 OPTION 16

V

"

PROCESSOR

/MODUL

E F

I

E

2 3 4

5 6 7 8 9

/

DDVll . B BACKPLANE MODULE INSERTION SIDE

USER DEFINED SLOTS NOTE

MEMORY CAN BE INSTALLED IN ANY SLOT; IT IS NOT PRIORITY DEPENDENT AND DOES NOT NEED TO BE ADJACENT TO THE PROCESSOR.

CONTROLLERS ARE ALSO COMPA TlBLE WITH H9273A MODULES.

Figure 2-2. Typical Backplane Configuration

3. If the formatter is equipped with a IOO-pin connector, adapter part number ACC993A must be used to convert the IOO-pin connector to two 50-pin connectors. Adapter part number ACC993B is used for 72-pin connectors.

4. Ins~r~ the coupler into the selected backplane posItIon. Be sure the coupler is installed with the components facing row one, the processor.

The coupler module is equipped with handles on the side opposite the slot connectors. Gently position the module slot con-

nectors into the backplane then press until the module connectors are firmly seated into the backplane. Both handles must be pressed simultaneously. When removing the module, apply equal pulling pressure to both handles.

5. Feed the module connector end of the tape drive cable(s) into the coupler module connector(s). Install the cable connector(s) into the module connector(s}. Verify that the connector(s) are fll'mly seated.

6. Connect the drive end of the I/O cables to the drive 110 connectors.

2·3

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2-4

7. Apply power to the computer and verify that the green diagnostic LED indicator on the coupler board is lighted. If the DIAG LED is not lighted. either power is not applied to the coupler. the coupler board is bad. or the LED is bad.

8. Refer to the tape drive manual for operating instructions and apply power to the tape drive. Install a known good reel of tape on the tape drive and place the tape drive ON LINE.

9. Place the computer in the HALT mode to enable ODT. Using the computer terminal examine location 772 520. The contents of this location should be 000 141. These are the tape drive status bits signifying: ON LINE.

BEGINNING OF TAPE, and TAPE UNIT READY.

10. Using the computer console device, deposit 60007 into location 772 522. The tape should move forward approximately 6 inches and stop. A file mark should have been written on the tape. Examine location 772 520. The contents of this location should be 040 101 signifying that a file mark has been written and detected.

11. Refer to the D ILOG software manual and run the diagnostics.

12. The tape system is now ready for data transfer operations.

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SECTION 3 OPERATION

INTRODUCTION

Prior to operating the system, the instruction manual sections describing the controls and indicators on the tape drive and procedures for mounting and removing tape reels should be read. To prevent loss of data or damage to the magnetic tape, the following precautions should be observed:

a. Always handle a tape reel by the hub hole.

Squeezing the reel flanges can cause damage to the tape edges when winding or unwinding tape.

b. N ever touch the portion of tape between the BOT and EOT markers. Oils from fingers attract dust and dirt. Do not allow the end of the tape to drag on the floor.

c. Never use a contaminated reel of tape. This spreads dirt to clean tape reels and can affect tape drive operation.

d. Always store tape reels inside their containers. Keep empty containers closed so dust and dirt cannot get inside.

e. Inspect tapes, reels, and containers for dust and dirt. Replace take-up reels that are old or damaged.

f. Do not smoke near the tape drive or tape storage area. Tobacco smoke and ash are especi- ally damaging to tape.

g. Do not place the tape drive near a line printer or other device that produces paper dust.

h. Clean the tape path frequently.

Note that tape drives permit off-line or on-line operation. The off-line mode is controlled by

switches on the tape drive. The on-line mode is controlled by programmed commands from the computer via the coupler and formatter. When system operation is desired, be sure the tape drive ON- LINE indicator is lit. On-line operation is a function of program commands described in Section 4 of this manual.

TAPE FORMAT

For detailed information on tape format characteristics see formattter and tape drive manuals.

BOOTING FROM MAGNETIC TAPES

1. Place the tape transport "ON LINE" and position the tape at "Beginning of Tape."

2. Load Register location 772 5228 with 10000₈,

3. Load Register location 772 5248 with 1777778 (-1).

4. Load Register location 772 5228 with 600118, The tape will jump forward and halt.

5. Load Register location 772 522_Rwith 600038, The tape will jump forward and halt.

6. Load PSW ($S) with 350₈,

7. Load PC (R7) with O.

8. Type "P" to start.

STREAMING TAPE TRANSPORTS

With the STREAMING switch on, the tape drive will function in the low-speed STOP/START mode when addressed as logical unit number 0, when addressed as logical unit number 4, the streamer will function in the high-speed, streaming mode.

3-1

/

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SECTION 4 PROGRAMMING

PROGRAMMING DEFINITIONS

FUNCTION: The expected activity of the tape system (read. write. rewind).

COMMAND: The instruction which initiates a function.

INSTRUCTION: One or more orders executed in a prescribed sequence that cause a function to be performed.

ADDRESS: The binary code placed on the BDALO-BDAL21 lines by the bus master to select a register in a slave device. Note that "register" can be either discrete elements (flip flops) or memory elements (core. solid state RAM or ROM). When addressing devices other than computer internal memory. i.e .• peripheral device registers. the upper 8K bytes address space is used.

REGISTER: An associated group of memory elements that react to a single address and store information (status. control. data) for use by other assemblies of the total computer system.

TAPE COUPLER FUNCTIONS AND REGISTERS

The tape coupler performs eight functions. A function is initiated by a Go command after the pro-

cessor has issued a series of instructions that store function-control information into coupler registers.

To accept a command. and perform a function. the coupler must be properly addressed and the tape drives must be powered up. at operational speed.

and be ready.

All software interaction between the coupler. the processor. and processor memory is accomplished by seven registers in the tape coupler. These registers are assigned memory addresses and can be read or written into (except as noted) by instructions that reference respective register addresses. A summary of the registers, their addresses.

mnemonics, and their bit assignments are shown in Figure 4-1.

Table 4-1. Function Codes

BIT 3 BIT 2 BIT 1 BIT 0(80) Octal

0 0 0 0 00 ^{Off line}

0 0 1 1 11 Read

0 1 0 1 05 Write

0 1 1 1 07 Write EOF

1 0 0 1 10 Space Forward

1 0 1 1 13 Space Reverse

1 1 0 1 15 Write with Extended Interrecord Gap

1 1 1 1 17 Rewind

4-1

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BIT POSITION MSB lSB 15 14 13 12 11 10 09 08

I

⁰⁷

I

⁰⁶

I

⁰⁵

I

⁰⁴ ⁰³ ⁰² ⁰¹ ⁰⁰

STATUS (MTS)

772520 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

III

COM EOF PRE BGl EOT RlE NXM SELR BOT 7CH

ISONN

WRL RWS TUR COMMAND (MTC)

772522

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

DEN DEN PWR INT XBA XBM

ERR 8 5 CLR PEVN US2 US1 USO CUR ENB 17 16 FU2 FU1 FUO GO

BYTE RECORD COUNTER 15 00

(MTBRC)

772524 BYTE COUNT

CURRENT MEMORY 15 00

(MTCMA)

772526 MEMORY ADDRESS

DATA BUFFER (MTD) 15 14 13 12 11 10 09 08 00

772530

DATA BUFFER TAPE READ LINES (MTRD)

772532 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

TIM

Figure 4-1. Register Summary

STATUS REGISTER (MTS) 772520

The address of the MTS register is 772 520. MTS is a read-only register. The functions of the bits of this register are as follows:

BIT(S) 00

DESCRIPTION

TAPE UNIT READY (TUR): This bit is set when the tape unit is ready and is not rewinding. This bit is cleared when the processor sets the GO bit and the operation defined by the function bit occurs.

01 REWIND STATUS (RWS): This bit is set by the coupler as soon as it receives a Rewind command from the processor. It is cleared by the coupler as soon as the tape arrives at the BOT marker in the forward direction. (It overshoots BOT in the reverse direction.)

02 WRITE LOCK (WRL): This bit is set to prevent the control unit from writing information on tape.

It is controlled by the presence or absence of the write protect ring on the tape reel.

03 TAPE SETTLE DOWN (SDWN): This bit is set whenever the tape unit is slowing down. The coupler will accept and execute any new command during the SPWN period except when the new command is to the same tape unit as the one issuing SDWN, and if the direction implied in the new command is opposite to the present direction.

4-2

(17)

04 SEVEN CHANNEL (7CH): This bit is set to indicate a 7 -channel tape unit; cleared. it indicates a 9-channel unit.

05 BEG INNING OF TAPE (BOT): This bit is set when the BOT marker is read. and cleared when the BOT marker is not read. BOT at a 1 does not produce a 1 in the ERR bit.

06 SELECT REMOTE (SELR): This bit is cleared when the tape unit addressed does not exist. is off- line. or has its power turned off.

07 NON-EXISTENT MEMORY (NXM): This bit is set during DMA operations when the control unit is bus master, and is performing data transfers into and out of the bus, when the control unit does not receive a slave Sync signal within 10 microseconds after it has issued a master Sync

signal. The operations which occur when the error is detected are identical to those indicated for the BGL error.

08 BAD TAPE ERROR (BTE): NOT USED.

09 RECORD LENGTH ERROR (RLE): This bit is detected only during a Read operation. It occurs for long records only, and is indicated as soon as MTBRC increments beyond 0, at which time both data transfer into memory and incrementing of the MTCMA and MTBRC stop.

However, the control unit reads the entire record and sets the ERR bit when the LPC character is read. CU Ready remains at 0 until the LPC character is read.

10 END OF TAPE (EOT): This bit is set when the EOT marker is read while the tape is moving in the forward direction. The bit is cleared as soon as the same point is read while the tape is moving in the reverse direction. The ERR bit, as a result of the EOT bit at a 1, sets only in the tape forward directio!l and coincidentally with the reading of an LPC character.

11 BUS GRANT LATE (BGL): This bit is set when the control unit, after issuing a request for the bus, does not receive a bus grant before the coupler receives the bus request for the following tape character. The condition is tested only for NPR (Non-Processor Request) operations. The ERR bit sets simultaneously with BGL, thus terminating the operation. If the BGL occurred during a Write or Write With Extended IRG operation, the control unit does not send the signal WDS to the master, while the master writes the CRC character (if required) and LPC character onto the tape, terminating the record.

12 HARD ERROR (HE): This bit is set as the result of an error being detected on tape.

For all errors, the ERR bit sets at the end of the record. Both lateral and longitudinal parity errors are detected during Read, Write, Write EOF and Write With Extended IRG operations. The entire record is checked. including the CRC and LPC characters. During a Write operation a correctable error in the PE (1600 bpi) mode will set this bit.

13 NOT USED.

14 END OF FILE (EOF): This bit is set when an EOF character is detected during a Read, Space Forward, or Space Reverse operation. During the Read or Space Forward operation, the EOF bit is set when the LPC (Longitudinal Parity Check) character following the EOF character is read.

During a Space Reverse operation, the EOF bit is set when the EOF character following its LPC character is read. The ERR bit sets when the LPC character strobe is generated with the File Mark signal upon EOF detection.

15 ILLEGAL COMMAND (ILL COM): This bit is set by any of the following illegal commands:

1. Any DATO or DATB to the command register during the tape operation period.

2. A Write, Write EOF, or Write With Extended IRG operation when the File Protect bit is a 1.

3. A command to a tape unit whose Select Remote bit is O.

4. The Select Remote (SELR) bit becomes a 0 during an operation.

In error conditions 1 through 3, the command is loaded into the MTC, but the GO pulse to the tape unit is not generated. In addition, the

eu

Ready bit remains set.

4·3

(18)

COMMAND (MTC)

772522

,

12 \ 11

r

15 14 13 10 09 ,

08 07 06

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⁰⁵ ⁰⁴ ⁰³ ⁰² ⁰¹ ⁰⁰

't

DEN DEN PWR INT XBA XBM

ERR 8 5 CLR PEVN US2 US1 USO CUR ENB 17 16 FU2 FU1 FUO GO The address of MTC is 772 522. The functions of

the bits of this register are as follows:

BIT(S) 00 01-03

04-05

06

07

OS-09

10

11 12

13-14 15

4-4

FUNCTION

GO: When set, this bit begins the operation defined by the function bits.

FUNCTION BITS: Selects I of S functions (programmable commands).

BIT 3 BIT 2 BIT 1

o

⁰ ⁰ Off-Line/Rewind

o

0 1 Read

o

1 0 Write

o

1 1 Write EOF

I 0 0 Space Forward

1 0 1 Space Reverse

1 I 0 Write With Extended Interrecord Gap

1 1 I Rewind

ADDRESS BITS: These are extended memory bits for an IS-bit bus address. Bit 5 corresponds to XBAI7, and bit 4 to XBAI6. They are an extension of the MTCMA, and increment during a tape operation if there is a carry-out of MTCMA.

INTERRUPT ENABLE (lNT ENB): When this bit is set, an interrupt occurs whenever either the CU Ready bit or the ERR bit changes from 0 to 1, or whenever a tape unit that was set into rewind has arrived at the beginning of the tape. In addition, an interrupt occurs on an instruction that changes the INT ENB from 0 to I and does not set the GO bit, i.e., CU READY or ERROR

=

^1.

CU READY (CUR): This bit is cleared at the start of a tape operation, and set at the end of a tape operation. The control unit accepts as legal, all commands it receives while the CU Ready bit is a 1.

UNIT SELECT 1: These bits specify one of the four possible magnetic tape units. All operations defined in the MTC and all status conditions defined in the MTS pertain to the unit indicated by these bits. They are cleared by INIT.

UNIT SELECT 2: This bit specifies one of two possible formatters. When the STREAM switch is OFF (see Section 2), and the bit is 0, the formatter addressed is unit 0; if the bit is I, the formatter addressed is unit 1. When the STREAM switch is ON and the bit is 0, the mode is START/STOP; if the bit is 1, the mode is STREAMING. If the switch is ON, the formatter addressed is always unit

o.

LATERAL PARITY (PEVN): NOT USED. This bit is not applicable for 9-track tape.

POWER CLEAR (PWRCLR): This bit provides the means for the processor to clear the control unit and tape units without clearing any other device in the system. The PWR CLR bit is always read back by the processor as a

o.

DENSITY (DEN S, DEN 5): NOT USED. These bits are not applicable for 9-track tape.

ERROR (ERR): This bit is set as a function of bits 7-15 of the Status Register MTS. It is cleared by INIT or the GO command to the tape unit.

(19)

BYTE RECORD COUNTER (MTBRC) 772524

15 00

BYTE COUNT

The MTBRC is a 15-bit binary counter which is used to count bytes in a Read, Write, or Write With Extended IRG operation, or records in a Space For- ward or Space Reverse operation. When used in a Write or Write With Extended IRG operation, the MTBRC is initially set by the program to the 2's complement of the number of bytes to be written on tape. The MTBRC becomes 0 after the last byte of the record has been read from memory. Thus, when the next WDS (Write Data Strobe) signal occurs from the master, the control unit will not send the WDR (Write Data Request) signal to the master, indicating that there are no more data characters in the record.

When the MTBRC is used in a Read operation, it is set to a number equal to or greater than the 2' s complement of the number of bytes to be loaded into memory. A Record Length Error (RLE) occurs for long records only, and is indicated when a read pulse

CURRENT MEMORY ADDRESS (MTCMA) 772526

15

for data (RDS occurring when CRC's or LPC's do not occur) occurs when the MTBRC is

o.

The MTBRC increments by 1 immediately after each memory access.

When the MTBRC is used in a Space Forward or Space Reverse operation, it is set to the 2' s complement of the number of records to be spaced. It is incremented by 1 at LPC time, whether the tape is moving in the forward or reverse direction. A new GO pulse is sent to the tape unit during the SDWN time if the MTBRC is not 0 during that time. When the tape unit is moving in the reverse direction, the LPC character is detected before SDWN, and before the entire record has been traversed. Thus, both SDWN and the LPC character appear to be in differ- ent positions on the tape from the positions apparent when the tape unit is moving in a forward direction.

00

[

MEMORY ADDRESS

The MTCMA contains 16 of the possible 18 memory address bits. It is used in DMA operations to provide the memory address for data transfers in Read, Write, and Write With Extended IRG operations. Before issuing a command, the MTCMA is set to the memory address into which the first byte is loaded in a Read operation, or from which the first byte is read in a Write, or Write With Extended IRG operation. The MTCMA is incremented by 2 immediately after each memory access. Thus, at any instant of time, the MTCMA points to the address that is next higher than the one which had been

most recently accessed. When the entire record has been transferred, the MTCMA contains the address plus 2 of the last characters in the record. In the error conditions Bus Grant Late (BG L) and N on- Existent Memory (NXM), the MTCMA contains the address of the location in which the failure occurred.

The MTCMA is available to the processor on a DATI, except bit 0 which always reads as a zero under program control. Bit 0 can be asserted during DMA to determine the selected byte. The bits are set or cleared on a processor DA TO. INIT clears all bits in the MTCMA.

4-5

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DAT A BUFFER (MTD) 772530

15 14 13 12 11 10 09 08

The data buffer is an 8-bit register which is used during a Read, Write, or Write With Extended IRG operation. In a Read operation, the data buffer is a temporary storage register for characters that are read from tape before being stored in memory. In a processor read. all nine bits are stored in memory.

Bits 0 through 7 in memory correspond to channels 7 through 0, respectively, from tape, and bit 8 corresponds to the parity bit. In a DMA operation only the data bits are read into memory, and are alter- nately stored in the low and high bytes. In a Write or Write With Extended IRG operation, the data buffer is a temporary storage register for characters that are read from core memory before they are written on tape.

TAPE READ LINES (MTRD) 772532

00 DATA BUFFER

In a Read operation, the LPC character enters the data buffer when bit 14 of MTRD is a 1, and is inhibited from doing so when bit 14 is a O. Thus, after reading a nine-channel tape, the data buffer contains the LPC character when bit 14 is a 1, and the CRC character when bit 14 is a O. After reading an EOF character, the data buffer contains all O's when bit 14 is a 1, and the LPC character when bit 14 is a O. The MTD is available to the processor on a DATI. Bits 9 through 15 are read identically to bits 1 through 7, respectively. Bits 0 through 7 are set or cleared on a processor DATA. Bits 8 through 15 are not affected by a processor DATO. INIT clears all bits in the MTD.

15 14 13 12 11 09 08 07 06 05 04 03 02 01 00

CRCI NOT

TIM LPC USED GS NOT USED P

The memory locations allocated for the tape read lines are:

BIT(S) DEFINITION

00-07 Channels 7-0 respectively.

08 Parity Bit.

09-11 NOT USED.

12 Gap Shutdown Bit.

13 NOT USED.

14 CRC, LPC Character Selector.

15 Timer.

For correct longitudinal parity, bits 0-8 are 0 after writing a record or reading a record from tape. For a longitudinal parity error, one or more of the bits 0-8 remain 1 's, indicating the channel(s) containing the error, which sets the CU Ready bit. Thus, if the pulse is set during a tape operation, CU Ready sets prematurely, producing the gap shutdown period while characters are still being read. Bits 0-8 are set and cleared by the tape unit. Bit 14 is set and 4-6

CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7

cleared by the processor or cleared by INIT. Bit 15 is uniquely controlled by the 100-microsecond timer.

The MTRD is available to the processor on a DATO, except that bit 13 reads back as a O.

TIM (Timer) is a 10-kHz signal with a 50% duty cycle. The signal is used for diagnostic purposes in measuring the time duration of the tape operations.

The timer is read as bit 15 in the MTRD.

(21)

SECTION 5 TROUBLESHOOTING AND THEORY

This section describes troubleshooting procedures at three levels of complexity: basic System9 coupler symptoms and detailed analysis. Basic system troubleshooting procedures are visual checks not requiring test equipment and may be performed by the operator. Coupler symptom procedures may require a SCOpe9 meter, extender board or diagnostics and should be performed by a technician.

Detailed analysis is troubleshooting at the IC level, and is presented for engineers or system analysts for coupler evaluation. The latter method may require the use of test equipment and the material presented here: board layout, term listing, theory of operation and logic diagrams.

CAUTION

Any troubleshooting requires a familiar- ity with the installation and operation procedures in this manual, the appropri- ate DEC manual, and the tape drive manufacturer '$ manuaL Ensure power is off when connecting or disconnecting the board or plugs.

BASIC SYSTEM TROUBLESHOOTING

The following should be checked before power is applied:

1. Verify that all signal and power cables are properly connected. Ribbon cable connectors are not keyed. The arrows on the connectors should be properly aligned.

2. Verify that all modules are properly seated in the computer and are properly oriented.

The following should be checked during or after application of power:

1. Verify that the computer and tape drive generate the proper responses when the system is powered up.

2. Verify that the computer panel switches are set correctly.

3. Verify that the console can be operated in the local mode. If not, the console may be defective.

4. Verify that the green diagnostic, the DMA, and activity lights on the coupler are active.

COUPLER SYMPTOMS

Coupler symptoms, possible causes and checksl corrective action are described in Table 5-1. Voltage checks should be performed before troubleshooting more complex problems. Check the logics for voltage sources.

PHYSICAL LAYOUT

The physical layout of the board is shown in Fig- ure 5-1. Column and row numbers on the layout correspond to the numbers on each IC on the logic diagrams.

TERM LISTING

The input and output terms for each logic diagram are described in Table 5-2. The sources and destina- tions refer to the sheet numbers on the logic diagrams.

5-1

(22)

Table 5-1. Coupler Symptoms

TROUBLE POSSIBLE CAUSE CHECKIAEPLACE

1. Green DIAGnostic light on 1. Microprocessor section of 1. Coupler.

coupler is OFF. coupler inoperative. Put board on extender. With scope look at pins of 2901. All pins except power and

---'~Crystal not properly seated ground should be switching. Look for "stuck in socket. high", or "stuck low", or half·amplitude

pulses. If no switching, either power or b. Short or open on board. crystal bad.

c. Bad integrated Circuit.

d. No DC power.

2. No communication 2. 110 section of coupler "hanging 2. Computer interface logic of coupler.

between console and up" a Bus.

computer.

DEN

always low.

a. a. Check signal DEN for constant assertion.

b. Shorted bus transceiver IC. b. Check 1/0 IC's. Remove coupler board to see if trouble goes away.

c. Bad CPU board. c. Run CPU diagnostics.

3. No data transfers to/from 3. Tape not ready or bad cable 3. Check tape switches and cable connector.

tape. BSY light never connection.

lights.

a. Improper communication with a. load and read tape registers from console tape registers on coupler or with processor halted, I.e., RKDS. RKDA.

bad IC in register section of RKER. Verify bits loaded can be read.

coupler.

4. Data transferred tolfrom 4. Bad memory board in backplane. 4. Run memory diagnostics.

tape incorrect. DMA and

BSY lights blink to indicate a. Noise or intermittent source a. Check AC and DC power.

transfers. of DC power in computer.

b. Bad IC in tape 110 section of b. While operating. check lines from coupler

coupler. to tape with a 'scope for short or open.

c. Run tape diagnostic, set c. Analyze error halt.

console to make system "Halt On Error."

d. Bad area on tape. d. Errors should always occur in same sector of tape.

e. Head worn. e. Replace head.

f. Configuration switch not set f. Check configuration in Installation Section.

properly.

5-2

(23)

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MAGNETIC TAPE COUPLER INSTRUCTION MANUAL

MODEL DQ130