Signetics 8X305 MicroController

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(1)Signetics. 8X305. March4984. 8X305. MicroController.

(2) h'j. %. program counter Ao. ~'.t—. " ~µj~...... A6. ,.. - .. ~gj—. a,. ·. . .. CD—-. N~µg-. :. ~Á)". l0 " í;j. 13. D :J 0. a. .'".'i-w·5. " "-.-.i ;."í: '""' '""'. 16. t,. .18,. ,=,. ". \ ^. m. ". "(ii. -' -'. '. '13 :::. ":. :::s¶:r'". gí. ~ÁP"". ~. " j-j". l. E. = @. xi. 2. ". decode and control logic. rf3 (Note3). R14. ,,,, shift. alu .. '. rio. ro—aux#1. "°"". "°"". '. @. ". , multíÁexer ,,. a 8. right. '"'""""' ,,,,,,,. &. —®—iv1. jg—" ®—iv3. —k. ,,d latches. _C®_"' 4®—W. 8. '°"". K+ág6. one of eight. 36. lV4. 49D"" ·(®)-sc. "(@_"'. i" internal control. j. :u O m. E. ". _. en. merge control. 8. b. mask (Note6). :. Z "m. r4. r3. - -. am (Noten. S. O :V O " O o O ao d Ci. r2. ". 3. "u áj. ~—c 12)—gnd. R7 (Not· 2). r6. Rt. '. alu tR&-¿R15 multiplexer. \y\\\\\\\\\\\\\\yC. 'S j_Z. ~,. R11. " -"'. m. f' «\\\\\\\«\\\\\\\\\\0 y. ~9>-vcc ~«i>- VCR. Notos1/6 r17 (Ñot82). t—w\ m50,r—vR R12 (Note3) -. *. 111. "'. ". \. ^.. -. 8 " ". -. 8 " j""""'. RIB. R15. R5. ". ". '". i'·"j %\"\\\\"Y ' >k ..ik . "i-Éi'a Iii:".' '"'""" 4': .'::'^ 4::i:ii!i^ 4:1.',·"^L"j-^ .g'·';,'^ "-' " " ' :-9.' i'.,,": H »s · Zir'S LrE7 "i -:. - 1>"". 1·'": a·é .-, i':::.': ". "...,": i"; "-' ;}ji ' :'-": 'j;'" ¿.;,·'j !j'.-!: ":.· ·:.. ·-. \\ " ==-'·=, -E-;·e:.:.... ->%' ·.": '3.=nTi¿'i"':"'"""-':::-:-'"·1"-:',.·:'!j' :-'"i' ...: :.·, "":' ¡i; -'i' b fj;i'§. 1%!, ,'"".,. ..,,,-,,'. q ,-.,.,-, . '"I'! i',-;.;;--"-': .. '"""1 "'"'"'"'""""""'--""' " " '" "' # m |R3-lR7 Z ..;: '.-;.: i"""'""""""'""" '""""""""""""'""'""""'" ""'"'"' "' " "'"""""'""""'""'""""""' is S£4.Z:. ^ n^. _m"r" \ : =SS\\N\\\r\\\\\» ho. '. " ". c'$í']. \\ " ~Tj~,,§ -". J3. en. 4: : :1". ,., "... e '"-)1 :,)"' "'"' ' . '. DATA address ANDaddress control 1NSTRUCT)DN AND instruction control INTERNAL/EXTERNAL control. ADDRESS multiplexer. zsti J5j. \_4. 'I'.u13 ".. ^ 4^'x ^ i3 "" "" "" ~5. i%. "". "ii address register e ,' A. lí9. Eú·.·... ..-·'··""'.' .'J: ' - ' ' ?a'!". -". data registers. W. ,. ...·j13 ,j'e". 6>. '4. =m>, "'""--" ---'. "^^. &2 ~<D— A'. increment logic. program register. ~Uj~,. Aj. Legend. UJ. i ,. "gg—" · gj)—T'. r. ·. f. (Á)—. mclk. 7. ". NOTE:. working registers. 1. Regtsters R1-R6, R11 and R14-R16 are general-purpose the B-bit vafue is In any inStruction where R7 (IVL) or R17 (IVR) is specified as the destination, . output on the IV bus as an iV device enable address (SC = High)—R7 = left bank and R17 = right bank; the results are also stored into the specified internal register and may later be accessed. 2. ". (S) (@. ". gij. ". ·. oscillator and timing generator. l. as source data. 3. R12 and R13 are general-purpose bit of register 4 The least significant . the most recent ADD operation.. except transmtt (XMIT). working registers for all operations RIO (OVF) is used to reflect the carryout status resulting from. working register that holds the implied operand for RO #1 is a general-purpose and Logical operations; the content of this register is repeated in AUX #2 (shown dotted). only for layout register is physically part of the ALU and is shown separate duplicate. 5. Auxiliary. register. Arithmetic The. convenience. working registers cannot be operated on by the MASK logic. the ALU tests for all bits equal to "O" (Transfer 7. During NZT instructions OPERATIONS that follow.. 6. internal. Figure. 1.. Architecture. and. Pin. Designations for. 8X305. MicroControHer. if Fk'0)—refer. to BASIC. Do. %. g. 2. ¢JN. :9. >. js.

(3) BIPOLAR. LSI PRODUCTS. MARCH. MICROCONTROLLER. 8X305. FEATURES. · · · · · · · · ·. Fetch, Decode, and Execute a 16-bit instruction in a minimum of 200 nanoseconds (one machine cycle) single·or· Bit·oríented instruction set (addressable multiple bit subfields) Separate buses for instruction, Address instruction and Three-State líO Thirteen B-bit general-purpose working registers Source/destination architecture Bipolar low-power Schottky technology/TTL inputs and outputs On·chip oscillator and timing generation Single + 5V supply 0.9-in. 50·pin DIP. PRODUCT. 1984. DOCUMENTATION ASSOCIATED Other documents directly relating to design and app/icat/ons use of the 8X305 MicroControl!er are: · Product Capabilities Manual · 8X305 Users Manual . (Data These documents and other current literature Sheets, Product Bulletins, Applications Notes, etc.) are . . . avaílab(e Sales and Service Offices—see at ali Stgnetics . . . . rear cover of this data sheet for the office in your locahty.. PIN CONFJGURATlON. DESCRIPTION. n,. j. package. vcq;. (Figure I) is a highThe Signetics 8X305 MicroControiier implemented with lowspeed bipolar microprocessor power Schottky technology. In a single chip, the 8X305 combines speed, flexibility, and a bit-oriented instruction set. These features and other basic characteristics of the chip combine to provide cost-effective solutions for a broad range of applications. The 8X305 is particularly useful in systems that require high-speed bit manipulations — sophisticated controllers, data communications, ' of a very fast interface control, and o th e r app li cations similar nature. The 8!305 can fetch, fjécode, and execute a 16-bit T" structton w2rd in a minimum of 200 nanoseconds. Within one instruction cycle, the B-bit data-processing path can be programmed to rotate, mask, shift, and/or merge single or multiple bit subfields and, in addition, perform an ALU operation; in the same instruction, an external data field can be input, processed, and output to a specifled destination — likewise, single or multiple bit data . fields can be .internaliy moved from a given source to a given destination. To summarize, fixed or variable-length data fields can be fetched, processed, operated on by the ALU, and moved to a different location — ail in a timeframe of 200 nanoseconds. To interface with ItO and program memory, the 8X305 uses a 13-bit instruction address bus, a 16-bit instruction bus, an B-bit bidirectional multiplexed l/O data/address bus and a 5-bit l/O control bus.. ®VR. ·r[j. mA·. MT. Fk F'1ü. y" '. " "'. a3G. ®Á12. e uj d. Aí A,[í A0g. "P. "tii:. '"fíí. ', [ií h[jÍ i,[i9. t3[j[ f,(íi fÁS. i;. O uj O F" O c9 Z X O QD O O X O E. '4Ét '4F '4S. Qfáü. a~. 'Qm"k. 'a"°. 'a" N" y'v'. ®Vcc ®Ñ"4. ®'t' ®ive. ®m FN ®g ®w'. ®" ®"5. ". "° f11µ. ®í14. m®. @13. top. order. view. numbers. 8x305n, 8x3051 s8x3q51/883b, s8x305i/883c. A wide selection of l/O devices, interface chips, and special-purpose parts are available for systems use. In applications, most the more powerful 8X305 is functionally interchangeable with its predecessor — the 8X300.. Signetics. 3.

(4) BIPOLAR. LSl PRODUCTS. MARCH. MICROCONTROLLER. 8X305. '"E. ® Mn. ". ·7[j QT. ®á9. 'sIT. :a'tQ. M9. 7Qm ®'12. '3G. e tu. a2[j a1G. "[íí "El io@. C. A()- A12 XI,. X2. voltage. input. Program. Address. Lines:. storage;. A12 is least. Timing. 'N. Z. GND. 29. SC. Select. 30. WC. Write. 31. LB. Left. fo. RB. lVO-lV7. 38-41. Bank. LB. fá" ®As. l11µ. ©14. |12F. 'QÍ13. Right. signal. active-high. (2N5320. direct. permit. outputs. or equivalent). addressing. of up to 8192. words. of program. bit. for. addresses. a capacitor,. a series. crystal,. resonant. external. or an. clock. source. with. MCLK. Master. Clock:. external. logic.. are. forced. I),. input. low {binary ME. pin. input. instructions. from. program. 45. storage;. is. output. connected. O), devices. and. is being. is being. output on. pins. on. pins. lVO through. lVO through. to the. Left. Bank. to the. Right. are. lV7.. lV7. accessed.. (Note.. Typically,. (Note.. Typically,. of //O peripherals).. pin. Bus). devices. address. O), devices. to the. l/O. an data. I),. low (binary. When. active-high. input inhibits. high. of. //0. these — memory. connected. Bank. are accessed. peripherals). bidirectional. active-low. locations.. three-state. voltage. A low. level. lines equals. communicate a binary. data. "I";. IV7. is. HALT. is not inhibited. input. are. synchronously. the. time. HALT. Internally-generated. is low MCLK.. signal. output. (binary. O), the. For the. period. for. is used. 8X305. l/O. clocking. and/or. devices. synchronization. Counter/Address sets Program — is low, the Left Bank/Right Bank (LB/RB). is initialized. of time. RESET. of. Register signals. asynchronously.. MCLK. 2.. (binary (binary. ME. This. When. Figure. 16-bit. Bit.. RESET and. receive. lines. supply.. power. When. input. to the. to. Significant. 42. high high. (lnput/Output. Interface Vector. + 5V. VR. transistor. active-high. When. is tied. Ycc. HALT. series-pass. These. When. Control:. Bank AB. and/or. RESET. from. When. is tied. signal. to zero. 4. f10µ. These. Control:. 37. 50. ®W'. bit.. Command:. Least. 44. "íg's. 'oµ. significant. Lines:. Command:. the. 43. ®nt FN'. outputs.. significant. least. the. 33-36,. ®Ñé. Ground.. fnstruction. 32. ®n5. 'Sµ. connections. generator. -Ñ. 13-28. t::'. FUNCTION Regulated. complementary 12. ®Ñá. IDENTIFIER VCR. 11. ®nz. isµ '7µ. 10,. t—. e O. l4liT. 45-49. "g"° 'qñ'. O. 'N. 2-9,. O. u. ,':. NO.. u ®n¢lk. e 3 Z u). gÑo[iZ. 1. @etáü. "J m. aqF. PIN. 1984. is low. (binary. O), internal. nor is any internal driven. high. register. during. the. output. voltage. operation. of the. affected:. first. however, of the. quarter. 8X305 both. stops. at the. instruction. cycle. time. of. start. the Left Bank/Right. Bank. and. is low. reference. Designations. and. Descriptions for. Signetics. for. externa!. Pins. of. series-pass. 8X305. regulator. MicroController.. transistor.. next. instruction;. (LB/RB). remain. high. signals during.

(5) BIPOLAR. MARCH. LSl PRODUCTS. 8X305. MICROCONTROLLER. FUNCTIONAL Typical. System. ing 256 ln£ut/OutpUt locations and, with additional bank bits (LB, RB), this number is expanded to 512 — each bank comprising 256 addressable locations. The addressable locations of each bank can be used in a variety of is shown in ways; a simple method of implementation Figure 3. When is active low, the left bank is enabled and any one of 256 locations within the RAM memory can be accessed for input/output operations. A similar set of "enable/acc,e,s,s" conditions are applicable to the right bank when RB is active low.. OPERATION Configuratlon. Although the system hookup shown in Figure 3 is of the simplest form, it provides a fundamental look at the 8X305 MicroController and peripheral relationships. As indicated, the 8X305 can directly address up to 8K words of program storage — either ROM or PROM. The user interface (lVO through lV7) is capable of uniquely address-. 'L' "".'.,., '""... ... 'i'. " 7,&sE,T " I. TRANSISTOR. ": m. ,"°"Z2L'"±"!j 1. VCR. VR. A7. & @~~"i!í) $jj Ág _J 4(J " [iij. ^C "·'.-·-····-. ·::'j__~j— . :.í;¿f:!" j.3 '!i:i:i!. Ni. ?j: j:?. "—mí. '%. A1q. J~. "^'. '11. il.l í!jilí iitl 33:!,l jf)í >. J">YRy" . ·¥' '-"-" program storage (READ ONLY MEMORY) 8X x 16 ROM/PROM. &. '".' "......: .:,:.:,::::::.,..:,:.'.:.::::::::',:,:,:,:,:::::::':':'.::::::::':':':'""""":::' :':":':':'"""r. !$¿3: :. iiiii;í. Ú::::g !I!I'. xtal (OFF.CHfP)=. T. 1984. ',',ít""5 i!: µ~mT !1—-~E. 8. í. "'. a,. 5. m. m... i " 7. t y. :G. ¢4. _A_ 15. x2 GND. j. ,0. d o F". C9. Z. a. u. Iq. O O O. I} |2. ño. user. 8. iv1. m. 'I:. 3. fP" .. 36. lV5. 35. "p 2c. h. lb. 31. —p@'. l8. WC. 30j. -~€á'. 'g. SC. a. 1. t. "2. '13. System. Signetics. " r. 27. %7/////////////////////////////////////////>IJ. ·. .. " 8. ·. 1.OF.256 addressable. locations. m. i". 7F"_. "5 H4. ^"^. \. " _7. "q. \. Jy. ®. l11. '. R(GHT BANK. lV4 —. Tb. ':::::,". LEFT BANK +5V. Z'. 8X305. ". 38. '6. Typical. " "p. "". % —L~_ 37j. Ycc. e. 3.. /'>. inputs. 41. IV2. ¿16 k. Figure. mío data and address jjjj" = INSTRUCTION ADDRESS //. = INSTRUCTION. reset íF" '°'"°"" """a. I. $-. W. " m~— m · 'Iii 43. xi. ~A— ,12. Legend:. halt µµ— i. A2. "úíµ " J" T. 50. ". j'. r. Hookup. 5.

(6) BIPOLAR. MARCH. LSl PRODUCÍS. MICROCONTROLLER BASIC. OPERATIONS. 1984. 8X305. OF 8X305. Refer. o' "Instruction to a later dtscussion Fields" for a detailed of all operand exammahan and subdmsions thereof--"S" (Sq, Sj). "D' (Oq, D), ' R'. "L", "J", and "A". fields. MOVE OPERATKJNS REGISTER.TO-REGISTER. < SOURCE. RQ-R17 S f Id. DATA PROCESSING (PREALU) k f. f cl t. y. Right by R. ». t. f. p d. f. t. >. ALU. d. Ng) operation. P. t. DATA PROCESSING (PQST-ALU) ». REGISTER-TO-IV. q SOURCE. DATA PROCESSING (PRE.ALU). Ro-R17as specjfied by "S" field of instrugtic)l1.. No operation. P. DATA PROCESSING (PRE ALU). Variable length field of tV t)üs—LOft Ba,n,k (iS) Or Right Bank (RB) as specified by "Sj" and "$0" fields of instruction. V. No operation.. BUS-TO-W. y. RQ-R7, R11-R17 as specified by 'D" field of |nstructIon. [JUS. P DATA PROCESSÉNG (POST-AW). ALU. Right rotate and mask as speci'ied by Sq' and 'L ' rie,as st to. Variable length fia.l,d of N bus—Left Ba,n.k (CS or Right Bank (RS) as speciheel by "Dq" and "Dj" fields Of mstruchon.. DESTINATION. D. DATA PROCESSING (PRE.ALU). ». y. P. Ng) pperahon. IV. Variable length fie.l.d of iV bus—Lelt 8a.m,k'CÉi' or Rrght Bank (PÉl) as speci tied by Sj and 'Sq' f Id f t. SMft and merge as specified by "(JO" md "L" f|eld$ of mstruction.. DATA PROÓES$ING (POST-AW). P. q SOURCE. DESTINATfON. BUS-TO-REGISTER. ALU. Right rotate and mask as $pocihed by "Sq" arid "L" fields of imructton.. PO-RT R11-R17as specihad by "D field c)' 'nstrucncm. >. Ng) operation.. lV. SOURCE. P. DATA PROCESSÉNG (POST-AW). P. <. Na operát©n. IJUS. ALU. P. DESTINATION. Ng) operation. P. h. DESTINATION. Shñt and merge as l b Dq ' aria 'L p he',d$ Of lñ$ttuct on. b. VariableNngth field of iV bus—Le't Ba.n,'clCS or R ght Bank (RBI as speer fted t)y Dq' and Dj ' f Id f t t. ADD OPERATIONS —M. REGISTER-to-REGISTER REGISTER-TO-Ñ lV lV. j~q. BUS. ~"ñ=ñ~Q. BUS.to-REGISTER. BljS.to-lV. source. BUS. -~1. SOURCE. —m. source. prealu. TÍ ~. pre-allí. l. pre.alu. 't. Same. as MOVE operations, except data is A1)Oed to contents. source of Alj)á1iary ALU.. l~q7=Tl—(. Register. if appropriate,. Register. RIO. {OVF). RO v)á. the Overflow is also. set.. }. ~ é—+=ún~r6Em post. t—q. ~. alu i—m. dest. post. alu. j—q. post. Alu. r-r=m. desi. ). I. AND OPERATIONS REGISTER·tO-REGISTER REGISTER.TO-Ñ. iV. BUS. BljS-to-REGISTER. iV BijS-tojV. BUS. EXCLUSIVE. BUS. iv. BUs-to-REgIsTER. lV. BljS-to-1V. 6. BUS. as. data. source. tents the. MOVE is AUXiliary. of. operations, except ANDed with conRegister. RC) via. ALU.. l m 'qst.alu. FM. dest. ~=-U F-M ~"="J M ~0" a'u µ·q post. alu. l. dest. l. OÉÉX. I. l. OR (XOR) OPERATIONS. REGISTER-to-REGISTER REGfSTER-TO.Ñ. ~7. Same. ~=E~=Áü~. ~ ~ ~ymm=Áú+m source. pre-a'u. F-t,. ~%ÜRce~m·^~. ). Same. as. MOVE. operations,. except. source data is Excluswdy ORed with contents of AUXilíary Registe' RO via. the. Signetics. ALU.. }m é—q. postal-u. F-M. d's'. POST: LU. ~. dest. íy—rm-A~ ~[PO" A'u~. DEST. d's'_j. I l.

(7) MARCH. LSl PRODUCTS. BIPOLAR. 8X305. MICROCONTROLLER. '"IE. ',. E. q984. -:-.·.'.-.·.'...·'·:...,-.·:·::-.·.·..:'.'-'-'..'.:.'...::.:..:·:·:·.-'-:-:-:·: .'.'.'.'.'.','.".'.'.'.'..'.'·: ·'.'.'.'.'·'·'.'-'·'·'·:-.-'·:.:·:-:':.:.:·::"."'-'·.--.-:. '.'.·,·".·.·.·,··.·.·.-.·.·.·.-.-.-,·.-.-.-.-.-,·.·.-.-.--·.'.-.·.-.'.'.'.-.'.'.'.'-'.'.' :·:>.%P:·:·.·.'.-,\'·,·. ·"': ':·:':·,·.'.'.'.'.·.'.·.'.':'.'.·."·.·.·:··:·:·:·:·:·:·::·:'.·-.:.'.'.'.'.'.···...'.' '··:.'.'...'.'..-..............: ·:.:...':':·:-:: ',j ..·.'.·.b%%%',·,-.-.-.'.'.-.-.·.·.'.'.-'-'·.'.': ...·'..'.'.'.·...'.'·'·'.'.-'·'·'·'.'· ..-.·. .'..'..'.'-,-,.'.',,.....: :.".'·:-:-:·:·.-.-:"' ":'.'.,....··.'.:.:..·.:::·:""'""":'.,¿p j '"",'":.....'.-. ·'·'·'·.·.·.-'·.·"·"-.-'-.·.·: -.-·-·.·.·.-.-.-.·.·.-.-.-.'.'.·.'.'.'.'.'.'.'.'.'.'.','·,·, ',".'.',','.'.'.",'."-'.-,..--,.,·,·--.-,·,·.· ....·.·...·...·.·.....·...·.·.·..··.-. ..··.'...'.'.·... -.,-,·,·. ,-,·... ' ...-...... .....-----......,.,. ....... .... ': : '!. ;r,. ". ",. . .........,..., ,... ,.... '·'.'·'·'·""".'·'·'·"·"-'-'·'"·"·'·"-'·'·'·'·'·'.'·'·'·"·'-'-'·'·'·'·"·"·'·'·'·'·'-'·"· """·'·"·'·"·'·'·'·'·'·'·"'"'"·"·"·"·"·'-'·'·"·'·'·""""·: ·:·:·:·'·'·:·'·'·'·'·'""·'· '·'·'--········· ··"" " ..,........................ XEC, REGISTER. . .. ,,,...., ,, . .. , .. ...,...... ,. .. .,.......... ................... ................. ... ..-.... ...... "I. jm. DATA PROCESSJNG (PRE.ALU). SOURCE. No operation.. RO-R17 as specified by "S" field of instruction.. ». P. DESTINATION. DATA PROCESSING (POST.ALU). ALU Add source data to B-bit field specified by instruclion litera! (Os :s 3778).. No operation. P. b. j. Replace 8 LSB of Address Register* with B-bit sum from ALU. *PGM CTR unchanged.. XEC,ÍV. ' a SOURCE. DATA PROCESSING (PRE.ALU). Left or Right Bank of iV bus as specified by "S" field of instruction.. DATA PROCESSING (POST.ALU). ALU. Rotate and mask as specified by "Sq" and "L" fields of instruction.. B. BUS. B. DESTINATION. No operation.. Add masked field of source data to 5-bit literal specified by "J" field of instruction (O 5 g 378).. m. P. j. zea. ,. ÑSFiá (n. '. DATA PROCESSING (PRE-MU). RO-R17 as specified by "S" field of instruction.. DESTINATION. ». '. Test contents of source register for all zeroes.. NZT,. ' a SOURCE. DATA PROCESSING (PRE-ALU). Left or Right Bank of N bus as specified by "S" field of instruction.. TA. ÑsMrr. ». Mit). Rotate and mask as specified by "Sq" and "L" fields of instruction.. EE. tí. m SOURCE. O g j s 3778-value specified by "J" field of instruction.. No operation.. ». No operation.. I a. O :s: j :£ 378-vaÍue specified by "J" field of instruction.. "I. DESTJNATJON. Test contents of masked field for all zeroes.. if S= O, increment PC by I; if SR), replace 5 LSB of AR and PC with literal specified by "J" field of instruction.. """""" DATA PROCESSING (POST-ALU). No operation.. 8·BITS. p. IMMEDIATE,. ». P. DATA PROCESSING (POST-ALU). FIELD. p. No operation.. N. IMMEDIATE. ALU. No operation.. No operation.. DEST1NATK)N. P. P. Signefics. I. '. l. Left (r12L or Right (R13) Bank of lV bus as specifled by "D" field of instruction.. BUS. Shift and merge source data as specified by "Dq" and "L" fields of instruction.. " DESTINATION. DATA PROCESSING (POST.ALU). No operation.. '. RO-R7, R11, R14-R17. Load B-bit integer specifled by "J" field into register specified by "D" field.. iv BUS. No operation.. VARIABLE-BIT. DATA PROCESSING (PRE-ALU). ». JV BUS. ALU. ». XMIT. SOURCE. If S = O, increment PC by I; if S¶éO, replace 8 LSB of AR and PC wi'th literal specified by "J" field of instruction.. _. ALU. ALU. DATA PROCESSING (PRE.ALU). ». _. I. -'·.·.·'·.'.'": ·:·'::-:-,-"·"·'-'-,-"-'·...-.·.·"·""·.'.'.·..'.·'·"-.·:-:·:-:-;-:·:-:·: -'-"-'-'-: ·:·:.:-:-:-:.:.'·'·'-:·".:.:·:.:':-:-:.:.:·:·:·:-:-:·:·:·:-:·:·:·:·:-:-:·:·:·:-: -:·:·:·:.:-:-:':':':·:.:.:·:'"."."."·"-:-:-:·.·:·:-:-:·:·:·:-:-:·:·:·:·:.:.:.:·:':':.:.:·: -:-:-:·:·'-:-:-:·:·:.:-:.'.:.:·:.:.:.:.:-:·:·:·:-:-:-:··:·:·:.:.:.:.".'.:.:·:"·'·-:·:·:·' ·"''"':'"'".::·'·:·'·'-'-'-:'"""""' ' '-'·"·".· ..·....'·'·"".-·.··--····-···-·····--· .·-.·.'.' ..·...·,-.-'-'·: ·:·:-.-.-,-.·.·.-.-..,·.............·.....·.-,.,....·.·.-,-,-.·.·.-.·,-.·, .......'...,·.. ,j'"j: ....·.·.' ....-,-,-.·.·.-..,..·...·......,....··.-,-,·,·.. ·..-........'-.......-.--,--·'·'·........"·'· ... - ..-.... . ".,.,...,.......,. ..............,.,...............,.,.......,..........,...,.......,.,......,.. ,. ,.....,.............-.... .,. i. ' ' .,.-..,.,..... ................ ........ :; :::::::::::::::::::::::::·,-,.:.,.::::::::::::::... ·:·... :·:-:-:-:-:·:·:·.-.. -.-.-...."' "...'·.."'""..·'·".·: -:-:-:'."·".'.. ' ' ''· ' ' """"...' "'""'. ....-...'.'.'...-'-.'..: ......·.,-, .,..,.,-.,,.,...............................-.,-, .'..'"." -,.,-..'., ....."...'"'.'"'" . :.:.:.:':.:.....:::::::.:..::::::-:.....,.,-,-,.,.,.,-.-,.,.,.,..-.-,-...........-...:·:·: .,.,...,...,.... XMIT, REGISTER I. XMIT. SOURCE. __. '. N. q. O :s J s 3778-va|ue specified by "j" field of instruction.. ». DATA PROCESSING (PRE-ALU) ». REGISTER. ALU. No operation. P. *PGM CTR unchanged.. i'. NZT,. SOURCE. Replace 5 LSB of Address Register" with S-bit sum from ALU.. ......-...,.....-.... .......................................,.... ,........... . ... .....-.....-. ,..,,..........,..............,.,...,.,-,.,.... ,..., ......... ...................... .......... ....................................... .' ....................... ...,.,.... ,...,....., ........................... ...... ·'·"·"·"·'·'-'·'·"·."-'·'·'·'-."-'·'·.·".'.·."·.-.·.'.'"'.'.'"-'""-'-""'.'."·' "".'.".".......... .'.'-'-'.""-'-'.'.'.'"...'.'...".'.'.'.'.'-'.., ....'.'.'.'.'.....".".'.'.'.'., ·'..." '.'-'-'": ..''":'.:::':·.""·'-. ' ' ' 'Ff : . '.'.·: .. , . '-'-' "' '."'"'"'"·: ·:':·: ,............ ......,........... .,........,............... .. ,..... . ...... : ·:-:·:·:·:·:·:"·:·:·:·::··:·:·:·:-.·.·:-:·:-:-·:·:·:.:....':':·::'::.:·:·::'-:-:':'::-:' : ::·:·:-...·'·'"...."...-'-: ·'·'·'-'·: ·:·:-:-:·:·:·:.'-'-":·:·:.':':':.-.-,-:-:-.'.:.:.::".'.'·"·'·"-'.'-:·:·:-:-:·:'·'·"·'-"·'·'·'·'·': ·:·:·:·:-:·:·:·:·:-:-:·:·:·:·:·:·:·:·:'::·:"·:·:·:·:·'":·:·:·:-'·"'. m. ·. "l. DESTINATION. P. Left or Right Bank of Ai bus as specified by "D" field of instruction.. 7.

(8) BIPOLAR. LSl PRODUCTS. MARCH. MICROCONTROLLER. UMP(. MP). ERAT. 1984. 8X305. N ' ...'.'.'.· ·.·-·.· . ··k·r. :.·.'·····. ·..··' . .·.··· ·.. ... ··.·.·.·.·.·.···..'.'.·.·.· JMP,. |<. ADDRESS. P. SOURCE. DESTINATION. 0% A :5 177778-valUe specified by "A" field of instruction.. Program. Storage. "". ". ,,. As shown in Figure program storage is connected to output address lines Aq through Aq (A12 = LSB) and input lines tQ through G5. An address output on instruction AqÁq identifies one 16-bit instruction word in program storage. The instruction word is subsequently input on |0/|15 and defines the MicroController operation which is to follow — one instruction word equals one completed operation. Any TTL-compatible memory can be used for program storage provided the worst-case access time is compatible with the instruction cycle time used for the for appropriate application section see timing — calculations. and Control. An B-bit bidirectional l/O bus, referred to as the Interface link between Vector (lV) bus, provides a communication the MicroController and the two banks of l/O devices. The íTb (Left Bank) and Wb (Right Bank) control signals Ídentify which bank is enabled; when both LB and RB are high (inactive), neither bank is enabled and the (V bus is inactíve (three-state). A functional analysis of the Left and Right Bank signals is shown below: LB. FIB. Low. Low. Basically, the data processing path of the 8X305 consists of the Rotate/Mask logic, the Arithmetic Logic Unit (ALU), the Shiftl Merge functions, on-chip memory (sixteen B-bit registers), and the bidirectional lV bus interface with its associated driver circuits and internal latches. The onboard memory and the lV bus are connected to both inputs and outputs of the ALU via internal B-bit data paths 1. Inputs to the ALU — see Figure are preceded by rightrotate and data-mask functions; the alu output is followed by the left-shift and merge operations. Depending on the desired operation, any one or all of the functions (Rotate/Mask/Shift/Merge) can operate on 8 bits of data in a single instruction cycle. For a summary of all dataprocessing capabilities, refer to BASIC OPERATIONS OF THE 8X305 described earlier in this data sheet. instruction. Cycle. Each operation of the 8X305 is executed in a single instruction cycle. The instruction cycle is internally divided into four equal parts — each part being as short as 50 nanoseconds. Figure 4 shows the general functions that. FUNCTION INPUT PHASE. q is not. Low. High. High. Low. This state Enable left bank Enable right bank. High. High. Disable. all. generated. by the. devices.. ~_QU:. devices.. devices;. lV bus. is three-state.. 50ns. SOns. decode. Both data and l/O address information are multiplexed on the N bus. The SC (Select Command) and WC (Write Com' ' ' between data and l/O address mand) signals distíngtnsh information as follows: SC. WC. High. Low. Low. The. Low. Low. Low. The. Low. Low. High. Data. Low. High. Low. Address. X. High. High. This. OUTPUT phase-. g. 50ns. and process input data. is three-state. looking for input lV bus. instruction address, generate. instruction and, if. control. required, new data. signals, setup data. fetch. is being. cond. and l/O. latch. i/o. enabling address i/o data. or into selected. peripheral.. for output. "1. »(A"C: 'V'E-¿ and. not. data.. is reading.. ~ 50ns. next. latch. FUNCTION lV bus. p-. ¿:ERjQU7:'TER—QU::'TERlQU::'TER—. instruction,. LB/RB. µ. 8X305.. input. 8. Load Address Register and Program Counter with contents of "A" field.. k. "". Data Processing. Interface 3,. l/O Interface. "~. .input data.. output. output. ition is never generated.. L. Note8: STATE) 1. New instruction must be accepted and latched at end of first quarter cycle. 2. The l/O data latches are open for the first two quarter cycles, that is, for lOCi nanoseconds. 3. The address changes during third quarter cycle. 4. iV bus drivers ara active (turned on} during third and fourth quarter cycles.. is being. Figure. 4.. Instruction and. Signetics. Cycle. Cycle Time. and. =. MCLK. 200. with: Crystal = 1OMHz nanoseconds..

(9) MARCH. LSl PRODUCTS. bipolar. 8X305. MICROCONTROLLER. occur during each quarter cycle; specifics regarding minimumlmaximum timing and other critical values are described later in this data sheet. During the first quarter cycle, a new instruction from program storage is input via 4rhs and decoded. If an )/0 operation is indicated, new data is fetched from a specified internal register or via the lV bus. At the end of the first quarter cycle, the new instruction is latched into the instruction register. the second quarter cycle, the l/O input data stabilizes and preliminary processing is completed; at the end of this quarter, the N' latches close and final processing can be accomplished, thus completing the input phase of the instruction cycle. During the third quarter cycle, the ad. dress for the next instruction is output to the instruction address bus, lV control signals are generated, and both data and destination are setup for the remainder of the output phase. During the fourth quarter cycle, a master clock signal (MCLK) generated by the 8X305 is used to latch either the l/O-enabling address or the l/O data into peripheral devices connected to the N bus; MCLK can also be used to synchronize any external logic with timing circuits of the 8X305. To summarize the action, the first half of the instruction cycle deals primarily with input functions and the second half is mostly concerned with output functions. In. INSTRUCTION General. and Operating. Principles. The 16-blt instruction word Qc) through &5) from program storage is input to the instruction register (Figure I) and is subsequently decoded to implement the events to qccur during the current instruction cycle.. Table. The general format for each instruction tows:. word is as fol-. t msb. lsb t. bit positions. —. o l 2. 3456789101112131415 operand(s). opcode. The 3-bit operation code (OPCODE) define any one of eight classes of instructions; variations within each class are specified by the remaining thirteen operand bits. The eight Instruction classes can be separated into two control areas — data and program; general functions within these areas are:. ·. ·. Data Control — ADD ) Arithmetic and Logic Operations AND XOR MOVE I Movement of Data and Constants XMIT Program Control XEC ) NZT Branch or Test JMP. Instruction. SET. Format. Fields. As shown in Table 1, each instruction word consists of an operation code {OPCODE) field and from one to three operand fields. The possible operand fields are: Source (S), Destination (D), Rotate/Length (FUL), Literal (J), and Address (A). The OPCODE and operand fields are described in the paragraphs that follow the table.. FUNCTIONAL DESCRIPTION OF 1NSTRUCTÍON SET. 1.. state of. DURING INSTRUCTION. word. descriptjon. class =. move. opcode =. o. operation. = (s). Register-to-Register 1. 2. 3. 4. OPCODE S = 008-178. 5. 6. 7. 8. S. 9. 10. 11. 13 14. 12. R. 15. D. - 008-078, 118-178 Register·to-lV Bus (Note) O. 1. 2. OPCODE. D. 3. 4. 5 S. 6. 7. 8. 9. 10. 11 12. L. D = 208-378. 14 15. D Dj. S = 008-178. 13. :. 0(). CONTROL. INSTRUCTION. see control signal. O. 1984. figure. input phase. 4. signal cycle — output phase. ~d Move content of internal register specified by S"field to internal register specified by D-field. Prior to the "MOVE" operation, right-rotate contents of internal source register by octal value (O through 7) defined by the R-field.. Move contents of interna! register specified by the S-field to the lV bus. Before outputting on lV tÁÁs¶ data is shifted as specified by the least significant octal digit of the D-field and the bits specified by the L-field are merged with the latched Í/O data.. ,. Signeñcs. SC. L. WC. L. H¡fD=078,178. LB. H. L if D=078. RB. H. Lif D=178. L. SC. L. L. WC. L. H. H. L if D = 2C)8-278. Lif D=208-278. RB. L if D = 308-378. L if 0= 308-378. 9.

(10) LSl PRODUCTS. BIPOLAR. MARCH. 8X305. MICROCONTROLLER. Table. FUNCTIONAL DESCRIPTION. 1.. INSTRUCTION SET (Continued). OF. STATE DURING WORD. INSTRUCTION. DESCRIPTION. = MOVE. OPCODE. Bus·to·Register. lV O. 1. 2. 3. OPCODE. S = 208-378 lV. . Sj. 1. 2. 10 11. 3. 5. 4. 6. 7. 8. 9. 10 11. OPCODE. Dj. = 1. OPCODE=. = AND. XOR. OPCODE. = XEC. Register O. 1. Move right-rotated lV bus (source) data specified b,ythe S-field to the I/O latches. Before outputting on lV bus, shift data as specified by the D-field; then merge source and latched l/O data as specified by the L (length)held-. 14 15. D. , . Sq. 0 :. Dq. 2. =. OPCODE. class. 3. 4. 6. 5. OPCODE S = 00B-17B. INPUT PHASE. SC. L L. H if D=07B,. W. L if S = 208-278. Lif. Éíé. LifS=3O8-378. Lif D=178. D=078. sc. l. l. WC. L. H. W. LifS=2Q8-278. Lif D=2O8-278. Á"B. L if S= 308-378. Lif D=308-378. =(S). OPERATION. 3. =. (S). class. 7. 8. =. Refer. 10 11. 12 13. 14 15. j. S. class. Same as MOVE instruction. class. to Description Execute instruction at current page address offset by J (literal) + (S). Return to normal instwction flow unless a branch is encountered. Execute instruction at an address determined by repiacing the low-order 8 bits of the Address Register with the following derived sum:. = O008-3778. j. Same as MOVE instruction. ~D. Same as MOVE instruction class except that contents of AUX (RO)register are Exclusively ORed with source data.. OPERATION. 9. EÉ)(AUX). class. +D. Same as MOVE instrucbon class except that contents of AUX (RO) register are ANDed with source data,. OPERATION. = 4. /\ (AUX). class. Same as MOVE instruction. SC. L. WC. L. L. LB. H. H. ÉiÉi. H. H. L. L. The PC is not incremented and the overflow status (OVF) is not changed. Bus. O. 1. Immediate 2. 3. 4. =. Register O. 1. 2. 10. 7. 8. 9. ':. 10. 11. 12 13. L. 14 15. j. Sq. J = 0O8-378. NZT. OPCODE. =. 5. OPERATION. = Refer. Execute instruction at an address determined by replacing the low-order 5 bits of Address Register with the following derived sum: S-bit value of literal (J-field) plus value of rotated source data specified by S-field. The L-field specifies the length of source data starting from the LSB posi" tion and, if less than 8 bits, the remaining bits are filled with zeros: the Program Counter is not incremented and the overflow status (OVF) is not changed.. 3. 4. 5. 6. S. j. = 0008-3778. 7. 8. g. 10. 11 12. j. 13. 14 15. SC. l. WC. L. L. LB. L if S = 20B-278. H. Á6. Ljfs=308-378. h. to Description. Immediate. OPCODE S = 008-178. 6. S Sj. CLASS. (Note). 5. OPCODE. S = 208-378. 17B. L. Value of literal (j-field) plus contents of interna) register 3pecified by S-field. lV. —. OUTPUT PHASE. WC. Same as MOVE instruction class except that contents of AUX (RO) register are ADDed to the source data. If there la a "carry" from MSB, then RIO (OVF) = 1 (overflow), otherwise OVF = Cl.. Immediate 2. CYCLE 3. =(S)+(AUX) -HJ. OPERATION. Same as MOVE instruction. CLASS. FIGURE. D Move right-rotatedÑ bus (source) data specified by the S-field to internal register specified by the D-field. The L-field specifies the length of source data starting from the LSB-position and, if less than 8 bits, the remaining bits are filled with zeros.. 15. SIGNAL. D = 208-378. = ADD. =. 12 13. L. ,D :. Same as MOVE mstructíon. CLASS. 13 14 D. Same as MOVE instruction. CLASS. 12. +. (Note). S. 208-378. CLASS. 9. 8. Sq. Bus. Sj. -. 7. L. i. OPCODE. S. (S). CONTROL. D = 008-078, 11l3-178. Bus·to-lV. O. 6. S. _. =. (Note). 5. 4. OPERATION. = O. OF. INSTRUCTION SEE. CONTROL SIGNAL CLASS. 1984. If data specified by the S-field is not equal to zero, jump to current page address offset by value of j-field; otherwise, increment the Program Counter. If contents of internal register specified by S-field is nonzero, transfer to address determined by replacing the low-order 8 bits of Address Register and Program Counter with "J", otherwise, increment PC.. Signeñcs. sc. l. WC. L. l l. a. H. H. RB. H. H.

(11) BIPOLAR. MARCH. LSl PRODUCTS. 8X305. MICROCONTROLLER. Tabfe. FUNCTIONAL DESCRIPTION OF INSTRUCTION SET (Concluded). 1.. STATE DURING INSTRUCTION. NZT. O. OPCODE. = Immediate. TV Bus. 2. 1. 3. OPCODE. S = 208-378 CLASS. O. = Register 2. 1. 3. 4. OPCODE. O. Bus. 2. 3. 2. O. j=. OPERATION. 5. 8. 10. 6. 7. 3. 2. D = 208-378 CLASS. 13 14. 15. Store B-bit value specified by "J" into register specified by "D".. J = 0O08-3778. 6. 7. 9. 8. 10. 12. 11. 13. 14. 15. Enable I/O device on the bank specified by "D", whose address is the B-bit integer specified by "J". Address "J" is stored in register "D".. 6. 7. Bus. 8. (Note). 9. 10. 12. 11. D. 13 14. 15. Store value of B-bit integer in the previously enabled I/O port, at the bank destination or Éíé) specified by "D". Contents of R12 or R13 remain unchanged.. e. J. 3. . Bit· Fteld. 4. 5. 6. Immediate, 7. 8. D ;. g. lV 10. 11. Bus 12. L. (Note) 13. INPUT PHASE. CYCLE. —. 3 OUTPUT PHASE. SC. L. L. L. L. LB. L it S = 208-278. H. R9. LifS=308-378. H. SC. L. WC. L. 14 15. j. Transmit Least Significant "L" bits of "J" field to ú,-bit" field of iV bus specified by "D"; if "L" is greated than 5 bits, the MSB bits of destination field is filled with zeros.. Dq. L L. LB. H. H. RB. H. H. SC. L. H. WC. L. L. H. l-if D=QÜj. Éié. H. l-if D=178. SC. L. L. WC. L. H. LB. H. Lif D=128. W. H. Lif D=138. SC. L. L. WC. L. H. U. LifD=208-278. l-if D=208-278. RB. L if D = 308-378. L if 0= 308-378. SC. L. L. J = 008-378 JMP. 3. OPCODE. 4. opcode. 5. 6. OPERATION. = 7. 7. 8. 9. 10. 11. 12. = Refer. 13. 14. 15. to Description jump to address in program storage specified by A-field: this address is loaded into the Address Register and the Program Counter.. a. a =0o0008-177778 Note: Sq specifies Sj specifies Dq specifies Dj specifies. FIGURE. WC. u. j. = Address Immediate 2. 12. J = 0008-3778. Dj. 1. 11. SIGNAL. ~D. J. 5. 4. OPCODE. O. 9. = J. O008-3778. Variable 1. = 6. 5. OPCODE D = 128-138 XMÍT. OPCODE. Bits Immediate, iV. 8 1. If right-rotated and masked lV bus is non-zero, transfer to address determined by replacing low-order 5 bits of Address Register and Program Counter with "J", otherwise, increment PC. (The L-field specifies the length of source l/O data starting from the LSB-position arid if less than 8 bits, the remaining bits are filled with zeros.). 15. J. L. D. D = 078, 178. O. 13 14. 12. Address 4. OPCODE. XMIT. 10 11. 9. 8. CONTROL. to Description. Sq. 118, 148-168. lV 1. 7. D. D=008-Cl68, XMIT,. =. J = O08-378 XMIT. XMÍT,. 6. 3 ;. Sj. Refer. OPERATION. (Note). 5. 4. 5. =. OF. ÍNSTRUCTfON SEE. DESCRIPTION. WORD. CONTROL SIGNAL CLASS. 1984. the the bit the. WC. L. L. u. h. h. h. h. Tb. LSB of rotated input data field bank of N' bus from which source data will be input position in I/O device with which LSB of processed data will be aligned and bank of lV bus which will be the destination.. Operations Code Field. The 3-bit OPCODE field specifies one of eight classes of 8X305 instructions; octal designations for this field and operands for each instruction class are shown in the preceding table. Source (S) and Destination {D) Fields. The 5-bit "S" and "D" fields specify the source and destination, respective-. ly, for whatever operation is defined by the OPeration CODE. The "S" and/or "D" fields can specify an internal 8X305 register or any one-to-eight bit field within an l/O device; octal values and source/destination field assignments for all internal registers are shown in Table 2.. Signetics. 11.

(12) BIPOLAR. MARCH. LSI PRODUCTS. 8X305. MICROCONTROLLER. Table. 2.. ADDRESS. OCTAL ADDRESSES AND SOURCE/DESTINATION REGISTER RO. ®8 018. (J"43. G8 048. 058. DESIGNATION. R2—General. R3—General. 108. X. X. 118. X. X. 128. X. X. 138. X. X. 148. X. X. 158. X. X. 168. X. X. 178. purpose. purpose. purpose. register M—General register. purpose. R5—General. purpose. to. RIO. DESIGNATION. next. DESTI-. SOURCE. NATION. (OVF—Overflow X. . register) R11—General. purpose. . register R12—Genera( . register. purpose. (Note). R13—General . register. purpose. (Note) purpose. . register purpose. . register R16—General. purpose. purpose (refer. REGISTER. R15—Genera\. register register. 8X305 REGISTERS. R14—General. register. R7—Special 078. ADDRESS. X. register. R6—General 06b. NAT1ON. X. register. FOR. DESTI". SOURCE. (AUX)—General register. FIELDS. purpose. R1—General. purpose. . register R17—Special. purpose. register. to. (refer. next. X. X. X. X. x. X. X. X. X. X. X. X. X. X. paragraph). paragraph). Note: R12 and R13 function as general purpose working registers for all operations except transmit (XMIT). During a transmit instruction where R12 or R13 is the destination, "J" field is immediately transferred to the lV bus; for this operation, the contents of the designated register remain unchanged. In instructions where R78 (IVL) or R178 (NR) is spe,c.ified as the destination, the B-bit value is output on the lV bus as an l/O device address or memory location; register R7 selects the Left Bank and register R17 selects the Right Bank. The results are also stored into the specified interrial register (R78 or R17g and may later be accessed as source data. When the lV bus is specified as a source and/or destination, the "S" and "D" fields are split into two parts, that is, · Source {S) = Sj, Sq and Destination (0)= m, Dq where, Sq specifies the LSB of rotated input data field Sj specifies the bank of tV bus from which source data will be input D0 specifies bit position in l/O device with which LSB of processed data will be aligned and D1 specifies the bank of IV bus which will be the destination. ríght·rotate function. DESIGNATES LSB OF líO DATA— REFER TO TEXT DESCRIPTIONS Sj OR Dl. Sq OR Do. . « 2c,. # .j. e o. 1. 2. 3. 4. 5. 6. 7. , , , , , , , ,. 2h. ::: 24, 25, 2g, 27b Notes, 1. The field length of O-tO-8 bits is specified by the "L" field, 2. For the Right Bank, 308-378 perform equivalent l/O functions.. 12. O. i. #. the B-bit. Rotate (R) and Length (L) Field. The 3-bit FUL field performs one of two functions, specifying either the field length (L) for l/O operations or a right-rotate (R) for internal operations. For a given instruction, the specified function depends upon the contents of the Source {S) and Destination (D) fields. When an internal register is specified by both the source and destination fields, the "Ft" field is invoked and it specifies a right-rotate of the data specified in the "S" field — see accompanying diagram. The source-register data (up to 8 bits) is right-rotated during the "input phase" of the instruction cycle (Figure 4) and this function is always performed prior to any ALU operation. (Note: The right-rotate function is implemented on the bus and not in the source register.). BitPodtion" DESIGNATES LEFT (2) OR RIG.HT (3) BANK OF lV BUS. 1984. 1. 2. 3. 4. 5. k dd. 6. 7. i. When either or both of the source and destination fields specify a variable-length l/O data field, the "L" field specifíes the length of the l/O data field — see following diagram. If the source field specifies an lV address (208-378) and the destination field specifies an internal register (008-078, 118-178), the "L" field specifies the length of source data; the source data is formed by rightrotating the lV bus data according to the source address and then masking result as specified by the "L" field. If length is less than 8 bits, all remaining bits are set to zero prior to processing data in the ALU. If the source field. Signetics.

(13) BIPOLAR. MARCH. LSl PRODUCTS. 8X305. MICROCONTROLLER. specifies an internal register (008-178) and the destination field specifies lV bus data (208-378), the "L" field specifies the length of the destination data. To form the destination data, the ALU output is left-shifted according to the destination address and then masked to the required length — see IV DATA LENGTH SPECiFICATION. The destination data is merged with data in the líO latches to finalize the lV bus data. Hence, a one-to-eight bit destination data field can be inserted into the existing B-bit l/O port without modifying surrounding bits. If both the source and destination fields specify lV bus data (208-378), the "L" field specifies the length of both the source and destination data.. Ñ. data (No. o. 1. 2. 3. 4. 5. 6. i i. [. !. i. l. I. i l. i. l. I. I. I. |«. specifícation Function Specified). i. I. l. l. !4. l. l. i. l. 1%. l. i. I. I. I. l. 1<. A. A. 7. l. 1<. l l l l l. =. 1. = 2 = 3 = 4 = 5. L = 6. |<. = 7. L = O. To form the source data, the iV bus input data is rightrotated according to the source address and then masked to the required length—see N DATA LENGTH SPECIFICATION. If length is less than 8 bits, all remaining bits are set to zero before processing in the ALU. To form the destination data, the ALU output is left-shifted according to the destination address and masked to the required length sp,e,cification. The destination data is then merged into the lV bus data that was used to obtain the source; thus, if the sourc.e and destination addresses are on the same bank, the IV bus data written to the destination I/O Port appears unmodified, except for bits changed during the shift-and-mask operations. If the source and destination addresses refer to different banks, the destination l/O Port is changed to contain the contents of the source I/O Port in those bit positions not affected by the destination data.. . . . , Field. The 5-bit. or B-bit. "J" held is used to load a hteral value (contained in the instruction) into a register, into a variable I/O data field, or to modify the low-order bits of the Program Counter. The bit length of the "J" field is im" plied by the "S" and "L" fields in the XEC, NZT, and XMIT instructions, based on the following conditions:. j. " When the Source (S) field specifies the literal value of the "J" field number.. internal register, is an B-bit binary. an. l/O data " When the Source (S) field specifies a variable a 5-bit binary field, the literal value of the "J" field is number.. A Field. The 13-bit "A" field is an address field which allows the 8X305 to directly branch to any of the 8192 locations in Program Storage memory.. Formation. of Instruction. Address. The Address Register and Program Counter are used to from generate addresses for accessing an instruction program storage. The instruction address is formed in one of the following ways:. length. Rotate. 1984. NZT · For all except the JMP, XEC, and a "satisfied" instruction, the Program Counter is incremented by one and placed in the Address Register. For the JMP instruction, the 13-bit "A" field contained in the JMP instruction word replaces the contents of both the Address Register and the Program Counter.. '. · Forthe XEC instruction, the Address Register is loaded with bits from the Program Counter modified as follows: XEC using lV Bus Data — low-order 5 bits of ALU output replaces counterpart bits in Address Register XEC using Data from Internal Register — low-order 8 bits in bits of ALU output replaces counterpart Address Register The Program Counter is not modified for either of the above conditions. NZT instruction, the low-order 5 bits · For a "satisfied" {NZT source is N bus data) or low-order 8 bits (NZT source is an internal register) of both the Address Register and Program Counter are loaded with the literal value specified by the "J" field of instruction word.. Data Addressing The source and/ordestination addresses of the data to be operated upon are specified as part of the instruction word. As shown earlier, sourceldestination addresses are specified using a 5-bit code (008-378). When the most significant octal digit is a "O" or "1", the source and/or destination address is an internal register; if the most significant digit is a 2 or 3, an Ñ bus operation is indicated — 2 specifying a Left-Bank (W) operation and 3 specifying a Right-Bank (Á"l) operation. The least significant octal digit (O through 7) indicates either a specific internal register address or positioning information for the least significant bit when specifying N bus data. Referring to Table 1, AUXiliary register FlO (008) is the implied source. Signetics. 13.

(14) BIPOLAR. MARCH. LSI PRODUCTS. 8X305. MICROCONTROLLER. of the second argument for the ADD, AND, and XOR operations. IVL register R7 and IVR register R17 {destination addresses 078 and 178, respectively) provide a means of routing enabling address information to l/O peripherals. With IVL orlVR specified as the destination address, data is placed on the lV bus during the output phase of the instruction cycle; simultaneouMy, a Select Command (SC) is generated to inform all l/O devices that information on the lV bus is to be considered as an l/O address. Since the contents of IVL and IVR are preserved, either register may later be accessed as a source of data.. DESIGN. Control outputs LB and FIB are used to partition )/0 bus in the devices into two fields of 256 addresses. With a of active-low state and source address 208-278, the left bank of (/0 devices are enabled during the input phase of the instruction cycle. With RB in the active-low state and a source address of 308-378, the right bank of devices are enabled. During the output phase, LB is low if the destination address is 078 or 208-278, whereas RB is low if the destination address is 178 or 308-378. Each address field (LB and RB) can have a different l/O device selected, that is, data can be transferred from a device in one bank to a device in the other in one instruction cycle.. G. PARAMETERS. Hardware design of sists of the following. an. 8X305-based system largely conoperations:. " Selecting and interfacing ROM, PROM, etc.. a. Program Storage device. All information required for easy implementation of these design requirements is provided under the following captions:. —. " Selecting and interfacing input/output devices — RAM, Ports, and other B-bit addressable l/O devices. Choosing and implementing System Clock — Capad" tor-Controlled, Crystal-Contrdled, or Externally-Driven. Selection of an off-chip series-pass transistor. ". · · · ·. Ordering Information Voltage Regulator DC Characteristics AC Characteristics. . Timing CQns¡derations · Clock Considerations HALT/RESET Logic. ·. VOLTAGE. REGULATOR. PARAMETER. All internal logic of the 8X305 is powered by an on-chip · voltage regulator that requires an external series-pass transistor. Electrical specifications for the off-chip power transistor and a typical hook-up are shown in the accom. , , , , , lead ,inductance, the trandiagram. To mimmize panying sistor should be as close as possible to the 8X305 package and the emitter should be ac-grounded via a 0.1 microfarad ceramic capacitor.. 14. 4984. CONDITIONS. LIMITS. YCC. —)""'. YCC 37, 'reg. W. i"' '°'". hfe. VCE=2V; > 50 1OOmA < lC < 50QmA. vbeon. \/ce =5v;. YCESAT. lC = 50OmA; lB = 50mA < 0.5V. 8x305. "'. '. T. + O.1uf YCR. ,r~-. note: = Typical approved pans—2N5320,. Signetics. jc = 50OmA < lV. BVCEO. > 15V. f,. > 30mhz. 2N5337.

(15) MARCH. LSl PRODUCTS. BIPOLAR. 8X305. MICROCONTROLLER. (Commercial. DC CHARACTERISTICS. Part). ABSOLUTE MAXIMUM RATINGS Temperature (Tstg) ratings are from. Storage. PIN. DESCRIPTION. Vcc. Supply. XI,. X2. 1984. -. to. < Vcc. voltage. ". 5.25v,. 70°c. < Ta <. o°c. + 150°C PIN. UNIT. RATING. voltage. Crystal input. 65. 4.75v. + 7.0. V. 2.0. V. All. other. Logic. input. UNIT. RATING. DESCRIPTION pins. V. 5.5. voltage. LIMITS PARAMETER. Ycc Yih. Supply High. TEST. voltage. level. input voltage Yil Voh. Max. 4.75. 5.0. 5.25. 0.6. 2.0. 2.0. 5.5 0.4 0.8. High. level. Low. Ycc. voltage. level. Kc. Input clamp voltage. Ycc. level. kc. input current. min;. loH =. 3mA. -. min;. |OL = 6mA |OL = 16mA. Vcc. = 5V. =. Ycc=. Regulator voltage. High '. = min;. Vcc. output voltage. Ycr. 4h. Typ. level. output Vol. Min. input voltage. Low. = min;. V. V. 2.4. -. 0.55. V. 0.55. Low-level. Ycc. input current Short circuit output current. |cc. Supply. |cr. Yil. Ycc. = max; than. more. (Note:. 1OmA. -. At. time,. any. output should connected to ground.) Ycc. current. Regulator control. Vcc. Regulator current. Ycc. AC CHARACTERISTICS. (Commercial. I). V. -. 30. through A12 other outputs. have. pins. inputs XI and X2 internal clamp diodes. and. XI. µA. Allother XI. -0·2. -. —. 10. -. pins. lVO-lV7. mA. ÍO-i15. 0.4. HALT. and. RESET. 140. 25. mA. Al!. mA. TA=70°C. pins. JÁ = O°C Max. mA. available. series-pass. Part) conditions:. 4.75v (See. ycc 5.25v; test circuits). ". ". (INSTRUCT1ON TIME Typ. LIMITS. = 20Ons) Max. CYCLE Min. o°c. <. t,, < 70°c. (INSTRUCTION TIME Typ. > 20Ons). UNITS. ns. XI. 100. 100. ns. Tch. XI clock. high. 50. 50. ns. Tcl. XI. low. 50. 50. Rcl. MCLK. low. Tyy. MCLK. pulse. Tmodo. Output MCLK. delay. width. driver. turn. falling. edge. on. time. 15. 40. 40. 60. 125. 145. Signetics. ns. 15 T4q. 40 10. T4q+. T1q + T2q+ 25. T2q+. -. COMMENTS. Max. 200. time. for. has been reached.. 200. clock. drive. Ta = O°C. Processor cycle time time. base. transistor. TA=70°C. mA. 230. output. Tcp. period. not. X2. Tpc. clock. do. X2. and. 1.6. 200 = max. Min. Aq. X2. mA. 195. = 5.OV. CYCLE. other. Crystal. 1.5. 180. LIMITS (Note. and. All. pins. no be. LOADING:. PARAMETER. XI. 50. -. = max. Notes: 1. Operating temperature ranges are guaranteed after thermal equilibrium 2. All voltages measured with respect to ground terminal.. X2. 4.0. _. = 0.4V. one. other. Ta= O°C Ta=70°C. V. -. fos. lREg. = max;. and. All. 3. )il. XI All. V. Yih = 0.6V V|h = 4.5V. = max. V. ::. ||n =. COMMENTS. UNIT. CONDITIONS. Lq. ns 10. ns. Note. 2. 45. ns. Note. 9. +. 15.

(16) BIPOLAR. MARCH. LSl PRODUCTS. 8X305. MICROCONTROLLER. AC CHARACTERISTICS. (Commercial. Part) conditions: LIMITS. (Note. CYCLE. I). Min Td'. Output (SC/WC. driver. Input. Tmhs. MCLK. falling. Tmhh. HALT. hold. Rcc. Program 1/0. data. edge. time. Tmas. MCLK. "fú. Instruction to. TlVA. Input. Tm{s. MCLK. Tm|h. falling. Tmwl. TMiBs Tl|E3S. falling. edge. MCLK. falling. (Input. phase). Tm|dh. 105. edge. edge). address. stable. time. to. SC/WC. to. LB/RB. LB/RB. falhng. Lods. Output. data. 20Ons). UNITS. edge. to. edge. to. data. hold. stable. (MCLK. edge). 2. ns. Notes2,3&4. 140. T2q+90. ns. Notes2,3&5. 85. 85. ns. T2q+. T1q. La. -. 20. 5. ns. T,q+. +. T2q+. 5. ns. T2q+. 25. Note. 2. ns. Note. 2. ns. Note. 2. Note. 2. ns. 10. 25. 10. 25. ns. 25. ns. 145. T2q+. 15. 55. Lq T2q+. T2q+. 45. T: :q. +45. + 15. 11. 130. 150. Lq + T2q+30. No t es 2 & 8. ns. 15. T,q +. 2 & 10. 2. 5. T1q +. Notes3&6 Notes. Note. ns. 15. 11. falling. 2. Note. T1q + 40. 115. time. Note. ns. 5. stable. 10. ns. ns. 25. edge). 20. -. 30. LB/RB. input. T1q. Note. ns. ns. 125. 115. COMMENTS. Max. 105. T1q+. phase). (Input. 85. 30. 105. Input data hold time falling edge). Output data. >. ns. 140. SC/WC. to. (MCLK. (MCLK. TIME. 60. 55. phase). ©odh. 70°c. :£. T1q+15. input). edge). edge. falling falling. t,. (INSTRUCTION. Typ. Min. 30 65. to instruction stable. edge. Instruction to MCLK. CYCLE. o'c g. 20. address. edge. falling falling. MCLK. Max. edge. MCLK. TMlDS. Typ. time. to. edge. Instruction falling. (Output. =. LIMITS. 20Ons). to address. (MCLK. Gobs. TIME. time. lV data. hold. rising. falling. falling. access. edge. falling. MCLK Tmwh. (INSTRUCTION. 85. HALT. to. (MCLK. enable. to valide. data. s v,, < 5.25v; test circuits). 20. to output data. output. (LR/RB. (See. edge). storage. port. time. turn-on. risíng. %d. TlO. 4.75v. LOADING:. (Continued). PARAMETER. 1984. ns T1q +. T2q+50. ns. notes: 1. XI and X2 inputs are driven by an external pulse generator with an amplitude of 1,5volts; all timing parameters are measured at this voltage level. 2. Respectively, T1q) T2Q) T3Q, and T4Q represent time intervals for the first, second, third, and fourth quarter cycles. 3. Capacitive loading for the address bus is 150 picofarads. 4. TMAS is obtained by forcing a valid instruction and an I/O bus input to occur earlier than the specified minimum set up time. 5. T|A is obtained by forcing a valid instruction input to occur earlier than the minimum set up time. 6· T|VA is obtained by forcing a valid líO bus input to meet the rninium set up time. 7. TM|S represents the setup time required by internal latches of the 8X305. In system applications, the instruction input may have to be valid before the worst-case set up time in order for the system to respond with a valid líO bus input that meets the I/O bus input set u.p.t.i.m.e(TlDS and TMlDS)· 8. TM|H represents the hold time required by internal latches of the 8X305. To generate proper LB/RB signals, the instruction must be held valid until the address bus changes. 9. The minimum figure for these parameters represents the earliest time that l/O bus output drivers of the 8X305 will turn on. 10. This parameter represents the latest time that the output drivers of the input device should be turned off.. 16. Signetics.

(17) 1984. MARCH. LSl PRODUCTS. BIPOLAR. 8X305. MICROCONTROLLER. TEST CIRCUITS other. address. : :::::e$t'. 5v. 5v. l""'. )""'. ). iI. 379{!. l ABSOLUTE. MAXIMUM. PIN. Supply X2. Crystal input. DC CHARACTERISTICS. (Military. Part). 4.5v. ratings. (Tstg). Temperature. are. from. PIN. UNIT All. V. + 7.0 2.0. voltage. ). L T. 169ñ. RATING. voltage. :::'t.st°. 150pf. Storage. DESCRIPTION. Vcc. XI,. RATINGS. ?:. other. -. 65. to. 30Opf. + 150°C. input. UNIT. RATING. DESCRIPTION. Logic. pins. pins. V. 5.5. V. v,,. s. s. 5.5v,. -55°c. g. t,. ,£. +125°c. LIMITS TEST. PARAMETER. Ycc. Supply. Yih. High. Vjj,. Low. Voh. High. voltage. Min. Typ. Max. 4.5. 5.0. 5.5. Yol. Low. level level level. .input voltage. V. 2.0 0.4. . voltage input. 0.8 Vcc. output voltage. Ycc. output. voltage. Vcc. = min;. =. Kjh. = |ol =. 3mA. All. other pins. V. XI. and. All. other pins. Aq. through A12 other outputs. 6mA. 0.55 0.55. V. Regulator voltage. Vcc. =. 5V. All Tc. 3.5. Ycr. V. 3.1. hi-i. Input High. clamp. level. voltage. Ycc. input current. Vcc. = min;. 2.6. I||y =. -. 1OmA. -. Yih = 0.6V V|h 4.5V. = max. 1.5. V. =. -. 4l. input current Vcc. Short. |os. circwt output current. |cc. Supply. |reg. |cr. Vcc. no. Yil. = max;. = max; (Note: than one be connected. more. At any time, output should to ground.). XI. and. All. other pins. XI. and. -. 1.6. = max. Regulator control. Vcc. = 5.OV. Regulator current. Ycc. = max. 205. -. 10. -. 25. mA. notes: 1. Operating temperature ranges are guaranteed after thermal equilibrium 2. All voltages measured with respect to ground terminal.. X2. 10-115 HALT. and. RESET. mA. All. mA. T =125°C c Tc = 55°C. mA. 180 260. X2. lVO-lV7. 0.4. 140. X2. diodes.. µA. 175. Ycc. current. inputs XI and internal. have. mA. 30. not. 50. -0.3. -. 55°C. 4.0. =. = 0.4V. do. clamp. 3. Low-level. X2. Tc = O"C Tc= 125°C Crystal. Yic. X2. V. 2.4. loL = 16mA. min;. = min;. -. XI. and. V. 2.0. 0.6 level. COMMENTS. UNIT. CONDITIONS. mA. output pins. -. Max. available. for. series-pass. base. drive. transistor. T 125°C c = 55°C Tc =. -. has been reached.. Signetics. 17.

(18) BIPOLAR. MARCH. LSl PRODUCTS. 8X305. MICROCONTROLLER AC CHARACTERISTICS. (Military. Part)coND(TIoNs: LOADING:. PARAMETER. (Note. I). Processor. Tcp. XI. clock. period. Tch. XI. clock. high. cycle time. Tcl. XI clock. Tmcl. MCLK. low. Tw. MCLK. pulse. Tmodo. Td|. time. low. delay. width. Output. driver. turn-on. (MCLK. falling. edge). Output. driver. turn-on. (SC/WC. Input. Tmhs. MCLK. falling. Tmhh. HALT. hold. Tacc. Program. Tmas. data. (íÉ/iíS. falling. MCLK. Iva. Input. Tm|s. MCLK. Tmwl. TMlBS TIlBS. data. JÚds TMlDH. Tmodh. Tmods. falling. falling. access. edge. TIME. MCLK. falling. falling. edge. MCLK. falling. (Input. phase). edge. edge. edge. edge. Instruction to falling. (Output. to instruction. Input. data. edge. hold. falling. >. 250ns). UNITS. ns. 125. ns. 62. 62. ns. 62. 62. 15. 40. 47. 72. 145. 175. ns. 15 T4q. 40. ns. 15. T4q+10. ns. Note. 2. 20. T2q+50. ns. Note. 9. ns. Note. 10. -. T1q + T2q+. T1q +. 20 115. 80. 115. 40 80. T,q T1q+18. ns 22. -. LB/RB. to. (Input. data. falling. Output. data stable falling edge). 2. ns. Note. 2. ns. 40. ns T1q +. ns. Notes2,3&4 Notes2,3&5. 160. T2q+98. ns. 90. 90. ns. 40. T1q. 22. -. T1q + 8. 154. Lq. ns T,q. +. T2q+. 2. ns. +. T2q+. 29. Notes3&6 Notes. 2 & 10. Notes2&8 Note. 2. ns. Note. 2. ns. Note. 2. Note. 2. Note. 2. ns. to. input. hold time edge). 5. 25. 5. 25. ns. 10. 35. 10. 35. rs. 30. ns. phase). LB/RB. time. Output. Note. SC/WC. to. to. ns. 90. 160. 127. COMMENTS. Max. 250. SC/WC. edge). (MCLK. (MCLK. Typ. Min. 125. 70. to. LB/RB edge. faling. (MCLK. Max. 250. stable. 30 140. phase). MCLK. Typ. address. Instruction hold time falling edge) falling. 125"c. (INSTRUCTION. stable. (MCLK. edge. <. T2q+35. to. MCLK. t,. CYCLE. 250ns). to address. rising. ,£. LIMITS. =. time. address. 55"c. (INSTRUCTION. input). to. -. TIME. edge. edge). < 5.5v;. LIMITS. time data. v,,. CYCLE. 80. HALT. (MCLK. ,s:. test circuits). 20. data. to. N. falling. MCLK Tmobs. time. to valid. Instruction. Tmwh. edge. output.e.nable. T|a. Tm|h. time. to output. storage. l,/.O.po.rt. time. edge). rising. %d. TlO. time. 4.5v (See. Min Tpc. 1984. data. 170. stable. T1q + T2q+. T,q 15. C?. 75. + 45. T2q+. +50. 140. Gq + T2q+15. ns. 11. 11. ns. 150. 180. Lq + T2q+25. T1q +. T2q+55. ns. notes: 1. XI and X2 inputs are driven by an external pulse generator with an amplitude of 1.5 volts; all timing parameters are measured at this voltage level. 2. Respectively, T1Q7 T2Q7 T3Q, and T4Q represent time intervals for the first, second, third, and fourth quarter cycles. 3. Capacitive loading for the address bus is 150 picofáradc. 4. TMAS is obtained by forcing a valid mstruction and an l/O bus input to occur earlier than the specified minimum set up time. 5. 4a is obtained by forcing a valid instruction input to occur earlier than the minimum set up time. 6· TlVA is obtained by forcing a valid llO bus input to meet the minium set up time. 7. TMlS represents the setup time required by internal latches of the 8X305. In system applications, the instruction input may have to be valid before the worst-case set up time in order for the system to respond with a valid l/O bus input that meets the l/O bus input set up time (T|DS and TM|DS)' 8. TMlH represents the hold time required by internal latches of the 8X305. To generate proper LB/RB signals, the instruction must be held valid until the address bus changes. 9. The minimum figure for these.parameters represents the earliest time that l/O bus output drivers of the 8X305 will turn on. 10. This parameter represents the latest time that the output drivers of the input device should be turned off. 18. Signetics.

(19) Lsi. bipolar. march. products. 8X305. MÍCROCONTROLLER. TIMING. 1984. CONSIDERATIONS. Part). (Commercial. Timing parameters for the 8X305 are normally measured with reference tc MCLK.. As shown in the AC CHARACTERISTICS table for the commercial part, the minimum instruction cycle time is 200 . . . nanoseconds; whereas, the maximum is determined . by the on-chip oscÚlator frequency and can be any value the user chooses. With an instruction cycle time of 200 . . nanoseconds, the part can be characterized in terms of absolute values; these are shown in the first "LIMITS" column of the table. When the instruction cycle time is greater than 200 nanoseconds, certain parameters are cycle-time dependent; thus, these parameters are specifled in terms of the four quarter cycles ¶1q, Lq, Lq, and T4q) that make up one instruction cycle — see 8X305 TIMING DIAGRAM. As the time interval for each instruction cycle increases (becomes greater than 200 nanoseconds), the delay for all parameters that are cycle-time dependent is likewise increased. In some cases, these delays have a significant impact on timing relationships and other design; subsequent paragraphs areas of systems describe these timing parameters and reliable methods of calculation.. cycle time are:. . . . for the lnstrUct!on System determinants , . . 8X305 withm the Propagation delays · of Program Storage , Access time . of Enable the líO port time ·. Normally, the instruction or more of the following Condition. 1. Condition. 2. Condition. 3. —. —. —. cycle time is constrained conditions:. by one. Instruction or MCLK to LB/RB (input phase) plus l/O port access time (TÍO) s: lV data set up time (Figure 5a). Program storage access time (TACC) pIus instruction to LB/RB (input phase) plus l/O port access time (TlO) pius lV data (input phase) to address s instruction cycle time (Figure 5b). Program storage access time plus instruction to address g instruction cycle time (Figure 5c).. Ii)) 1/) /)Í'2)N.)/ '. '. ). '. '. '. 'BgR'l ív0-{v7. CD mclk to rBAe,(i,n,put phase) or instruction to LB/RB (input phase). G). J/O port access (TÍO).. @. JV data set·up time (roferenced mclk).. a. Condition. I l l. ) t } l. ,Á@!~®:. } l t. ';7/. Á. '. I 1. 7. :. , / 1. (j). Program storage access time.. ®. MCLK to íe/TB,(inEut phme) or instruction to íá/RB (Input phase).. I. ). i. '. l i i. addrS"|,. jTO. '. '. '. i bj. program. ' '. storage access. ® I/O port access (TÍO). ® Ñijata (input phase to address.. to. #1. b. Condition. Figure. 5.. Constraints of. 8X305. #2. Instruction. Signehcs. c. Condition. Cycle. #3. Time. 19.

(20) BIPOLAR. MARCH. LSI PRODUCTS. MICROCONTROLLER. 8X305 TIMING. 1984. 8X305. DIAGRAM TPC. g TCP. q TCL. q. P. XI 1. >. P. _. TCH. P. 2. 4. 3. P,"',4. MCLK TW. m TMAS. q. W////Z,. """". (AO-A12) ). l. |q. TIA. J. TtVA. q. '": :-:::°'. T,ÁGC. T. I. l. SC/WC. TMM. ad. ,,,,t,;. """". P. "'"'1. · l. ,X. X ) TMOBe. :. .. )¢mssm(. °""". ""'. TMlDH. <. µµ! :. Whs ->". ~—-. """. q. X. '\ m m SNDÉCATES CHANGINGDATA 3-STATE INDdCATES. l For an ¡n8trtjction cycle time greater than 200 ns I , the \/0 bü3 can be Meble mmetime within the I 'q l third quarter (T3Q) cycle. Id l l lq l l lq I l :. lq. ». , MOD. °"""'. I. P. 'I I. INPUT. PHASE t l. '. l ( l SC=WC="(j". t LA RS BotfOrinput dmB ' l LiÓ dñvwbKtM0D-8t¿!Á0 i ! I/'O roc0WorsOPQbñ ) l l l l j l. Signetics. b l PI a I. OUTPUT. PHASE. '. r I hmtructionMdroos á-K high——PJ , 'I ' changm ' I s l SC = "1" for l/O > i [ p ' :1"' " , we = "1" for l/O derta l ' I 16, A6 Qt for output dda j R P { ' l I l Pl l/O driv0r$MtND if outurt data or ad&o88 to l/O BUS;thew0tEe otMrwia _~Á l P l ( l I I l tm ~"). ~. r~_. -r~~o. ( ONECYCLE l. =. l l i. u+. "q—. :. l. "MODS. Irmruction open. Note:. TD[). t. TMODO THHIII. " 1· l. ,j. TMIDS. 'd ,q. "". TMWH '. L,,,. TMWL L. / /. l. ' '. -~q. P. I '. wá ". m. i. , <. y//qz. ,. I. P. kw77ww7////7////////(//'Á. %}z>/">z/"z>>/"zzz/"zg//k//////>/I/I/gÁ. '. 20. P. k. { l. i l I I i l ) I. l. l p I i. *slmm.