SLAVE LOGIC

SLAVE LOGIC ANALYZER

2302-5012-00

July 1981

GenRadjDevelopment Systems Division 5730 Buckingham Parkway

Culver City, CA 90230

REVISION HISTORY Title

Slave Logic Analyzer RELATED PUBLICATIONS

Slave Emulator Control Unit Hardware, Reference Manual

_GenRad

e GenRad/DSD,. 1981

0-2 Revision History

Number

-

Date Notes

2302-5012-00 ^7/81 First Edition

2302 -5000· .. 00

2302-5012-00

PREFACE,

This manual introduces and discusses the concepts of Slave Logic Analyzer operation. It prepares the user to i nsta 11 and operate the SLA for debuggi ng prototype system in real time. Special emphasis is given to system commands and console displays.

This manual consists of:

Chapter 1, INTRODUCTION, covers the basi cs of the Slave Logic Analyzer subsystem, specifications, and documentation.

Chapter 2, SERVICE AND provisions of customer information.

MAINTENANCE, describes servi ce and parts Chapter 3, INSTALLATION, di scusses Logi c Analyzer support and installation.

Chapte~ 4, OPERATION, narrates the technique of invoking the Slave Logic Analyzer, presents general operation of the system, defines. the use of commands, and details the finer points of Logic Analyzer operation.

The information in this manual is subject to change without prior notice.

Please note that a Documentation Reply Card is included in this manual. When you complete and return it, you help us produce better documentation for you.

A User Regi stration Card is i ncl uded in the set of manual s you recei ve with your GenRad/DSD system.: When you compl ete and return the User Registration Card, you ensure that you will receive all updates and new information for your configuration.

For your convenience, a 1 ist of GenRad/DSD Service Locations is appended to this manual.

CONTENTS

PAGE CHAPTER 1 - INTRODUCTION

.1.1 PURPOSE AND SCOPE 1-1

1.2 SLA OVERVIEW 1-1

1.3 SLA SUBSYSTEM DESCRIPTION 1-2

1.3.1 The· SLA Card 1-2

1.3.2 SLA Card Digest 1-2

1.4 SPECIFICATIONS 1-4

1.4.1 The SLA Card 1-4

1.4.2 Cable Assembly, Internal (LA-P3 To EP-P3) 1-4 CHAPTER 2 - SERVICE AND MAINTENANCE

2.1 CUSTOMER SERVICE

2.2 INSTRUMENT RETURN 2-1

2-1 2-1 2-1 2-5 2-3 2-6

2-8

2-15 2.2.1 Returned Material Number

2.2.2 Packaging 2.3 PARTS LIST

2.4 IC INFORMATION

2.5 MNEMONIC DESCRIPTIONS 2.6 LOGIC SCHEMATICS . 2.7 ASSEMBLY DIAGRAMS CHAPTER 3 - INSTALLATION

3.1 PREPARATION

3.2 INSTALLING THE SLA SUBSYSTEM 3-1

3-2

CONTENTS. (COntinued)· '.

CONTENTS (Concluded)

CHAPTER'4 .. OPERATION"

4.1 INTRODUCTION

4.1.1 Command Definitions 4.2 GENERAL OPERATION

4.3 DETAILS OF LOGIC ANALYZER OPERATION 4.4 COMMANDS

4.4.1 Wi ndow Mode Conmand 4.4.2 Mode Conmand

4.4.3 Breakpoint Command 4.4.4 Qualify Trace Command GENRAD/DSO'SERVICE LOCATIONS

0-6 Contents

PAGE

4-1 4-2 4-4 4-3 4-7 4-8 4-15 4-18 4-19

2302-5012-00

ILLUSTRATIONS

FIGURES PAGE

1-1 Logic Analyzer Block Diagram 1-3

2-1 Logic Schematic Section 2-9

3-1 Emulator Rear View 3-3

ABBREVIAT,IONS' .

ABBREVIATION ADS

ASCII AWG, BCD BP CAP BUF CER CONN CPU DIP DR DSD EP FF GND HEX

It

LA INV

LB/SQ IN.

":MEM LED MOT MUX MV OCTD OSC POS PROM RAM PWB REC RIB SEL ROM SIP

SLA

SPR ST TANT TI

2302·5012-00

DEFINITION

Advanced Development System

American Standard Code for Information Interchange'

American Wire Gauge Binary Coded Decimal Breakpoint

Buffer Capacitor Ceramic Connector

Central Processor Unit Dual In-line Package Driver

Development Sys·tems Division Emulator Personal ity

Flip-Flop Ground Hexadecimal

Integrated Circuit Inverter

Logic Analyzer

Pounds Per Square Inch Light Emitting Diode Memory

Motorola Multiplexor Multivibrator Octal

Oscillator Positive

Programmable Read Only Memory Printed Wiring Board

Random Access Memory Receiver

Ribbon

Read-Only Memory Select

Single-In-Line Package Slave Logic Analyzer Sprague

State Tantalum

Texas Instruments

Abbreviations 0-8

CHAPTERt

INTRODUCTION

1.1 PURPOSE AND SCOPE

The purpose of this manual is to inform and instruct the user specifically about the Logie Analyzer portion of the Slave Emulator. The depth of coverage is sufficient for the intended purpose. This manual has been prepared

assuming the user has a knowledge of GenRad Advanced Development System operation, including the Sl ave Ernul ator.

1.2 SLA OVERVIEW,

The SLAsimp1ifies. debugging and. troubleshooting tasks by displaying detailed pictures of time-related events within digital circuits. This allows the user to view bus data during program execution.

The SLA has a sampling rate of 10MHz. Information is recorded synchronously with the system, and stored in an area of memory contained in the SLA hardware.

The SLA samples and stores. a maximum of 256 traces for up to 24" address lines, up to 16 data lines, four external user-defined lines, and 20

processor-dependent lines. A hardware register (Trace Qualifier) selects the trace to be stored in SLA memory.

These and other detail s are exp1 ai ned in Chapter 4, OPERATION.

1.3 SLA SUBSYSTEM DESCRIPTION

The SlA subsystem consists of one 2302-4746-01 logic Analyzer card and one 2302-0234-01 Cable Assembly for Internal lA-P3 to EP-P3 connection.

1.3.1 THE SLA CARD

Th~' bogic'Analyzer '-ls'"a'stand'ara Sl ave Emulator card with two' rear double-sided edge connectors, P3 and P5, for interfacing the Breakpoint and Emulator

personality cards. The front edge connectors, PI and P2, plug into the motherboard (backpl an e) • PI and P2 are identical on all Ernul ator cards.

There are approximately 122 components on this card, containing 256x4 RAMs, assorted IC logic arrays, resistor PAKs, a 20MHz crystal oscillator,

capacitors and resistors.

1.3.2 SLA CARD DIGEST

The SlA card records bus signals during emulation, beginning at a specific event which is predetermined on the breakpoint card. The SlA 24-bit cycle counter records, the time (or bus cycle) between two events. These two events are detected ,by Breakpoints land 2. Breakpoint 1 starts the count and

Breakpoint 2 ends the count. The SlA card records specified bus cycles dete.rmi ned by the trace qua 11 fi e r.

The SlA block diagram is shown in Figure 1-1. Notice that memory logic falls into two groups:

(1) mai n memory and (2,) memory address counters. Traces are stored in si xteen 256 x 4-bit main memory RAMs. Information to be stored can be restricted to a READ or WRITE to a specified location. The memory addresses are two 4-bit synchronous counters for addresses AO through A7.

Data latches coming off the bus consist of 24 address lines (BAO-BA23), 16 data lines (BOO-BOIS), and four control lines (X6, R/W-, X17, and BHE).

Non-bus signa·ls are 16 processor-dependent inputs {XO-X1S} and four external conditions (ECO-EC3).

The timinglogic'conststsof a 20MHz crystal clock source and a lO/IMHz

real-time clock, a clock selector, and a 24-bit cycle counter working into the bus through a buffer array carrying BOO-B07.

1-2 Int roduct ion 2302-5012-00

MEMORY

:>

ADDRESS COUNTER

U20, U33

v

NOTE

Symbols inside blocks refer to IC DIPS on Schematic, Logie Analyzer, 2302-4746. For example, U4, U5, U6, U38-42 are data latches.

EXTERNAL CONDITIONS

, I

V

PROCESSOR DEPENDENT

, I

~

U6 DATA 1ATCH U4, U5 U12- 19, U25-,32

64 X 256 MEMORY ARRAY

TRACE QUAL! FI ER (FROM BP CARD)

, I

~

10/1 MHZ REAL-TIME

CLOCK -U2, U8

CLOCK 24 BIT

DATA LATCH U4, U38-42

(/') (/') UJ 0:::

Cl Cl ex:

v

SELECTOR r-- CYCLE COUNTER

U10 U34-36

1\

v

BUFFER U46-48

1.4 SPECIFICATIONS 1.4.1 THE SLA CARD

Width:

Length:

Thickness:

Weignt::,~

9 inches (23 cm) 12 inches {30 cm}

.06 inches (1-1/2 mm) 8·oz. (226.8 grams)

1.4.2 CABLE ASSEMBLY,INTERNAL (LA-P3 TO EP-P3) Overall Length: 3.25 inches {8 cm}

1-4 lntroducti on 2302 -5012 -00

CHAPTER 2

SERVICE AND MAINTENANCE

2.1 CUSTOMER SERVICE

Our warranty (at the front of this manual) refers to the materials and workmanship of our product. If a malfunction occurs, our service engineers will assist in any way possible. If the difficulty cannot be eliminated by use of the following service instructions, please write or phone the nearest GenRad/DSD ser.vice. facility, giving full information about the trouble and the steps taken to remedy it. Describe the instrument. by name, catalog number, serial number, and ID lot number if any. (Refer to front and rear panels.)

2~2 INSTRUMENT RETURN

2.2.1 RETURNED MATERIAL NUMBER

Before returning an instrument to a GenRad/DSD facility for service, please ask our nearest office for a "Returned Material" number. Use of this number

in correspondence and on a tag tied to the instrument will insure proper handling and identification. After the initial warranty period, please avoid unnecessary delay by sending a purchase order number.

2.2.2 PACKAGING

To safeguard your instrument during shipment, please use packaging that is adequate to protect it from damage during shipment. Use of the original packaging is preferable. Any GenRad/DSD field office may advise or provide packing material for this purpose. Contract packaging companies in many cities provide dependable custom packaging on short notice. The three recommended packaging methods are:

a. Rubberized Hair b. Excelsior

c. Bubble Pack

a. Rubberized Hair. Cover painted surfaces of instrument with protective wrapping paper. Pack instrument securely in strong protective corrugated container (3501b/sq. in., bursting test), with 2-inch rubberized hair pads placed along all surfaces of the instrument. Insert fillers between pads and container to ensure a snug fit. Mark the box "Delicate

Instrument" and seal with strong tape or metal bands.

b. Excelsior. Cover painted surfaces of instrument'with protective wrapping pape·r. ·.Packinstrument·instrong corrugated container (350 lb/sq. in., bursting test), with a layer of excelsior about six inches thick packed fi rmly against all surfaces of the instrument. Mark the box "Del icate Instrument" and seal with strong tape or metal bands.

c. Bubble Pack. Bubble packs are continuous thin sheets of clear double sealed plastic material with bulging air bubbles spaced along the sheet to act as cushions. Cover painted surfaces of instrument with protective wrapping paper. Pack instrument in strong corrugated container (350

lb/sq. in., bursting test), with several layers of bubble pack wrapped firmly against all surfaces of the instrument. Mark the box "Del icate Instrument" and seal with strong tape or metal bands.

2-2 Service And Maintenance 2302-5012-00

2.3 PARTS LIST

These parts lists are only for the Logic Analyzer card and Internal Cable Assembly. When ordering parts, use the full description.

PARTS LIST

LOGIC ANALYZER 2302-4746-01

lITEM PART NO. QTY DESCRIPTION MFR MFR PART NO. SYMBOL 1 2302-0746-01 1 PWB, LOGIC ANALYZER

2 5431-8600-00 2 IC, 4/2-IN POS NAND TI SN74LSOON U3,24 3 5431-8761-00 1 IC, BINARY 4-BIT COUNT TI SN74LS161AN U7 4 5431-8630-00 1 IC, 8-IN POS NAND TI SN74LS30N U49 5 5431-8632 -00 1 IC, 4/2-IN POS OR TI SN74LS32N U37 6 5431-8674-00 1 IC, 2/D-FLIP-FLOP TI SN74LS74AN U8

7 5431-8686 .. 00 1 IC, 4/X-OR GATES TI SN74LS86N Ull

8

5431-8707-00 1 IC, 2/JK FLIP-FLOP TI SN74LSI07N U23 9 5431-8738-00 2 IC, 3-8 LINE DECODER TI SN74LS138N U21,22 10 5431-8751-00 1 IC, 1 of 8 DATA SEL/MUX TI SN74LS151N U10

11 5431-8761-00 2 IC, BINARY 4-BIT COUNT TI SN74LS161N U33,20 12· 5431-8775-00- . 1 IC, 4/D-FLIP-FLOP TI SN74LS175N U44

13 5431-8844-00 4 IC, 8/BUF-DRIVE-REC TI SN74LS244N U43,46,47,48 14 5431-8968-00 1 IC, 6/3-STATE INVERTER TI SN74LS368N U9

15 5431-8974-00 B IC, BID-FLIP-FLOP TI SN74LS374N U3B-42,4-6 16 5431-B993-00 3 IC ,2/4-BIT BINARY COUNT TI SN74LS393N U34-36

17 5627-1017-00 16 IC, RAM BIPOLAR 256x4 FC 93L422 U12-19,25-32 1B 7540-1B16-00 1 SOCKET, IC 16-PIN TI C-9316-02 TCI

19 5434-0206-00 1 OSC, 20 MHZ, 14-PIN DIP MOT KllOOA-20.MHZ U2 20 6099-2105-00 7 RES, 1K, 1/4W, 5% A-B RCOG7GFl02J RI-7 21 6740-2663-00 1 RES,PAK,9/4.7K,10-PINSIP CTS 750-101-R4.7K RPI 22 4431-4103-00 57 CAP, IC 01mf, 50V AVX MD015E103ZAA CB-64 23 4450-6260-00 7 CAP, 33mf, TANT, 10V SPR 196D336X9010KA1 Cl-7

1 2

4230-4751 .. 00 0034-6938-00

PARTS LIST

CABLE ASSEMBLY INTERNAL LA-P3 TO EP.P3

2 CONN CARD EDGE, 26 CONTACT 1 CABLE, RIB 26 CONDUCTOR, 28 AWG

2-4 Service And Maintenance

EP -P3 , LA-P3

2302-5012-00

2.4 IC INFORMATION

The integrated circuits used in the SLA logic are mostly all low-power

Schottky TTL's. Notice that the total number of pins per DIP are either 14, 16, 20, or 22.

X )_ J'! _N_ U M B E R

TYPE LOGIC DESCRIPTION GND vcc

74LSOO' 4/2-IN POS NAND 7 14

74LS161 BINARY 4-BIT COUNT 8 16

74LS30 8-IN POS NAND 7 14

74LS32 4/2-IN POS OR 7 14

74LS74 2/0 - FF 7 14

74LS86 4/X - OR 7 14

74LSI07 2/JK FF ^- 8 16

74LS138 3-8 LINE DECODER 8 16

74LS151 1 OF 8 DATA SEL/MUX 8 16

74LS161 4-BIT BINARY CO~NTER 8 16

74LS175 4/0 .~ FF 8 16

74LS244 8/BUF-DR REC 10 20

74LS368 6/3-STATE INV 8 16

74LS374 8/D - FF 10 20

74LS393 2/4-BIT BINARY COUNTER 7 14

93L422 256x4 BIPOLAR RAM 8 22

74S289 64-BIT RAM 8 16

74S08 2-IN POS AND 7 14

74S02 2-IN POS NOR 7 14

74S03 2-IN POS NAND O/C 7 14

7404 HEX INV 7 14

74221 Me-NOSTABLE MV 8 16

74LS04 HEX INV 7 14

74LS08 2-IN NAND 7 14

74LS10 3-IN NAND 7 14

74LS30. 8-1N NAND 7 14

74LS157 2 TO 1 SEL/MUX 8 16

74LS373 OCTD LATCH 10 20

8098 BUS 'DR INV, 3-ST 8 16

2.5 MNEMONIC DESCRIPTIONS

The following signal names were taken from the SLA schematic diagrams included in this manual. Most of the signals are those which traverse the bus. In other words, these signals go off the card. A signal which stays on the card is shown by an asteri'sk after its name. See notes.

NOTES:

MNt.MUNIC LUGIC ANALYZ.ER

LAS .. · Logic Analyzer Strobe BAO-BA24 Bus Address, 0-24 BDO-B014 Bus Data, .0-14

BHE+ Byte, High Enable

EPCYC- Emulation Processor Cycle

PRTY- Priority Error Input

MEM- Memory Cycle

IPWAIT- Interface Processor Wa1 t

RFSH- Refresh Cycl e

BYTE+ Byte - 8-Bit Operation

R/W- Read Write Cycle

HLOA";' Hold Acknowledge

MROY+ Memory Ready

~SAO+)-(SA2+) System Address, 0-2 BPl+)-{BP3+) Breakpoint, 1-3 BP10UT .. · Breakpoint 1, Out

EPI- Emu 1 ation Process.or Interrupt MAP- Memory Mapper .. Internal/External

TIME- Test Memory Enable

SYS+ System Address Enable

BP20UT .. Breakpoint 2, Output BPlIN-BP2IN Breakpoint 1-2, Input 100-1031 Input/Output, 0-31 (SAl+)-(SA3+) System Address, 1-3

BP2+ Breakpoint 2

BP4+ Breakpoint 4

LAI- Logic Analyzer Interrupt

WPROUT - Write-Protect

BP30UT - . Breakpoint 3, OUT

RSTPB- Reset Push Button

BP3IN- Breakpoint 3, IN

BP40UT- Breakpoint, OUT

(1)

g~

- means Active Low Bus Signals + means Active High Bus Signals

*

means Active Low Non-Bus Signals

2-6 Service And Maintenance 2302 .. 5012-00

2.5 Continued

MNI::MUNIG LUGIG ANAL HER

BP4IN- Breakpoi nt, IN

XO-X15 Processor-dependent Logic Analyzer inputs ECO;;;;EC3 "External Condition" 0-3

TQ Trace Qualifier for Logic Analyzer

BP2- Breakpoi nt 2

BP3- Breakpoint 3

00-07 Slave Emulator Bus Data, 0-7

CLRCNT* Clear address counter overflow bit.

CYCCNT "Cycle Count"

Enable counting of Breakpoint 3 cycling.

DATA STR Inverse of Logic Analyzer Strobe (LAS)

SELL*, Select read-data buffer for Logic Analyzer RAMS.

SELR* Enable Sell*

NOTES:. (1) (2) (3)

- means Active Low Bus Signals . + means Active High Bus Signals

*

means Active Low Non-Bus Signals

2.6 LOGIC SCHEMATlCS

The Logic Analyzer schematic, 2302-4746-01-S0, consists of five sheets.

Sheets 1 and 2 depict reference information, such as pin number and signal name, for Edge Connectors Pl, P2, P3, and P5. This information can be traced to logic inputs and- outputs on the remaining sheets. Each IC DIP is labeled with pin numbers, symbol, and I/O signals.

Ffgure2-1shows~ a~sectton 'of' Toglc extracted from Sheet 3. The bow-tie connector symbol represents bi-directional bus Signal flow. The number 1, within the left side of the bow-tie means Pl. To the left of this number are the numbers A31, B31,A30', B30, A29, B29, A28, and B28. "A" stands for the upper or component side of the PWB, while IIBII stands for the other side. The two-digit numbers are the pin numbers. Therefore, A31 means Pl pin 31.

BOO through B07 are mnemonics for 8-bit bus data on lines 0 through 7. The symbols in parentheses are schematic page"numbers and zone location on that page. For example.. (4-02) mean s page 4, zone 02.

2-8 Service And Maintenance. 2302-5012-00

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2-14 Service And Maintenance 2302-5012-00

2.7 ASSEMBLY DIAGRAMS

The following assembly diagrams are for the SLA card and the internal LA-P3 to EP-P3 cable.

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2302-5012-00

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CHAPTERS-

INSTALLATION

3.1 PREPARATION

Chapter 3,

INSTALLATION

Before installing the SLA subsystem, check with your GenRad/DSD service facility to ve~ify that your Slave Emulator is configured with the latest version of:

a... Software.

b. Breakpoint Card

c. Interface Processor Card with correct ROM d. External Probe

2302-5012-00

NOTE

All Slave Emulators shipped from GenRad/DSD after April 30, 1981 are correctly configured to operate with the SLA subsystem.

Installation 3-1

3.2 INSTAlLING THE SLA SUBSYSTEM

a. On the Emulator, set the ON/OFF power switch to OFF and remove the a.c. power cord from the rear panel socket.

b. Remove the rear panel.

c. Refer to Figure 3-1. Insert the LogiC Analyzer card in Position 1 tn., ,the, card ,cage.', ,

d. Connect one end of the short flat cable, 2302-0234-01, to the LogiC Analy,zercard" (P3;); and the other end of the cable to Personality Card P3.

e. On Cable'2302-0225-01, connect the LA-P5 plug tG the Logic Analyzer card.

f. Before replacing the rear panel, make sure that all cable's are properly aligned and pushed all the way onto the: card edge connectors. Replace the rear panel.

g. Replace the a.c. power co,rd.

h. Place the ON/OFF switch on the Emulator to ON and proceed to Chapter 4, Operation.-

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2302-5012-00 Installation 3-3

CHAPTER 4

OPERATION

4 .1 I NTRODUCTI ON

The Slave Logic Analyzer (SLA) option allows the user to view the emulated processor's operation by displaying as many as 64 processor functions in three different formats. The user may record a trace of the target processor's activity, in real time.

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Parameters which the user can control include the following:

Trace qualifier

Trigger event identity Trace contents, relative to trigger event

To identify a specific subset of bus cycles to trace. Breakpoint 3 serves as the trace qua 11 fier'.

Breakpoints 0, 1, and 2 may serve as a Logic Analyzer trigger.

A post-trigger delay count identifies how many qualified bus cycles to trace after the triggering event occurs.

The Logic Analyzer's trace buffer is large enough to trace 256 bus cycles.

These actually represent target processor execution cycles, but the term "bus cycles" is used to suit common usage, whether or not the target processor is connected to a bus in the target system.

Event timing' is, another Logic Analyzer function. The Analyzer has a mode in which it times the interval between Breakpoints 1 and 2, allowing accurate measurement of the elapsed time between two events. Such an interval can be measured in microseconds, hundreds of nanoseconds, or bus cycles.

Software enhancements in the following functions provide support for the SLA:

Window mode command Mode command

Breakpoint command Qualify trace command

4.1.1 COMMAND DEFINITIONS

A definition of each of these commands is given here; a more detailed discussion follows in the section entitled COMMANDS.

WINDOW MODE COMMAND

The Wtndow.Mode command accepts three new modes. Each new mode selects one of the Logic Analyzer display formats listed below for the current window. It also allows the user to edit the set of signals to be shown by the waveform display.

Logic Analyzer trace data may be displayed in the following formats:

Cycle data

Waveform

Execution trace

MODE COMMAND

Each bus cycle is formatted on a single line, with most information shown in hexadecimal.

Individual signals in the trace are drawn as lines in the display, as in a waveform

diagram.

This processor-dependent display shows disassembled instructions combined with the data they manipulate on the target bus.

The Mode command provides options for both breakpoint and Logic Analyzer functions.· These controls are unified in a single command because the Logic Analyzer is actually an extension of breakpoint support.

BREAKPOINT COMMAND

The Breakpoint command itself is essentially unchanged, but the meaning of breakpoints is expanded when the Logic Analyzer is enabled.

QUALIFY TRACE COMMAND

The Qualify Trace command sets parameters to select bus cycles to be traced when the Analyzer is enabled. These parameters are identical to those used with breakpoints, but the meaning of a match condition is lit race this cycle"

rather than "break execution^{ll •} This command also sets the post-trigger delay, whi ch indicates how many bus cycl es to trace a fter the tri ggeri ng event occurs •..

4-2 Operation 2302-5012-00