TYPE 281-IH COMMUNICATION CONTROL AND TYPE 285-IH

HONEYWELL EDP

SUBJECT:

SPECIAL

INSTRUCTIONS:

DATE: April 26, 1966

8857 3466 Printed in U. S. A.

HARDW ARE BULLETIN

SERIES 200

TYPE 281-IH COMMUNICATION CONTROL AND TYPE 285-IH

COMMUNICATION ADAPTER

Equipment Specifications - the Type 281-1H Communication Control and Type 285-1H Com- munication Adapter for use with Bell DAT Aspeed Type 2 Remote Terminals on Voice-Grade Dial Telephone Lines or on Leased Voice-Grade Telephone Lines.

This bulletin updates the Honeywell Customer Information Bulletin Number 200-47, Communi- cation Control Unit Specifications: Models 281- IH and 285-1H, dated February 10, 1965. The text uses the following references: the bulletins Type 281-1 Single-Channel Communication Controls, Order No. 086 and Type 286-1, 2 and -3 Communication Controls, Order No. 160;

also the Honeywell Series 200 Models 200/1200/

2200 Programmers' Reference Manual, File No.

113.0005.0000.00.00.

*

FILE NO:. 112.0005.1100.0-092

':'When ordering this publication please specify Title and Underscored portion of File Number.

Section I Section II

Section III Section

IV

Section V

Section

VI

Copyright 1966 Honeywell Inc.

Electronic Data Processing Division Wellesley Hills, Massachusetts 02181

TABLE OF CONTENTS

General Description . . . • . . . Interface with the Series 200 Central Processor or the Type

286 Multi-Channel Communication Control .••••••••••••••••

A. Type 281-1H/Central Processor Interface •••••••••••

B. Type 285-1H/286 Interface ••••••••••••••••••••••••

Interface with the Common Carrier Line.

Code Characteristics and Remote Terminals •••••••••••••••••••

A. Code Characteristics ••••••••••••

B. Rern.ote TerIllinals . . • . . . . • . • . . .

1. Description . . . • . . . • . . . 2. Co:rnpatihility . . . • . . . . • . . . • . . • • . . . . • • . . . • . Functional Description . . . • . . . • .

A. Type 281-1H . • . . . • • • . . . • . • • • . . • . . 1. General . . • . . .

2. Reception • . . . 3. Type 281-1H Transmission ••••••••••••••••••••••••.

B. Type 285-1H ••••••••••••••••••••••••••••••••

Programming Reference Data ••..•••.•••

A. General Description .••••••••••••

B.

C.

D.

E.

F.

Initial Start . . . . Type 281-1H Stand-By Condition ••

Type 281-1H Reception .•••••••••.

Type 281-1H Transmission •••••

Instruction Formats .••••••••••

1. Type 2SI-IR . • . . . . • . . . • . • . . . . 2. Type 285 -lH . . . • . . . G. Record Marks and Character s in Main Memory •••••••••

1. Record Marks Required by Five-Bit or Six-Bit

Code A pplic ations . . . • . . . a. Single -Character Mode . . • . . . • . . . • . • . . . . b. Block - or Me s sage - Mode ••••••••••••••••••••

2. Record Marks Required by Seven-Bit or Eight-Bit Code Applications . . . • • . . . • . . . a. Single -Character Mode . . . • . . • . • . . . b. Block - or Message Mode ••••••••••••••••••••

3. Character Configuration in Memory •••••••••••••••••

H. Program Timing . • • • . . . • . . • . • • . . . . • . . . . • • . . I. Series 200 and Type 281-1H Interface Signals •••••••••

1. Single -Character Transmi s sion •••••••••••••••••••

a. Device Busy . . . .

b. Interrupt... • •••••••••

c. Input Frame Demand (IFD) •••••••••••••••••••

d. Output Frame Demand (OF D) •••••••••••

e. Timing Error ••••

f. Parity Error ••••

Page 1 2 2 2 2 2 2 3 3 3 5 5 5 5 5

6 ^r-~

6

---

6 6 7 7 7 8 8 8 8 8 8 8 8 8 8 8 10 10 10 10 10 10 11 11 11

Section VI (cont)

Section VII Section VIII Section IX

Figure I.

Figure 2.

Figure 3.

TABLE OF CONTENTS (cont)

Page g. Turn Off Interrupt. • • • • • • • • • • • • • • • • • • • • • • • • • • • • II

h. ResetAllow . . . • . . . 11

2. Single-Character Timing Considerations ••••••••••• II a. Set Allow. . . . • • • . . . . 11

b. Received Data. • • . . . . 11

c. Transmitted D a t a . . . 12

3. Block-Method Transmission... 12

a. Input Frame Demand •••••••••••••••••••••••••• 12 h. Output Frame Demand. • • • • • • • • • • • • • • • • • • • • • • • • 12 c. TiIlling Error. . . . . . . . .. ... ..•. . .•. . . ... 12

Operational Controls. . . • . . . • . . . • . • . . . . . 12

Optional F e a t u r e s . . . 13

Maintenance Facilities. • • • • • • • . • • • • • • . . • • • • • • • • • • • • • • • • • • • • • 13

LIST OF ILLUSTRATIONS

Type 28I-IH and 285-IH Applications •••••••••••••••••••••.•••

Bell System DATAspeed Terminals •••••••••••••••••••••••••••

Character Configuration in Type 281 -1 H Memory ••••••••••••••

iii

I 4 9

EQUIPMENT SPECIFICATIONS FOR THE TYPE 28l-lH COMMUNICATION CON- TROL AND TYPE 285-lH COMMUNICATION ADAPTER

1. GENERAL DESCRIPTION

The Type 28l-lH Single-Channel Communication Control and Type 285-lH Communi- cation Adapter provide the interconnection of a Series 200 central processor with Bell DATAspeed Type 2 high-speed punched paper tape input/output terminals by means of a Bell DATA-PHONE Dataset 202C on switched, voice-grade telephone lines or Bell DATA- PHONE Dataset 202D on leased, point-to-point voice-grade private lines.

As illustrated in Figure I, the Type 28I-IH Communication Control is used to connect one voice-grade telephone line to the Series 200 central processor. The Type 285-IH Communication Adapter is utilized in conjunction with a Type 286 Multi-Channel Communi- cation Control to connect one voice-grade telephone line when a maximum of 63 communi- cation lines are to be connected to a central processor.

SERIES 200

DATASET CENTRAL

202C

TYPE 281-1H PROCESSOR

2020 OR

VOICE-GRADE DIAL EXCHANGE LINE OR

LEASED PRIVATE LINE DATASET

202C TYPE

OR 285-1H

2020

DATASET

TYPE TYPE SERIES 200

202C 285-1H 286 CENTRAL

OR .- _PROCESSOR

2020

DATASET

202C TYPE

OR 285-1H

2020

Figure 1. Type 28I-1H and 285-IH Applications

The communication line is characterized by start-stop, synchronous serial trans- mission of any five-, six-, seven-, or eight-level code in the half-duplex (two-way, non- simultaneous) mode. The maximum line speed is 105 characters per second, 1050 bits per second, or 1050 words per minute.

Equipment at the remote stations consists of a Bell DATAspeed Type 2 in anyone of the three following configurations:

Transmit Only - Paper Tape Reader and Control, Receive Only - Paper Tape Punch and Control,

Composite Terminal - Paper Tape Reader and Punch.

The standard Series 200 logic drawer contains one Type 281-lH Communication Con- trol or eight Type 285-lH Communication Adapters.

II. INTERF ACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI- CHANNEL COMMUNICATION CONTROL

A. Type 281-1H/Central Processor Interface

Standard peripheral interface logic for non-simultaneous input and output con- nects the Type 281-1H to the Series 200 standard peripheral bus.

B. Types 285-1H/286 Interface

Section IV of the Honeywell bulletin Type 286-1, -2 and -3 Multi-Channel Communication Controls describes this interface circuit.

III. INTERF ACE WITH THE COMMON CARRIER LINE

The common carrier line termination is a Bell DATA-PHONE Dataset 202C or 202D.

The datasets convert the voltage-level signals of the communication devices into audio- frequency signals for transmission on the line.

IV. CODE CHARACTERISTICS AND REMOTE TERMINALS A. Code Characteristics

Types 281-1H and 285-1H are capable of operation with five- through eight- level codes. The Bell DATAspeed remote terminal determines the ordering of the particular code. Arrangement of the codes in central processor memory is described in Section VI, G.

All line signals are transmitted or received in a basic ten-bit format. For eight-bit codes, this format provides a start bit, eight data bits and a stop bit, each of approximately 952 microseconds' duration.

In six-bit and seven-bit codes, superfluous bits are transferred as "marking"

pulses (or bits equal to logical "l's") immediately preceding the stop bit.

Six-bit code positions differ sequentially from those of the other codes, as

shown in Figure 3, Section VI, G; the sixth bit precedes bits one, two, three, etc.

The first bit position of the five-bit code is superfluous and is transmitted as a "spacing" pulse (or bit equal to a logical "0"), while superfluous bit positions seven and eight are transmitted as marking bits.

B. Remote Terminals 1. Description

The remote. terminals used with these communication devices are Bell DATAspeed Type 2 Stations equipped with Bell DATA-PHONE Datasets 202C for switched telephone circuit (dial exchange) ser- vice or with Bell DATA-PHONE Datasets 202D for leased point- to-point private line service, as illustrated in Figure 2, page 4.

A DATAspeed Type 2A ("Send") Terminal containing a Teletype Model CX Paper Tape Reader and Control is used for transmission of data from the remote site to the central processor.

A DATAspeed Type 2B ("Receive") Terminal containing a Teletype BRPE Paper Tape Punch and Control is utilized for reception of data from the central processor.

Each of these DATAspeed units is individually housed in a cabinet containing facilities for tape supply and "takeup. II Paper tape input/output equivalents may be adjusted to accommodate five- through eight-level tapes.

DAT Aspeed Type 2A and 2B Stations at the same remote site may share a common dataset; this is the "composite" arrangement.

In this case a manual selector switch adjusts the dataset for trans- mission or reception.

2. Compatibility

The Type 28l-lH Communication Control and Type 285-1H Com- munication Adapter provide the interconnection of a Series 200 central processor with the following arrangements of Bell DATA- speed high-speed paper tape input/output terminals:

a. Basic attended operation of Type 2A ("Send"), Type 2B ("Receive") and Type 2 Composite Terminals over switched telephone circuits or voice-grade, leased, point-to-point private lines;

b. Unattended operation and automatic operation of Type 2B ("Receive") Terminals over switched telephone circuits or voice-grade, leased, point-to-point private lines;

c. Type 2A ("Send") DATAspeed terminals equipped with the five-second delay feature for unattended answer and auto- matic operation over leased, voice-grade, point-to-point private lines;

d. Basic configuration of five-level DATAspeed Type 1 terminals. (Although this equipment is no longer manu- factured by Bell, existing units may still be encountered in the fi eld. )

The Types 281-1H and 285-1H are not compatible with these Bell DATAspeed Type 2 combinations:

a. Dataspeed Type 2A ("Send") Terminals and Type 2 Com- posite Terminals equipped with "Discrete Character

Recognition" for unattended answer and automatic operation;

REMOTE STATION EQUIPMENT

CX READER

CX READER

SEND ONLY

BRPE PUNCH

RECEIVE ONLY

BELL- SUPPLIED SWITCH

L

(

DATASET 202

COMPOSITE TERMINAL

DATASET 202

DATASET 202

BRPE PUNCH

I

DATASET 202C OR 2020

DATASET 202C OR 2020

DATASET 202C OR 2020

COMPUTER LOCATION

TYPE 281-1 H OR 285-1H

TYPE 281-1H OR 285-1H

TYPE 281-1H OR 285-1H

Figure 2. Bell System DATAspeed Terminals

tl

b. DATAspeed Type 2A ("Send"), Type 2B ("Receive") or Type 2 Composite Terminals equipped for the "Reverse Channel Break" operation.

V. FUNCTIONAL DESCRIPTION A. Type 28l-lH

1. General

The Type 281-lH uses standard peripheral interface logic for non-simultaneous input or output. The logic also imple- ments an eight-bit shift register serving as a buffer and serializer in receiving and transmitting; a strobe generator delivering a pulse to sample and shift individual bits; con- trol functions to indicate whether the communication device is in the input or output mode and to signal activity, busy and error conditions to the central processor.

2. Reception

A "space" signal (0) on the communication line enduring more than one-half of a bit time switches the Type 28l-lH to the receive mode.

A bit from the line moves into the buffer shift register, causing the bits already stored to be shifted one position.

When all bits of one character are stored in the shift register, an Input Frame Demand is activated.

In the block mode of transmi s sion, the Type 281 -lH Com- munication Control has continuous access to the central proc- essor by way of its read/write channel (RWC) and the Input Frame Demand is honored during the next memory cycle.

During the single-character method of transmission, two means exist for notifying the central processor of activity requests:

a. The Input Frame Demand is tested by a Peripheral Control and Branch (PCB) instruction frequently enough to ensure the removal of the stored charac- ter from the shift register within the stop-bit time.

b. A program interrupt saves repetitive testing for frame demands, although an Input Frame Demand condition should be checked before the subsequent

"Input" PDT instruction is issued. (This method requires the program interrupt feature, which is standard equipment for all Series 200 central proc- essors except the Type 201; Type 201 must be equipped with Feature 012, as described in the Models 200/1200/2200 Programmers' Reference Manual, pages 1-15 and 1-16.

3. Type 281-lH Transmission

Type 281-lH reception of an "Output" PDT instruction sets the Transmit function. Data arriving thereafter from the central processor over the output bus (six bits in parallel) is stored in the buffer shift register. Two six-bit transfers are required to transfer seven-bit or eight-bit characters.

5

Before the data is sent to the communication line, a start bit is generated. The character is then shifted through the shift register and onto the line. During part of the last-bit and stop-bit time an Output Frame Demand becomes active, as described in Section V, A, 2.

Activity requests to the central processor are handled as described in Section V, A, 2.

B. Type 285-1H

The functional description of the Type 285-1H is similar to that given in the preceding Section V, A, for the Type 28l-1H, with these exceptions: the Type 285-1H mode of data transfer is always single- character and its activity requests are sent to the Type 286 Multi- Channel Communication Control. When a complete character is accumulated, an interrupt is sent to the central processor.

VI. PROGRAMMING REFERENCE DATA

NOTE

The following description is based on the presence of the program interrupt feature, which is standard equipment for all Series

200 central processors, except the Type 201. However, the basic Type 281-1H does not require this feature, since the system can be programmed using PCB instructions to test for "busy," thereby initiating a pro- gram branch whenever a request is made for service. Also, the following description

applies mainly to the Type 281-lH; for Type 285-1H programming see the bulletin Types 286-1, -2 and -3 Multi-Channel Communi- cation Controls.

A. General Description

Though the Type 285-1H - operating in conjunction with the Type 286 Multi-Channel Communication Control - uses only the single-charac- ter method of transmission, the Type 281-1H Communication Control handles data on a single-character

£!

Block transmission with the Type 281-1H permits handling of more data with less manipulation and fewer program interruptions than does single-character transmission. Therefore, block transmission is essential for use with very high-speed lines; also, it is often convenient for use with lower-speed lines, especially when communication is

sharing computer time with other processing.

Whether operating on a single-character or a block basis, the Type 281-lH Communication Control requires that a record mark be set in the data storage area of main memory to terminate data transfer and to release the read/write channel.

B. Initial Start

The Type 281-1H starts when INITIALIZE is pressed on the central processor control panel.

C. Type 281-1H Stand-By Condition

Unless transmitting or receiving, the Type 281-1H is in a neutral state, permitting transmission by the program onto the communi- cation line, but also interrupting the program when a character is received from the line.

If no characters are received from the line during a half-character period, the Type 281-1H interrupts the program with an output re- quest. Thus, if characters are being received at less than two- thirds the line rate, there may be two interrupts per character.

D. Type 281-1H Reception

Reception of the start bit of the first character switches the Type 281-1H to the "busy" state. The first full character received causes a program interrupt if the Type 281-1H has been conditioned - by execution of a "Set Allow" PCB instruction - to allow interrupts.

The Allow Interrupt function remains set until specifically reset by the program or by depression of INITIALIZE. In response to this interrupt, the program issues a Peripheral Data Transfer (PDT) instruction bringing that character and succeeding characters into main memory.

Reception continues until a record mark is encountered in main memory; then the read/write channel is released. If no further characters are received during a half-character period, the Type 281-1H reverts to not busy and sends an interrupt requesting output if Allow is set. This interrupt (identified by a positive response to the PCB "Output Request" query) may be utilized by the programmer to indicate the end of a received message.

When a received message occupies less than the assigned memory area, the record mark terminating data transfer is not encountered.

A timer in the Type 281-1H is therefore activated and - after a specified interval - it releases the assigned read/write channel, sets the Device Error condition, and allows the Type 281-1H to revert to not busy. If Allow is set, an interrupt requesting output then occurs. When the Type 281-1H utilizes a Bell Dataset 202C operating on switched service, a disconnect is also generated by the

"time-out. "

E. Type 281-1H Transmission

Starting in the "initialized" condition (interrupts not allowed), the Type 281-1H may then accept an "Allow Interrupt" PCB instruction.

This is followed by a PDT instruction beginning transmission of data from the central processor. Such data is transferred from the as- signed memory location until a record mark is encountered; then the read/write channel is released. When the read/write channel is

released and the last character goes onto the line, an interrupt occurs.

A second PDT instruction continues data transmission or - if ,such transmission is complete - a "Reset Interrupt" PCB instruction

acknowledges the interrupt and signifies the completion of transmission.

An interrupt can still occur if data is received, or a "Reset Allow"

PCB instruction can be given to the Type 281-1H to prevent further interrupts.

When interrupts are not allowed, testing of Input and Output Frame Demands is required.

F. Instruction Forxnats 1. Type 28l-lH

The forxnats for the Type 28l-lH Peripheral Data Transfer and Peripheral Control and Branch instructions are found in Section II of the bulletin Type 281-1 Single-Channel Coxn- xnunication Controls.

2. Type 28S-lH

The forxnats for the Types 286/28S-lH Peripheral Data Transfer and Peripheral Control and Branch instructions are found in Section VI of the bulletin Type 286 -1, -2 and -3 Multi-Channel Coxnxnunication Controls.

G. Record Marks and Characters in Main Mexnory

Since the Type 28l-lH Coxnxnunication Control and the Type 28S-lH Coxn- xnunication Adapter accept any five-level code and since two xnexnory lo- cations are required to store character codes of xnore than six bits, the record xnark requirexnents for the Type 28l-lH {record xnarks are not required for the Type 285-1H} differ froxn those described in the bulletin Type 281-1 Single-Channel Coxnxnunication Controls. The following de- scription applies specifically to the Type 28l-lH Coxnxnunication Controls.

1. Record Marks Required by Five-Bit or Six-Bit Code Applications a.

b.

Single -Character Mode

In the single-character transxnission xnode, a record xnark is placed in xnexnory location A+l to terxninate a character;

in the single-character reception xnode, a record xnark in location A terxninates the character.

Block - or Message - Mode

In the block transxnission xnode, a record xnark is placed in xnexnory location A+n {where n is the nuxnber of char- acters} to terxninate a xnessage; in the block reception xnode, a record xnark in xnexnory location A+{n-l} terxni- nates the xnessage.

2. Record Marks Required by Seven-Bit or Eight-Bit Code Applications a. Single-Character Mode

In the single-character transxnission xnode, a record xnark is placed in xnexnory location A+2 to terxninate a character; in the single-character reception xnode, a record xnark in lo- cation A+l terxninates the character.

b. Block - or Message - Mode

In the block transxnission xnode, a record xnark is placed in xnexnory location A+2n to terxninate a xnessage; in the block reception xnode, a record xnark in location A+{2n-l) terxninates the xnessage.

3. Character Configuration in Mexnory

Figure 3, page 9, shows the layout of the code bits in xnexnory for five - through eight-level codes (Bl to B8 represent the DATAspeed bits).

"'if. ,

Series 200 RECEIVING Series 200 SENDING

Series 200 RECEIVING Series 200 SENDING

Series 200 RECEIVING Series 200 SENDING

Series 200 RECEIVING

Series 200 SENDING

5-BIT CODE WM

WM 6-BIT CODE

WM

WM 7-BIT CODE

WM

1M WM 8-BIT CODE

WM

1M WM

IBIT POSITION I MEMOR Y LOCATION

A A

+

A A

+

I

I

I

I

I

A

+

B6 B5 B4 B3 B2

B6 B5 B4 B3 B2

1M = Item Mark WM = Word Mark 1M

+

=

Bn = Code Bit

B7 BI

B7 BI

A A+I

A A

+

A A

+

A

+

A A

+

A A

+

A

+

~.<If hardware parity checking is used, then the eighth bit is not sent

from the control unit to the central processor memory. If the hard- ware parity checking is not used, then the eighth bit appears in this

position.

Figure 3. Character Configuration in Type 281-1H Memory 9

H. Program. Tim.ing

In Type 281-IH program.m.ing, the program. m.ust refill or em.pty the shift register during the tim.e interval of a stop bit (952 m.icroseconds).

In the case of the Type 285-IH, the program. has a full character tim.e interval (9.52 m.illiseconds) in which to transfer a character to the central processor or from. it.

If received data is not taken from. the shift register of the Type 281-IH or Type 285-IH within the specified tim.e, data is lost. In this event, the Error function is set in the Type 281-IH, or an error indication is stored in the Type 286.

When the central processor is transm.itting data, the Type 281-IH Com.m.unication Control waits if a new character for transm.ission is not received within the specified tim.e. In the case of the Type 285-IH, however, the Type 286 repeats the last character transm.itted unless a

"Transm.it Last Character" PDT instruction is issued by the program..

During operation of the Type 281-IH in the single-character m.ode, data being sent into m.ain m.em.ory for storage requires a tim.e interval of at least 11 m.em.ory cycles after the instruction is com.pleted. Data being transferred to the Type 281-1H by an "Output" PDT instruction cannot be changed until 14 m.em.ory cycles after extraction of the in- struction.

I. Series 200 and Type 281-IH Interface Signals 1. Single -Character Transm.i s sion

During single-character transm.ission between the Type 281-1H and the Series 200 central processor, the following interface signals occur.

a. Device Busy

This Busy signal indicates that a PDT instruction cannot be accepted by the control unit. Busy is active whenever the read/write channel associated with a PDT instruction addressed to the control unit is busy or when the control unit is receiving or transm.itting data on the line.

b. Interrupt

c.

Activation of INTERRUPT indicates that the control unit is requesting service. INTERRUPT responds to the first

"Set Allow" PCB instruction when the control unit is

"initialized"; thereafter, it responds only when an Input or Output Fram.e Dem.and becom.es active. The com.m.uni- cation control Interrupt signal is reset when a PDT in- struction is sent to the unit, when a "Turn Off Interrupt"

PCB instruction is sent to the unit, or when the system. is

"initialized. "

Input Fram.e Dem.and (IFD)

The IFD signal indicates that the com.m.unication control - having assem.bled a character from. the line and readied it for the com.puter - is requesting a "Receive" PDT instruc- tion. The next PDT instruction to the com.m.unication con- trol resets the IFD signal; if no further PDT instruction is executed, the IFD signal is not reset.

d. Output Frame Demand (OFD)

The OFD signal indicates that the communication control is capable of accepting a "Transmit" PDT instruction.

This signal may be actuated when the communication control is neither transmitting nor receiving, and when the IFD signal is inactive.

The Output Frame Demand, then, becomes active in the transmit mode when the communication control is ready to transmit the next character. In the receive mode, after a one-half character duration of inactivity on the line, and after a PDT instruction has reset the IFD signal, the Output Frame Demand becomes active.

The OFD signal is reset by a "Transmit" or "Receive"

PDT instruction, or when the communication control senses a character on the line.

e. Timing Error

The Timing Error signal indicates the loss of a control- unit data character. In the receive mode, the signal is set when a "Receive" PDT instruction does not respond to an Input Frame Demand before the next character is sensed on the line.

Timing Error is reset when the next PDT instruction is issued to the communication control.

f. Parity Error

The Parity Error signal is associated only with the re- ceive mode. The signal is set - if the communication control is capable of checking parity - by a character demonstrating bad parity when the Input Frame Demand becomes active. Parity Error is reset by the next PDT instruction issued to the communication control.

g. Turn Off Interrupt

The "Turn Off Interrupt" PCB instruction permits the effectiveness of a Resume Normal Mode (RNM) instruc- tion without executing a PDT instruction to the communi- cation control.

h. Re set Allow

The "Reset Allow" PCB instruction prevents future inter- rupts from the communication control. A current inter- rupt is not reset by this PCB instruction; either a "Turn Off Interrupt" PCB instruction or a PDT instruction is needed to render an RNM instruction effective.

2. Single-Character Timing Considerations a. Set Allow

The timing of the interrupt responding to the "Set Allow"

PCB instruction is unpredictable.

b. Received Data

Data offered in response to a "Receive" PDT instruction is entered into main memory within eleven memory cycles after the extraction of the PDT instruction.

11

c. Transmitted Data

Data in main memory which is to be transferred by a

"Transmit" PDT instruction cannot be exchanged until fourteen main memory cycle s are completed after the extraction of that instruction.

NOTE

The read/write channel is busy until all the data is transferred. The control unit is busy two main memory cycles longer than the read/write channel.

3. Block-Method Transmission

During the block method of transmission between the Type 281-1H and the Series 200 central processor, the following interface signals occur.

a. Input Frame Demand

The IFD signal is activated when the communication control has assembled the first block (message) char- acter from the line for transfer to the compute:r. This signal is reset by a PDT instruction and not activated again by a character on the line until the assigned RWC is released. Such a release is accomplished either by the sensing of a record mark in memory or by a line in- activity period of approximately 30 seconds.

b. Output Frame Demand

The OFD signal is activated in the transmit mode when the communication control is ready to transmit a block. In the receive mode, the OFD signal becomes active after a line inactivity period of one-half a character time, pro- viding the RWC has been released. If the RWC has not been released, an inactivity period of 30 seconds elapses before the release is effective and the OFD signal is activated.

c. Timing Error

In the receive mode, Timing Error is set when the com- munication control releases the RWC after the 30-second period of inactivity described in paragraph b, above.

VII. OPERATIONAL CONTROLS

Calls are originated manually, either from the central processor or from the re- mote terminal station. An operator at either end initiates a data connection as a telephone connection, establishing voice communication and agreement on procedure.

Then both operators depress DATA on their Bell DATA-PHONE Datasets 202, plac- ing the line in the data transmission mode.

Optional features include these possibilities:

1. Automatic answer at the remote terminal;

2. Automatic answer at the computer station;

3. Automatic call initiation from the computer by means of a Bell DATA-PHONE Dataset 80lA or 80lC and a Honeywell Type 285-5A Communication Adapter.

vm.

No checking options are available for the Types 281-IH and 285-IH. Bell remote equipment performs neither a parity nor a longitudinal redundancy check on data received from the central processor. Furthermore, Bell remote equip- ment lacks the rereading capability necessary to utilize a parity or long check indication detected by the Series 200 central processor.

IX. MAINTENANCE FACILITIES

The Types 281-IH and 285-IH have no maintenance panel, indicator lights or switches.

13

COMPUTER-GENERATED INDEX APPLICATIONS. 8

CODE APPLICATIONS. 8 285-1H APPLICATIONS.

TYPE 281-1H AND 285-1H APPLICATIONS.

BELL SYSTEM DATASPEED TERMINALS. 4 BLOCK

" - OR MESSAGE - MODE. 8 BLOCK-METHOD TRANSMISSION. 12 BUSY

DEVICE BUSy, 10 CARR I ER LI NE

INTERfACE WITH THE COMMON CARRIER LINE. 2 CENTRAL PROCESSOR

INTERfACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-. 2

CHANNEL COMMUNICATION CONTROL

INTERfACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-. 2

CHARACTER CONfiGURATION

" IN MEMORY. 8

" IN TYPE 281-IH MEMORY. 9 CHARACTERISTICS

CODE CHARACTERISTicS. 2

CODE CHARACTERISTICS AND REHOTE TERMINALS. 2 CHARACTERS

RECORD HARKS AND CHARACTERS IN MAIN MEMORY. 8 CODE

" APPLICATIONS. 8

" CHARACTERISTICS.

CODE CHARACTERISTICS. 2

CODE CHARACTERISTICS AND REMOTE TERMINALS. 2 SIX-BIT CODE.

RECORD MARKS REQUIRED BY FIVE-8IT OR SIX-BIT CODE. 8

COMMON CARRIER LINE

INTERfACE WITH THE COMMON CARRIER LINE. 2 COMMUNICATION CONTROL

INTERFACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-. 2

COMPATIBILITY. 3 CONDITION

TYPE 281-1H STAND-BY CONDITION. 7 C.ONFIGURATION

CHARACTER CONFIGURATION IN MEMO~Y. 8

CHARACTER CONFIGURATION IN TYPE 281-1H MEMORY. q r::ONSIDERATIONS

SINGLE-CHARACTER TIMING CONSIDERATIONS. 11 CONTROL

OPERATIONAL CONTROLS. 12

TYPE 286 MULTI- CHANNEL COMMUNICATION CONTROL.

INTERFACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-. 2

DATA

PROGRAMMING REFERENCE DATA. 6 RECEIVED DATA. 11

TRANSMITTED DATA. 12 DATASPEED TERMINALS DEMAND

BELL SYSTEM DATASPEED TERMINALS. 4 INPUT fRAME DEMAND. 12

I NPUT fRAME DEMAND (J F D). 10 OUTPUT fRAME DEMAND. 12 OUTPUT FRAME DEMAND (OrD). 11 DESCRIPTION. 3

FUNCTIONAL DESCRIPTION. 5 GENERAL DESCRIPTION. I. 6 DEVICE BUSY. 10

EI GHT-B I T

RECORD MARKS REQUIRED By SEVEN-RIT OR EIGHT-BIT. 8 ERROR

PARITY ERROR. II TIMING ERROR. II. 12 FACILITIES

MAINTENANCE FACILITIES. 13 FEATURES

OPTIONAL FEATURES. 13 FIVE-BIT

RECORD MARKS REQUIRED By FIVE-BIT OR SiX-BIT CODE. 8 FORMATS

INSTRUCTION FORMATS. 8 FRAME DEMAND

INPUT FRAME DEMAND. 12 INPUT FRAME DEMAND (IFD). 10 OUTPUT FRAME DEMAND. 12 OUTPUT FRAME DEMAND (OFD). II FUNCTIONAL DESCRIPTION. ~

GENERAL. 5 (cONT. )

GENERAL (cONT.)

• DESCRIPTION. 1. 6

IfD INPUT fRAME DEMAND (If D) • 10 INITIAL START. 6

INPUT FRAME DEMAND. 12

" (lFD). 10 INSTRUCTION fORMATS. 8 INTERFACE

" SIGNALS.

SERIES 200 AND TYPE 281-IH INTERfACE SIGNALS. 10 TYPE 281-1H/CENTRAL PROCESSOR INTERFACE. 2

TYPE 285-1H/286 INTERFACE. 2

• WITH THE COMMON CARRIER LINE. 2

• WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 266 MULTI-. 2

INTERRUPT. 10

TURN OFF INTERRUPT. 11 LINE

COMMON CARRIER LINE.

INTERFACE WITH THE COMMON CARRIER LINE. 2 MAIN MEMORY

RECORD MARKS AND CHARACTERS IN MAIN MEMORY. 8 MAINTENANCE FACILITIES. 13

MARKS

RECORD MARKS AND CHARACTERS IN MAIN MEMORY. 8 RECORD MARKS REQUIRED BY FIVE-BIT OR SIX-BIT CODE. 8 RECORD MARKS REQUIRED BY SEVEN-BIT OR EIGHT-BIT. 8 MEMORY

CHARACTER CONFIGURATION IN MEMORY. 8 MAIN MEMORY.

RECORD MARKS AND CHARACTERS IN MAIN MEMORY. 8 TYPE 281-1H MEMORY.

CHARACTER CONfIGURATION IN TYPE 261-1H HEMORY. q MESSAGE

BLOCK - OR MESSAGE - MODE. 6 MODE

BLOCK - OR MESSAGE - MODE. 8 SINGLE-CHARACTER MODE. 6 MULTI- CHANNEL COMMUNICATION CONTROL Of 0

INTERFACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-. 2

OUTPUT fRAME DEMAND (oFD). 11 OPERATIONAL CONTROLS. 12

OPTIONAL fEATURES. 13 OUTPUT fRAME DEMAND. 12

• (OFD). 11 PARITY ERROR. 11 PROCESSOR

• INTERFACE.

TYPE 261-1H/CENTRAL PROCESSOR INTERFACE. 2 SERIES ZOO CENTRAL PROCESSOR.

INTERfACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-. 2

PROGRAM TIMING. 10

PROGRAMMING REfERENCE DATA. 6 RECEIVED DATA. 11

RECEPTION. 5

TYPE 281-1H RECEPTION. 7 RECORD MARKS

• AND CHARACTERS IN MAIN MEMORY. 8

• REQUIRED By fiVE-BIT OR SIX-BIT CODE. 6

" REQUIRED BY SEVEN-BIT OR EIGHT-BIT. 8 REFERENCE DATA

PROGRAMMING REFERENCE DATA. 6 REMOTE TERMINALS. 3

CODE CHARACTERISTICS AND REMOTE TERMINALS. 2 RESET ALLOW. II

SERIES 200

• AND TYPE 281-1H INTERfACE SIGNALS. 10

" CENTRAL PROCESSOR.

INTERFACE WITM THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-. 2

SET ALLOW. II SEVEN-BIT

RECORD MARKS REQUIRED BY SEVEN-BIT OR EIGHT-BIT. 8 SIGNALS

TYPE 281-1H INTERfACE SIGNALS.

SERIES 200 AND TYPE 281-1H INTERfACE SIGNALS. 10 SINGLE-CHARACTER

" MODE. 8

• TIMING CONSIDERATIONS. 11

• TRANSMISSION. 10 SINGLE-CHARACTER-MODE. 8 SIX-BIT CODE

RECORD MARKS REQUIRED BY FIVE-BIT OR SIX-BIT CODE. 8 STAND-BY CONDITION (CONT.)

COMPUTER-GENERATED INDEX STAND-BY CONDITION

TYPE 281-1H STAND-BY CONDITION, 7 START

INITIAL START. 6

SYSTEM DATASPEED TERMINALS

BELL SYSTEM DATASPEED TERMINALS. 4

TERMINALS

TIMING

BELL SYSTEM DATASPEED TERMINALS, 4

REMOTE TERMINALS. 3

CODE CHARACTERISTICS AND REMOTE TERMINALS. 2

" CONSIDERATIONS.

SINGLE-CHAKACTER TIMING CONSIDERATIONS, 11

" ERROR. 11. 12 PROGRAM TI~ING, 10 TRANSMISSION

BLOC~-METHOD TRANSMISSiON, 12 SINGLE-CHARACTER TRANSMISSION, 10 TYPE 281-1H TRANSMISSION. 5. 7 TRANSMITTED DATA. 12

TURN OFF INTERRUPT, 11 TYPE

" 281-1H/CENTRAL PROCESSOR INTERFACE. 2

" 285-1H. 6. 8

" 285-1H/266 INTERFACE, 2

• 28& MULTI- CHANNEL COMMUNICATION CONTROL,

INTERFACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-. 2

TYPE 281-1H, 5. 8

" ANU 265-1H APPLICATIONS, 1

• INTERFACE SIGNALS.

SERIES 200 AND TYPf 281-1H INTERFACE SIGNALS. 10

" MEMORY.

200

CHARACTER CONFIGURATION IN TYPE 281-1H MEMORY. 9

" RECEPTION. 7

" STAND-BY CONDITION. 7

" TRANSMISSION. 5, 7

" CENTRAL PROCESSOR,

INTERFACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-, 2

SERIES 200 AND TYPE 281-1H INTERFACE SIGNALS. 10 281-1H

" INTERFACE SIGNALS.

SERIES 200 AND TYPE 281-1H INTERFACE SIGNALS. 10

" MEMORY,

CHARACTER CONFIGURATION IN TYPE 281-1H MEMORY. 9

" RECEPTION.

TyPE 281-1H RECEPTION. 7 I

" STAND-By CONDITION.

TYPE 281-1H STAND-BY CONDITION. 7

" TRANSMISSION.

TYPE 281-1H TRANSMISSION. 5, 7 TYPE 281-1H, 5, 8

TYPE 281-1H AND 285-1H APPLICATIONS.

l81-1H/CENTRAL PROCESSOR INTERFACE

TyPE 281-1H/CENTRAL PROCESSOR INTERFACE. 2 285-1H

" APPLICATIONS,

TYPE 281-1H AND 265-1M APPLICATIONS.

TYPE 285-1H, 6, 8 285-1H/286 INTERFACE

TYPE 265-1H/286 INTERFACE, 2 266 MULTI- CHANNEL COMMUNICATION CONTROL

INTERFACE WITH THE SERIES 200 CENTRAL PROCESSOR OR THE TYPE 286 MULTI-, 2

GI C

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HONEYWELL EDP TECHNICAL PUBLICATIONS USERS' REMARKS FORM

DATED: APRIL, 1966 TITLE: SERIES 200 TYPE 281-1H COMMUNI-

CATION CONTROL AND TYPE 285-1H COMMUNICA TION ADAPTER

HARDWARE BULLETIN

FILE NO: 112.0005. 1100.0-092

ERRORS NOTED:

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~ SUGGESTIONS FOR IMPROVEMENT:

o

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FROM: NAME _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DATE

- - - -

COMPANY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TITLE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ADDRESS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

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ATT'N: TECHNICAL COMMUNICATIONS DEPARTMENT

PERMIT NO. 39531 WELLESLEY HILLS

MASS.

._---_ ^... _---

Honey~ell

ELECTRONIC DATA PROCESSING

l