ANALYTICAL ANALYSIS OF PUNCHTHROUGH IN BURRIED CHANNEL P-MOSFETs

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ANALYTICAL ANALYSIS OF PUNCHTHROUGH IN BURRIED CHANNEL P-MOSFETs

T. Skotnicki, G. Merckel, T. Pedron

To cite this version:

T. Skotnicki, G. Merckel, T. Pedron. ANALYTICAL ANALYSIS OF PUNCHTHROUGH IN BUR- RIED CHANNEL P-MOSFETs. Journal de Physique Colloques, 1988, 49 (C4), pp.C4-261-C4-264.

�10.1051/jphyscol:1988454�. �jpa-00227952�

JOURNAL DE PHYSIQUE

Colloque C4, supplement au n"9. Tome 49, septembre 1988 C«-261

ANALYTICAL ANALYSIS OF PUNCHTHROUGH IN BURRIED CHANNEL P-MOSFETs

T. SKOTNICKI, G. MERCKEL and T. PEDRON

CNET-CNS, BP 98, Chemln du Vleux ChSne, F-38243 MeyIan Cedex, France

Résumé - Le phénomène de perçage dans les MOSFET dépiétés à canal P (BC-P-MOSFET) est modélisé de manière analytique par l'utilisation de la transformation tension-dopage (VDT). On montre que le mécanisme du perçage dans les BC-P-MOSFETs est semblable à celui des MOSFET canaux N à conduction à surface, ceci à cause de l'abaissement de barrière provenant de la tension drain (DIBL). Cependant ce phénomène est renforcé, dans les canaux enterrés, par un phénomène d'écran électrostatique de la surface inversée. Ce nouveau modèle de courant de perçage, le premier du genre, traite correctement les effets d'écrantage et donne une grande précision sur une large plage de polarisation et de longeur de canal.

Abstract - The punchthrough phenomenon in burried-channel (BC) P-MOSFETs (depletion mode devices) is analysed analytically using the voltage-doping transformation (VDT) technique. The mechanism of punchthrough in a BC-P-MOSFET is shown to be, similarly as in a surface-channel (SC) N-MOSFET, due to the DIBL effect. However in a BC-MOSFET the DIBL effect is shown to be considerably enhanced by the effect of screening of the surface inversion layer of electrons. The new punchthrough current model, an unique up to date, deals correctly with the screening effect and shows high accuracy within a wide range of biases and channel lengths.

1 - IMTRODUCTION

Punchthrough (pt) leakage currents give a significant rise to a stand-by power dissipation in MOS circuits. Thereby punchthrough becomes one of the severest limitations when shrinking MOSFETs to submicron dimensions. For this reason pt phenomenon has received a great deal of interest in the literature, but this uniquely in relation to surface-channel (SC) N-MOSFETs. To date there is no analytical model published, being able to predict punchthrough currents in burried-channel (BC) P-MOSFETs. Such a situation must become strange when taking into account that in CMOS circuits pt leakages of BC-P-MOSFETs contribute, at least, equally as those in SC-P-MOSFETs to a total stand-by power dissipation. The analysis presented in this paper is based on the voltage-doping transformation (VDT) which has already been successfully applied to the modeling of short-channel threshold voltage [1] and punchthrough [2] in SC-N-MOSFETs. Now an extension of the VDT to the punchthrough in BC-P-(or N-)MOSFETs is proposed.

2 - PHYSICS OF PUNCHTHROUGH IN BC-P-MOSFETs

According to the voltage-doping transformation [1] the 2-dim Poisson equation on the x-axis can be rewritten in the following 1-dim form

324< q

1 „ ^N*^w (1)

"*x I xe x-axis £s

where the x-axis is the loci of the potential minima along the channel and goes perpendicularly to the silicon surface. The effective doping N*(x)=N(x)-esD(x)/q where D(x)£32vP/3y2 |xe x-axisis found analogically as in [2] from an approximation of the lateral potential distribution

*(y)=vf(x=const,y) although now an exponential instead of a parabolic approximation is used. In a SC-N-MOSFET it is reasonable to approximate the lateral potential distribution by a family of parabolas because the potential across the p-n 'source-bulk and drain-bulk junctions varies quadratically with distance. However in a BC-P-MOSFET there is no n-p junction in the way from a source to a drain. Pfiester et.al. found in [3] a 2-dim analytical solution for a potential distribution in a BC-MOSFET. Their solution shows that the lateral potential distribution in a BC-MOSFET depends exponentially and not quadratically on a distance. This finding prompts the lateral potential distribution -d(y) to be approximated by a superposition of a constant and two exponents

y + Lvc y-Lei + lvc

«(y) = a + bexp< ) + cexp( • ) (2)

l0 h

where y=lyc is the distance of the virtual cathode from the source boundary and l0 will serve as a fitting parameter. The coefficients a, b and c are determined by the boundary conditions identical as in [2] and next N*(x) is found to be

2Es Lei

-forosxstc N*(x)gN*^A = N^A V *^{D S}e x p ( ) (3a)

qL^{2 0} 2 l⁰

where

2 , V*DS < [VDS+(V^bi + V^SB - W^{c v c}) ( 2 - d ) - 2¹/ ( V^bi ⁺ V^SB-t^l<(.^cvc)(V^bi ⁺ VsB + V^Ds-Tl<l)^cvc)(1-d)]

d

I (Vw + vS B - n w (2 -d) -2 V(Vbj+vSB - t w ^ x vb i+ vS B + vD S - W c v c)(i -d) ] } i * (3b)

and d-1 - exp( -L^e|Ap). t^c is the thickness of the implanted p-channel and T| is the second fitting parameter.

Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988454

JOURNAL DE PHYSIQUE

Fig. 1

-

Physical mechanism of punchthrough in BC-P-MOSFET. Large negative drain bias increases the effective channel doping N*

pertaining to the gate field. As a result, potential within the channel becomes more negative, thus lowering the barrier height and thereby allowing more current to flow.

Additionally we assume that only the channel doping is modified by the drain field so that for l & x e N*(x)=N~. Expression (3) describes explicitly the voltage-doping transformation. On this base the mechanism of punchthrough in a short- BC-P-MOSFET can be accounted for as follows: the drain bias increases the effective channel doping N*A pertaining to the gate field thereby reducing the penetration of gate and bulk electrical fields into the channel, see Fig. 1. As a result the potential minimum cpmc along the x-axis becomes more negative thus bringing the transistor towards the "on-state" as shown in Fig. Ib). In this way the drain current can become quite significant even for VGS=OV (when the channel should normally be "oif"), which purely means punchthrough. It is to be noted that the above effect is suppressed when Lei+- because then N*A+NA whatever the drain bias, compare eqn (3a).

3

-

POTFNTIAL BARRIER HFIGHT

The potential barrier encountered by holes on their way from a source to a drain equals [cpvc(x) -Vbi-Vs~]. and as cpVc varies with x thus also the barrier differs in height depending on depth x , where qvc(x)eY(x,y=lvc). The lowest barrier occurs at the depth tvc (corresponding lo the location of the virtual cathode) and equals (cpwC-Vb+"~), where cpwC~Y(tvcCvc) is the potential of the virtual cathode. Thus the pt current flows within only a narrow strip at depth tvc instead of a whole channel opening 0 to

k.

Consequently we will focus only on

vCvc

finding.

Equation (1) has a l d i m form typical of the long-channel case so its solution (easily obtainable by double integrating) is well known from the long-channel MOSFETs theory. For this reason, as well as for the lack of space, it will not be quoted here. The solution for ,,,pc

-.-

combined with a pt current expression (analogical to that used in [2]) allows BC-P-MOSFET punchthrough characteristics to be modeled.

The resulting lines N in Fig. 2 show much less punchthrough than the measured ones denoted by M. A physical interpretation of this fact is that the surface inversion layer of electrons, neglected up to now, screens the gate electrical field lines thus giving completely the control over the channel up to the drain, and thereby enhancing punchthrough, compare [4].The simplest way of how to take into account the surface inversion layer screening (SILS) effect is to assume that the barrier heigth becomes independent on the gate bias once a strong inversion is induced, as prompted by the depletion theory. Lines P in Fig. 2 show, however, that such an approach (perfect SlLS effect) must lead to a significant overestimation of punchthrough at large positive VGS biases. From the above it becomes clear that the SlLS effect is essential to punchthrough in BC-P-MOSFETs and thereby necessitates a more careful treatment.

1

SlLS effect:

_{. . . . . . . . . .} 1

perfect neglected

'. \.

' ~ 4 . 3 :

d

^{! :}

'

: : 1.2

gate-source voltage,

(V)

Fig. 2 - Comparison of the model of ideal SlLS effect - lines P, and the neglect of the SlLS effect

-

lines N with measurements

-

lines M.

In order to find the principle of the SlLS effect the Poisson equation (1) must be completed with the term N ~ e x p ( \ Y / u ~ ) corresponding to the concentration of electrons in the inversion layer

a 2 ~ I

- -

-

--[N*(x)+NDexp--] (4)

ax2 ES UT

A strict derivation of c ~ , , ~ would necessitate in double integration of (4) which is analytically impossible. However it is to be noted that c ~ , , ~ can be accurately described by a solution to (1) thus neglecting the inversion layer, if only the the actual depletion depth td, is derived from (4) which deals correctly with the inversion layer. Indeed, knowing the actual

b

value, which accounts correctly for the effect of the surface inversion layer of electrons we may expect good resub for (pcVc from the solution to (1) because whole the region tv&x<(tc+td) is free of electrons and contains only the space-charge of ionized impurities which is just correctly incorporated in (1). k will be shown in the next Section that such an approach ensures very good results even for gate biases much greater than that needed to produce the strong inversion at the surface. On the above basis qmc is formally found by double integrating (1) to be

~ N D ND

'pcvc=

- -

t 2 d ( l + - )

%

N*A

and td by single integrating (4) to be

where

L D E ~ ~ V ~ ~ ~ q(N*A+ND)

q = U ~ l n [ ( )2

-

^{t2dcrit + 1}

1

^(6b)

b x 4

u~

h U T

tdc,ifl corresponds to the onset of the strong inversion at the surface ( qs=O ) and is formally given by (6a) after substituting cps by 0. LD is the Debye's length and reads ( E ~ u ~ R / ( / N ~ ) ~ ~ and V g e f = V ~ s - V s ~ V ~ ~ .

The presented model of nonideal SlLS effect has fairly improved the accuracy. The mean error of the theory is made 9s small as 3f3%

(currents in logarithm are compared). The comparison between measured and modeled BC-P-MOSFET subthreshold characteristics, as illustrated in Fig. 3, demonstrates an excellent agreement for long as well as short channels. The verified range of validity of the model includes gate voltages VGS ranging from threshold voltage, in this technology Vlh?0.5V, up to large positive voltages much higher than those needed to induce a strong inversion at the surface. In the technology used for the veriiication the surface inversion is induced at VG$+0.3V - - whereas the modeled characteristics shown in Fig. 3 extend up to 1.2V still being in very good agreement with measurements.

As far as a drain bias is concerned the range of OV down to -10V is treated very correctly by the model, however under a condition that the corresponding pt current does not exceed the level of about 1pA Otherwise the current becomes space-charge limited which is not taken into account in the analysis. As regards the bulk bias, the range 0 to 5V poses no difficulty to the model as can be obsewed in Fig. 4. It is worth noting that the positive bulk bias suppresses punchthrough in BC-P-MOSFETs analogously as a negative bulk bias suppresses punchthmugh in SC-N-MOSFETs.

.---- modeled

gate-source voltage. IV) gate-source voltage. IV) gate-source voltage. (V)

Fig. 3

-

Measured (solid line) and analyticaly modeled (dashed line) subthreshold characteristics for a series of BC-P-MOSFETs with different electrical channel lengths and parametrically varied drain bias. Bulk bias is kept at OV. The technological parameters read:

N ~ = I . ~ ~ X I O ~ ~ C ~ - ~ , ~ ~ = 3 . 3 x 1 ~ ~ ~ c m - ~ , tC=0.21pm. bx=25qm, ~ p = 4 7 0 c m 2 ~ l s and V F B = - O . ~ ~ ~ V . The used values of the fitting parameters are: q=0.979 and 10=0.304pm.

C4-264 JOURNAL DE PHYSIQUE

- ~ 0 ' 0 ! 6 - i 4 5 " 6 ' . " " I : : . : : : :I .

-1.2 1.2

gate-source voltaae, (V) gate-source voltage. IV) gate-source voltage, IV)

Fig. 4

-

Measured (solid line) and analyticaly modeled (dashed line) subthreshold characteristics for a series of BC-P-MOSFETs with different electrical channel lengths with parametrically varied bulk bias. Drain bias is kept constant. The technological parameters read:

N ~ = 1 . 4 4 ~ 1 0 ~ ~ ~ 1 n - ~ , ~ ~ = 3 . 3 ~ 1 0 ~ ~ c r n - ~ , tc=0.21pm, bX=25qm, pp=470cm2~ls and VFB=-O.~~~V. The used values of the fitting parameters are: q=0.979 and LO=0.304pm.

In conclusion, our analysis for the first time enables the BC-P-MOSFET characteristics to be modeled analytically. The model exhibits an excellent accuracy and a wide range of validity. The mean error of the theory is of 3% (currents in logarithm are compared) whereas the number of code lines needed to implement it on the HP9000 calculator is as small as 30 lines of BASIC code. Thanks to the analytical analysis the punchthrough phenomenon in BC-P-MOSFETs has for the first time be entirely accounted for. The impact of the surface inversion layer screening (SILS) effect on punchthrough is deduced and investigated. As a result the analysis is believed to find applications in design, process optimization and simulation of advanced BC-P-MOSFETs.

REFERENCES

[I] Skotnicki T., Merckel G. and Pedron T., IEEE Electron Device Len., JZIU!. (1988), 109.

(21 Skotnicki T., Merckel G. and Pedron T., IEEE Trans. Electron Dev., to be published in July 1988.

[3] Pfiester J.R., Shot J.D. and Meindl J.D., IEEE Trans. Electron Dev.,

a,

(1985). 333.

[4] Merckel G., Process and Device Modeling for Integrated Circuit Design, edited by F. Van De Wiele et.al., Noordhoff, Leyden, (1977).

667.