Automatic extraction m Automatic extraction m measurement of effect

Automatic extraction m Automatic extraction m measurement of effect

65nm MOSFET tec

Dominique Fleury ^1,2 , Antoine Cros ¹ Franck Perrier ³ Benjamin Franck Perrier , Benjamin

Extensive Electrical Ch

Email : dominiqu Phone : +33 (0

1

STMicroelectronics, 850 rue

2

2

IMEP, Minatec, 3 Parvis Lo

3

NXP Semiconductors, 860 rue

methodology for accurate  methodology for accurate 

tive channel length on  g hnology and below

1 , Krunoslav Romanjek ³ , David Roy ¹ ,  n Dumont ³ Hugues Brut ¹

n Dumont , Hugues Brut

haracterization group

e.fleury@st.com 0) 438 923 314

e Jean Monnet, Crolles France ouis Néel, Grenoble, France

e Jean Monnet, Crolles, France

State‐of‐the‐art Methodology Problematic

Outline

 Problematic of accurate L

 St t f th t

 State‐of‐the‐art

 Methodology for automa

 Methodology for automa

 Test structure design for 

 Results and validation l

 Conclusion

Test structures Results & validation Conclusion

L _eff extraction atic extraction atic extraction

automatic extraction

State‐of‐the‐art Methodology Problematic

Problematic

Outline

 Problematic of accurate L

 St t f th t

 State‐of‐the‐art

 Methodology for automa

 Methodology for automa

 Test structure design for 

 Results and validation l

 Conclusion

Test structures Results & validation Conclusion

L _eff extraction atic extraction atic extraction

automatic extraction

State‐of‐the‐art Methodology Problematic

Problematic

Problematic of accurat

 The mask length (L _mask ): gate defin

 The effective channel length (L _{eff ff} ):

 ΔL = L _mask  − L _eff is the channel len

Nowadays, L _eff hardly  reaches 50% of L

reaches 50% of L _mask

A few nanometer change  can induce bad results 

interpretation !

Test structures Results & validation Conclusion

te L _eff extraction

ition from lithography mask

defined by the inversion layer length ngth reduction

L

lithography mask gate definition

spacer Gate

(poly‐Si)

L

Source SDE L

SDE Drain

gate oxide

L

Channel

State‐of‐the‐art Methodology Problematic State‐of‐the‐art

Problematic

Outline

 Problematic of accurate L

 St t f th t

 State‐of‐the‐art

 Methodology for automa

 Methodology for automa

 Test structure design for 

 Results and validation l

 Conclusion

Test structures Results & validation Conclusion

L _eff extraction atic extraction atic extraction

automatic extraction

State‐of‐the‐art Methodology Problematic State‐of‐the‐art

State-of-the-art

 Most of I _D (V _G )‐based metho the mobility with the length o the mobility with the length o

Mistaken approach due to low  f ld b l d d

field mobility degradation  observed on short devices  ^[1], [2]

 Capacitive method provides L assumption towards the mob assumption towards the mob

[1]K.Romanjek, Solid State Elec., vol. 49, pp. 721‐726, 2005

[2]A.Cros, IEDM’06, San Francisco  USA, dec. 2006, pp. 663‐666 , , pp

Test structures Results & validation Conclusion

ds assume invariance of  of transistors.

of transistors.

L _eff extraction without any  bility

bility.

Solution avoiding a 

 mistaken extraction ^g



State‐of‐the‐art Methodology Problematic State‐of‐the‐art Methodology

Outline

 Problematic of accurate L

 St t f th t

 State‐of‐the‐art

 Methodology for automa

 Methodology for automa

 Test structure design for 

 Results and validation l

 Conclusion

Test structures Results & validation Conclusion

L _eff extraction atic extraction atic extraction

automatic extraction

State‐of‐the‐art Methodology

Problematic Methodology

Methodology: experim

 Capacitance measurements a

 On fully automatic prober with

 On fully automatic prober with 

 Using high precision LCR‐meter

 Using a connection matrix (Agil

 Using a connection matrix (Agil

 Extractions are performed th

d l d f ( l b )

developed software (Scilab™)

−

−

−

Test structures Results & validation Conclusion

mental setup

are performed:

probecard (Accretech UF3000) probecard (Accretech UF3000)  (HP4984 LCR‐meter)

ent 4073B) ent 4073B)

anks to a home‐

))

− Test of several pad combinations

− Large samplings (>20 dice/wafer)

− Batch extractions

State‐of‐the‐art Methodology

Problematic Methodology

Methodology: capaciti

 L _eff is extracted from gate‐to‐

 Proportional to the channel area

 Proportional to the channel area

 max(C

) is set as a reference  point for each curve.

N d b ddi t t

No de‐embedding structure   needed to get rid of 

i i i

parasitic capacitances

Test structures Results & validation Conclusion

ive method

‐channel measurements C _gc (V _G )

10

n ce   (f F) _L

_=10µm

high (gate) 10

ca p acita n

1 µm

max(C

)

low (drain) low

(source) 10

o ‐ chan nel ^0.4 µm

0.2 μm ground

measurement setup

10

1 2 0 6 0 0 0 6 1 2

Ga te ‐ to _0.12µm

0.1µm

‐1.2 ‐0.6 0.0 0.6 1.2

Gate bias V

(V)

State‐of‐the‐art Methodology

Problematic Methodology

Methodology: L _eff extr

 Two ways of extraction are p L _eff ext

Assume ΔL Assume ΔL

constant

L extracted from an axis intersept

Recall : ΔL = L

− L

axis intersept

mask  eff

Test structures Results & validation Conclusion

ractions

ossible:

raction

Extract Extract  ΔL(L _mask ) 

 L extracted from a  cross product

cross product

State‐of‐the‐art Methodology

Problematic Methodology

Methodology: constan

 ΔL is assumed invariant with 

 C = W.C (L _k  − L)

 C _gc  W.C _ox (L _mask   L)

 ΔL is extracted from the linear

 ΔL is extracted from the linear  regression: max(C _gc )=f(L _mask )

L _{eff eff} error strongly depends  g y p on ΔL linearity assumption. 

(lithography and gate etch 

( g p y g

processes optimization)

Test structures Results & validation Conclusion

nt ΔL method

L _mask  , thus:

L_mask=1µm

200

gc)(fF)

10

∆L  82nm

gc)(fF)

10

(fF) 120

160

0.1µm 0

0.07 L _k(µm) 0.13 max(C g

0.1µm 0

0.07 L _k(µm) 0.13 max(C g

0 4

linear regression

max( C

) (

80

L_mask(µm) L_mask(µm)

0.4µm

0.2µm

0

40

Mask length L

(µm)

0.2 0.4 0.6 0.8 1.0

0

State‐of‐the‐art Methodology

Problematic Methodology

Methodology: individu

 Extraction of individual ΔL ^* (f

 ΔL are extracted from a

 ΔL are extracted from a proportionality rule:

 The longest transistor is set as the reference (L  L ) the reference (L _eff  L _mask )

Th ΔL i l h

 The constant ΔL is almost the average value of ΔL(L _mask )

Test structures Results & validation Conclusion

ual ΔL method

for each transistor)

N M O S 100

m ) ^L median values

L

= 0.4µm

90

–L

(n m

0.2µ m

80

L   =   L

0.12µm

constant ΔL from previous method ΔL = 82nm

70

Δ L

0 0.1 0.2 0.3 0.4

0.1µm

L

= 10µm

Mask length L

(µm)

State‐of‐the‐art Methodology

Problematic Methodology

Methodology: individu

 Extraction of individual ΔL ^* (f

 ΔL are extracted from a

 ΔL are extracted from a proportionality rule:

Allows studying ΔL(L y g ( _{mask mask} )  ) behavior

Needs a long transistor as  g reference

Test structures Results & validation Conclusion

ual ΔL method

for each transistor)

N M O S 100

m ) ^L median values

L

= 0.4µm

90

–L

(n m

0.2µ m

80

L   =   L

0.12µm

constant ΔL from previous method ΔL = 82nm

70

Δ L

0 0.1 0.2 0.3 0.4

0.1µm

L

= 10µm

Mask length L

(µm)

State‐of‐the‐art Methodology

Problematic Methodology

Methodology: parasiti

 C _gc measurements are impacte

 From cabling, probes and connection 

 Inherent to the MOSFET architecture

● Overlap capacitance C

(V

‐dependen

f C (V d

● Inner fringe capacitance C

(V

‐depen

● Outer fringe capacitance C

 C

is chosen to have the same value than parasitic capacitances include into max(C ) [3]

include into max(C

) [3].

Test structures Results & validation[3]F.Prégaldiny, Solid State Elec.,Conclusion vol.46, pp. 2191‐2198, 2002

ic capacitance

ed by parasitic capacitance

pads (constant term)

16

Gate Gate

C

(fF) C

nt)

d )

L_mask=65nm 12

14 L_mask=100nm

max(C_gc)

Source Drain Source SDE

Drain

SDE

C C_ofof

CC_ifif C C_ovov

apacitance (

dent)

L_mask 65nm

C_ovvariation C_ifvar.

8.0 1.0

C^min

Channel Channel

-channelca

Parasitic capacitance 4.0

3 5 1 5 0 5 2 5

C_gc 6.0

Gate-to-

-3.5 -1.5 0.5 2.5

Gate bias V_G(V)

State‐of‐the‐art Methodology

Problematic Methodology

Methodology: parasiti

 C _gc measurements are impacte

 From cabling, probes and connection 

 Inherent to the MOSFET architecture

● Overlap capacitance C

(V

‐dependen

f C (V d

● Inner fringe capacitance C

(V

‐depen

● Outer fringe capacitance C

Use of ΔC = max(C _gc ) ‐ C ^min instead of max(C ( _{gc gc} ) )

 cancel parasitic capacitances approximation on C ^min

approximation on C

 error less than 3% on L _eff

Test structures Results & validation[3]F.Prégaldiny, Solid State Elec.,Conclusion vol.46, pp. 2191‐2198, 2002

ic capacitance

ed by parasitic capacitance

pads (constant term)

16

Gate Gate

C

(fF) C

nt)

d )

L_mask=65nm 12

14 L_mask=100nm

max(C_gc)

Source Drain Source SDE

Drain

SDE

C C_ofof

CC_ifif C C_ovov

apacitance (

dent)

L_mask 65nm

C_ovvariation C_ifvar.

8.0 1.0

C^min

Channel Channel

-channelca

Parasitic capacitance 4.0

3 5 1 5 0 5 2 5

C_gc 6.0

Gate-to-

-3.5 -1.5 0.5 2.5

Gate bias V_G(V)

State‐of‐the‐art Methodology

Problematic Methodology

Outline

 Problematic of accurate L

 St t f th t

 State‐of‐the‐art

 Methodology for automa

 Methodology for automa

 Test structure design for 

 Results and validation l

 Conclusion

Test structuresTest structures Results & validation Conclusion

L _eff extraction atic extraction atic extraction

automatic extraction

State‐of‐the‐art Methodology Problematic

Test structures

 Requierements of the measur

 Connection matrix: areas above

 Connection matrix: areas above  noise ratio

 Use of array test structures com wired together (area ≈ 100µm²) wired together (area  100µm )

L

active poly-Si

active

Test structuresTest structures Results & validation Conclusion

rement setup

50µm² to provide enough signal‐to‐

50µm  to provide enough signal to

mposed by N identical transistors 

S h l t b

Such large areas can not be  measured on leaky devices  (T 15Å) !

(T _ox  15Å) !

State‐of‐the‐art Methodology Problematic

Test structures: leaky

T   > 15Å t t t t T _ox  > 15Å

array test structures

A ≈ 100µm²

matrix connection  between LCR‐meter 

and devices 2‐3min/curve

Test structuresTest structures Results & validation Conclusion

devices

T   < 15Å i l t d t t t t

T _ox  < 15Å

isolated test structures

A = LW < 10µm²

direct connection of direct connection of LCR‐meter to devices

20min/curve

20min/curve

State‐of‐the‐art Methodology Problematic

Outline

 Problematic of accurate L

 St t f th t

 State‐of‐the‐art

 Methodology for automa

 Methodology for automa

 Test structure design for 

 Results and validation l

 Conclusion

Test structuresTest structures Results & validationResults & validation Conclusion

L _eff extraction atic extraction atic extraction

automatic extraction

State‐of‐the‐art Methodology Problematic

Results and validation

 Hot Carrier Injection mechani

Bulk current I _b and I _b /I _d ratio I _b  and I _b /I _d ratio 

are increased

 HCI strongly depends on L _eff  :

 When L _eff decreases the lateral  electric field increases (E  1/L _e

 Carriers get high kinetic energy  thanks to the high field  hot ca

Test structures Results & validationResults & validation Conclusion

n: HCI lifetime

ism:

Carrier injection NMOS

e

First ionization

e

h

First ionization Second ionization

h

h

L _ff must be measured L _eff must be measured  with accuracy to identify  the origin of HCI lifetime

eff )

the origin of HCI lifetime  degradation

arriers

State‐of‐the‐art Methodology Problematic

Results and validation

 L _eff  measurements to unders

Thick oxide (T _ox  18.5Å) Å

 array test structures Statistical measurements

20 dies 20 dies

HCI‐lifetime study predicts 4nm‐

shift on L _eff between ‘A’ and ‘B’

SUL T

L _eff measurements give 3.5±1 nm

RE

Test structures Results & validationResults & validation Conclusion

n: HCI lifetime

stand HCI lifetime results:



U nits)

Extrapolated:

 L

 4nm

Measured:

 L

 3.5  1nm 100

Arbitr aty U 

70nm 60nm 10

Lif etime (

Process ‘A’

L

= 50nm 1

0 5 10

Process B’ ‘ 0.1

I

/I

ratio [  10

]   ionisation rate

State‐of‐the‐art Methodology Problematic

Outline

 Problematic of accurate L

 St t f th t

 State‐of‐the‐art

 Methodology for automa

 Methodology for automa

 Test structure design for 

 Results and validation l

 Conclusion

Test structures Results & validationResults & validation ConclusionConclusion

L _eff extraction atic extraction atic extraction

automatic extraction

State‐of‐the‐art Methodology Problematic

Conclusion

 High capabilities of our indus

 Outstanding accuracy (± 1nm)

 Outstanding accuracy (± 1nm)

 Unequal benefits toward HCI lif

 Test structure improvement

 Systematic measurements than Systematic measurements than

 Reduction of the measurement

Ex

− 

− 

Test structures Results & validation ConclusionConclusion

trially‐adapted L _eff extraction

fetime and mobility studies

nks to new array test structures nks to new array test structures

t time (20min  2min)

xpected method improvements:

Extend L _ff meas to in line monitoring

Extend L _eff meas. to in line monitoring

In‐depth study of parasitic capacitances

State‐of‐the‐art Methodology

Problematic Test structures Results & validation Conclusion