BOOK 1985

$10.00

1985

DATA BOOK

Rockwell International

Semiconductor Products Division

©Rockwell International Corporation 1985

Rockwell Semiconductor Products Division is headquartered in Newport Beach, California with Field Sales Offices located throughout the United States, Canada Europe and the Far East. Their listings, plus those of domestic and international representatives and distributors, appear on pages A-1 through A-5 of this publication.

NOTICE

Rockwell International does not assume any liability ariSing out of the application or use of any products, circuit or software described herein, neither does it convey any license under its patent rights nor the patent rights of others. Rockwell International further reserves the right to make changes in any products described herein without notice.

Specifications in the Data Book are subject to change without notice. Preliminary

specifications have tentative parameters which may be subject to change after final

product characterization is completed.

TABLE OF CONTENTS

Rockwell Semiconductor Cross-Reference

Guide ... . Application Note Index. . . 2 Part Number/Data Book Page Index . . . 3 Index by Product Family. . . 5 R68000 Microprocessor and Peripherals. . . . 1-1 Product Family Overview . . . 1-1 R68000 16-Bit Microprocessing Unit (MPU). . . 1-3 R68265 Double-Density Floppy Disk Controller

~~Dq ... 1~

R68465 Double-Density Floppy Disk Controller

(DDFDC) . . . .. 1-60 R68560 Multi-Protocol Communications Controller (MPCq ... 1-86 R68561 Multi-Protocol Communications Controller (MPCC) . . . .. 1-86 R68802 Local Network Controller (LNET) ... 1-118 R68C552 Dual Asynchronous Communications

Interface Adapter (DACIA) . . . .. 1-138 2 8-Bit Microprocessors and Peripherals. . . 2-1 Product Family Overview .. . . 2-2 R6S00 Family Products

R650X Microprocessors (CPU). . . 2-3 R651X Microprocessors (CPU). . . 2-3 R6501Q One-Chip Microprocessor. . . . .. 2-18 R6511 Q One-Chip Microprocessor. . . .. 2-18 R6520 Peripheral Interface Adapter (PIA) . . . .. 2-24 R6522 Versatile Interface Adapter (VIA) . . . .. 2-36 R6530 ROM-RAM-I/O Timer (RRIOT) . . . .. 2-58 R6531 ROM-RAM-I/O-Counter (RRIOC). . . . .. 2-69 R6532 RAM-I/O:rimer (RIOT) . . . .. 2-82 R6541 Q One-Chip Intelligent Peripheral

Controller. . . . .. 2-92 R6500/41 One-Chip Intelligent Peripheral

Controller. . . .. 2-92 R6500/42 One-Chip Intelligent Peripheral

Controller. . . .. 2-92 R6500/43 One-Chip Intelligent Peripheral

Controller. . . .. 2-92 R6545 CRT Controller (CRTq . . . 2-100 R6545-1 CRT Controller (CRTq . . . 2-118 R6549 Color Video Display Generator (CVDG) ... 2-134 R6551 Asynchronous Communications Interface Adapter (ACIA) ... 2-165 R6592 Single Chip Printer Controller ... 2-185 R65560 Multi-Protocol Communications Controller (MPCC) ... 2-196

R65C02 CMOS Microprocessor (CPU). . . . 2-226 R65Cl02 CMOS Microprocessor (CPU) ... 2-226 R65Cl12 CMOS Microprocessor (CPU) ... 2-226 R65C21 CMOS Peripheral Interface Adapter (PIA) .. 2-242 R65C22 Versatile Interface Adapter (VIA). . . . 2-254 R65C24 CMOS Peripheral Interface Adapter Timer (PlAT) ... 2-276 R65C51 CMOS Asynchronous Communications

Interface Adapter (ACIA) . . . .. 2-296 R65C52 CMOS Dual Asynchronous

Communications Interface Adapter (DACIA) ... 2-316 ZBO/BOBO Bus Compatible Products

R6265 Double-Density Floppy Disk Controller

(DDFDC) . . . 2-335 R6765 Double-Density Floppy Disk Controller

(DDFDC) . . . 2-335

3 R6S00/" Microcomputers. . . 3-1 Product Family Overview .... . . 3-2 R65COO/21 Dual CMOS Microcomputer. . . 3-3 R65C29 Dual CMOS Microprocessor. . . 3-3 R65Fll FORTH One-Chip Microcomputer. . . .. 3-36 R65F12 FORTH One-Chip Microcomputer. . .. .. .. 3-36 R65FRX RSC FORTH Development and Kernel

ROMs ... 3-68 R65FKX RSC FORTH Development and Kernel

ROMs ... 3-68 R6501 Q One-Chip Microprocessor. . . .. 3-76 R6500/1 One-Chip Microcomputer ... 3-105 R6500l1E Emulator Device ... 3-136 R6500/1 EB Backpack Emulator . . . 3-143 R6500/1EAB Backpack Emulator ... 3-143 R6500/11 One-Chip Microcomputer ... 3-149 R6500/12 One-Chip Microcomputer ... 3-149 R6500/15 One-Chip Microcomputer ... 3-149 R6500/16 One-Chip Microcomputer ... 3-149 R65/11EB Backpack Emulator ... 3-184 R65/11EAB Backpack Emulator ... 3-184 R6511Q One-Chip Microprocessor ... 3-189 R6500/13 One-Chip Microcomputer ... 3-189 R6500/41 One-Chip Intelligent Peripheral

Controller. . . . .. 3-224 R6500/42 One-Chip Intelligent Peripheral

Controller. . . 3-224 R65/41 EB Backpack Emulator . . . 3-253 R65/41 EAB Backpack Emulator. . . 3-253 R6541Q One-Chip Intelligent Peripheral

Controller. . . .. 3-258 R6500/43 One-Chip Intelligent Peripheral

Controller. . . .. 3-258

TABLE OF CONTENTS (Continued)

4 Memory Products ... 4-1 RDC-1024 Rockwell Design Center 8K132K164K

Product Family Overview ... 4-2 Target RAM Module ... 6-26

Masked ROMs RDC-1030 Multiple Target Development System

R2332A 32K NMOS Static ROM ... 4-3 PROM Programmer Module ... 6-30 R2332B 32K NMOS Static ROM ... 4-3 Software Preparation System

R2364A 64K NMOS Static ROM ... 4-7 SPS-200 Software Preparation System Peripheral R2364B 64K NMOS Static ROM ... 4-11 Connector Module ... 6-36 R23C64 64K CMOS Static ROM ... 4-15

R23128 128K NMOS Static ROM ... 4-19 7 Integral Modems ... 7-1 R23C128 128K CMOS ROM ... 4-23 Product Family Overview ... 7-2 R23256 256K Static ROMs ... 4-27 Product Preview-High Speed Modems

R23257 256K Static ROMs ... 4-27 R96FT/SEC 9600 BPS Fast Train Modem with

UV Erasable PROMs Secondary Channel ... 7-3

R87C64 64K CMOS UV EPROM ... 4-31 R144 Synchronous 14.4 KBPS Modem ... 7-4 R4875 4800/75 BPS Modem ... 7-5 EPROM Pinouts Guide ... 4-37 R208A1B 4800 BPS Modem ... 7-6

High Speed

5 Intelligent Display Controllers ... 5-1 R96FAX 9600 BPS Facsimile Modem ... 7-7 Product Family Overview ... 5-2 R96DP 9600 BPS Data Pump Modem ... 7-20 10937 Alphanumeric Display Controller ... 5-3 R96FT 9600 BPS Fast Train Modem ... 7-34 10957 Alphanumeric Display Controller ... 5-3 V96P/1 9600 BPS Modem ... 7-47 10938 Dot Matrix Display Controller ... 5-11 R48DP 4800 BPS Data Pump Modem ... 7-55 10939 Dot Matrix Display Controller ... 5-11 V27P/1 4800 BPS Modem ... 7-69 10939 Dot Matrix Display Controller ... 5-21 Product Preview-Low to Medium Speed

10942 Dot Matrix Display Controller ... 5-21 Modems

10943 Dot Matrix Display Controller ... 5-21 R1212DS Modem Device Set

10941 Alphanumeric and Bargraph Display (212A Compatible) ...•... 7-76 Controller ... 5-31 R2424DS Modem Device Set ... 7-77

10939 Alphanumeric and Bargraph Display R24DP 2400 BPS Modem

Controller ... 5-31 (201 C Compatible) ... 7-78 10951 Bargraph and Numeric Display Controller ... 5-41 Low to Medium Speed

10955 Segmented Display Controller/Driver ... 5-51 R1212 1200 BPS Full Duplex Modem ... . 7-79 R1212/U 1200 BPS Full Duplex Modem with

6 Microcomputer Development Systems ... 6-1 Internal USART ... 7-94 Product Family Overview ... 6-2 R2424 2400 BPS Full Duplex Modem ... 7-110 RDC-1001/2 Multiple Target Development System R24DC 2400 BPS Direct Connect Modem ... 7-126 (MTDS) ... 6-3 R24LL 2400 BPS Leased Line Modem ... 7-134 RDC-31 01/2 Low Cost Emulator (LCE) ... 6-9 R24 2400 BPS Integral Modem ... 7-143

RDC-3XX Rockwell Design Center R6500/' Modem InterfaCing Products

Personality Set ... 6-14 RDAA Rockwell Data Access Arrangement

RDC-502 Rockwell Design Center R6502-R65C02 Module

...

^7-151

Personality Set ... 6-18

RDC-504 Rockwell Design Center R6502-R65C02 8 T·1 and T·lICEPT Pulse Code Modulation

Personality Set ... 6-18 Protocol Devices ... 8-1 RDC-509 Rockwell Design Center R6502-R65C02 Product Family Overview ... 8-2 Personality Set ... 6-18 R8040 Tri-Port Memory ... 8-3 RDC-2000 R6500 Cross Assembler for Intel R8050 T-1 Serial Transmitter ... 8-9 Development System ... _ ... 6-22 R8060 T-1 Serial Receiver. . . . 8-17 RDC-2005 R6500 Cross Assembler for Intel R8070 T-lICEPT Pulse Code Modulation

Personal Development System ... 6-24 Transceiver . . . 8-23 RDC-1020 Rockwell Design Center 8K132K164K

Target RAM Module ... 6-26

RDC-1022 Rockwell Design Center 8K132K164K Sales Offices, Representatives and

Target RAM Module ... 6-26 Distributors. . . .. A-1

iv

ROCKWELL SEMICONDUCTORS CROSS·REFERENCE GUIDE

SYNERTEK ROCKWELL NCR ROCKWELL

SY6502 R6502 NCR6500/1E R6500/1EC

SY6503 R6503 NCR6500/1 ... · R6500/1

SY6504. .... R6504 NCR6500/11 .. . .... R6500/11

SY6505 R6505 NCR6500/12 .... R6500/12

SY6506 R6506 NCR6500/13 R6500/13

SY6507 R6507 NCR6500/11 E R65110

SY6512 .. R6512 NCR6500/41 R6500/41

SY6513 R6513 NCR6500/42 R6500/42

SY6514 R6514 NCR6500/43 . · R6500/43

SY6515 R6515 NCR6500/41E R6541 0

SY6520 R6520 NCR65C02 . R65C02

SY6522 R6522

SY6530. .. .. R6530 GTE ROCKWELL

SY6532 · R6532

G65SC02. R65C02

SY6545-1 R6545-1

G65SC21 ... R65C21

SY6551 · R6551

G6SSC51. .. R6SC51

INTEL ROCKWELL R23C64

8272 R6765 RICOH ROCKWELL

MOTOROLA ROCKWELL RD5H64 R87C64

MC6820 R6520

(1)MC6821 · R6520 AMI ROCKWELL

(2)MC6845 R6545-1 S2333 R2332

(2)MC6845M R6545-1 S2364 .. .. R2364

MC68000 R68000 S23128

...

R23128

(1) except apphcatlOn of (2) TIL loads S6551 .. R6551

(2) ask customer for evaluatIon

MOS TECHNOLOGY ROCKWELL

FUJITSU ROCKWELL

MPS6502. R6502

MBM27<364 R87C64

MPS6503 R6503

MPS6504 R6504

MPS6505 R6505 AMD ROCKWELL

MPS6506 R6506

AM2764. · R87C64

MPS6507 R6507

MPS6512 R6512

MPS6513 R6513

RCA ROCKWELL

MPS6514 R6514

MPS6515 · R6515 CDP65564

...

.. R23C64

MPS6520 R6520

MPS6522 R6522

MPS6530 R6530 NEC ROCKWELL

MPS6532 R6532 765 R6765

APPLICATION NOTE INDEX

Order No. Title Order No. Title

R6500 Mlcroproceaeora and Peripherals Microcomputer Development Systems

223 R6S02lR6532 Timer Interrupt Precautions 224 System 65 to AI~ 65 Microcomputer Interface 296 R6502 Interfacing Higher Speed R6502's to Lower 240 User 65 Emulation with less than 512 Byles of RAM

Speed I/O & Memory

246 System 65 Bus Interface 256 Printer Control with R6522 VIA (Versatile Interface

Adapter) 2129 OS3.1 Monitor ROM & Macro Assembler/linking Loader

226 R6531 ROM-RAM-I/O Counter (RRIOC)

2158 CMOS User 65 System 65 Development System 227 R6531 Address Lines for Contiguous ROM

2166 R6500 Software Preparation System Development 225 Generating Non·Standard Baud Rates with the R6551

Configurations ACIA (Asynchronous Communication Interface Adapter)

208 Low-Cost Crystal Oscillator for Clock Input Frequency Integral Modema Generator

231 Interfacing R6S00 Microprocessors to a FDC (Floppy 607 R24 Modem Options

Disk Controller) 608 Quality of Received Data for R24 Modem

276 Crystal Considerations for R6500 Family Devices 619 R24DC Interface to EIA RS·232·C 287 USing R65XX Family Peripheral Devices with Z80 CPU

622 R24DC Interface to U.S. SWitched Telephone Network R6500/' Microcomputers

624 R24DC Modem Options

239 Interfacing R6S00/1 to SIDC (Serial Input Display 634 R24LL and R24DC Modem Control Signal To LED

Controller) Interface

237 R6500/1 Microcomputer·Based Printer Controller 632 R24LL Modem Interface to EIA RS-232-C 258 A Logical Tester for R6500/1 One-Chip Microcomputer

635 R24LL Modem Options 2163 A Dot Matrix Controller System Design Using the

10938/10939 Display Drivers and R6500/1 EB 617 4800/9600 BPS Modem Interfacing

Microcomputer 637 Picture Plotter Data Transmission System

2162 A Low Cost Development Module for the 654 R96FAX Modem RAM Write Control R65Fl1/R65FI2 FORTH Microcomputer

656 R96FAX Modem Recommended Receive Sequence for 2178 Design Considerations for Conversion to Rockwell

Group 2 Facsimile R6500/11 and R6501Q from Intel 805118031

2182 R6500/41 Based Stepper Motor Controller 656 R96FAX Modem Scrambled Ones Work-Around for R530D-18 and R530D-19

Intelligent Display Controllers

657 R96DP and R48DP Modems RAM Write Control 2163 A Dot Matrix Controller System Design Using the 658 High Speed Modems Filter Characteristics

10938/10939 Display Drivers and R6500/1EB Microcomputer

2175 Display Controller Designer Notes

2

PART NO.lDATA BOOK PAGE INDEX

10937 Alphanumeric Display Controller ... 5-3 R6502 Microprocessor (CPU) ... 2-3 10938 Dot Matrix Display Controller ... 5-11 R6503 Microprocessor (CPU) ... 2-3 10939 Display Controller ... 5-11, 5-21,5-31 R6504 Microprocessor (CPU) ... 2-3 10941 Alphanumeric and Bargraph Display R6505 Microprocessor (CPU) ... 2-3 Controller ... 5-31 R6506 Microprocessor (CPU) ... 2-3 10942 Dot Matrix Display Controller ... 5-21 R6507 Microprocessor (CPU) ... 2-3 10943 Dot Matrix Display Controller ... 5-21 R6511Q One-Chip Microprocessor ... 2-18, 3-189 10951 Bargraph and Numeric Display Controller ... 5-41 R651X Microprocessors (CPU) ... 2-3 10955 Segmented Display Controller/Driver ... 5-51 R6512 Microprocessor (CPU) ... 2-3 10957 Alphanumeric Display Controller ... 5-3 R6513 Microprocessor (CPU) ... 2-3 R1212 1200 BPS Full Duplex Modem ... 7-79 R6514 Microprocessor (CPU) ... 2-3 R1212DS Modem Device Set (212A Compatible) ... 7-76 R6515 Microprocessor (CPU) ... 2-3 R1212/U 1200 BPS Full Duplex Modem with R6520 Peripheral Interface Adapter (PIA) ... 2-24 Internal USART ... 7-94 R6522 Versatile Interface Adapter (VIA) ... 2-36 R144 Synchronous 14.4 KBPS Modem ... 7-4 R6530 ROM-RAM-I/O Timer (RRIOT) ... 2-58 R208A/B 4800 BPS Modem ... 7-6 R6531 ROM-RAM-I/O-Counter (RRIOC) ... 2-69 R23128 128K NMOS Static ROM ... 4-19 R6532 RAM-I/O:rimer (RIOT) ... 2-82 R23256 256K Static ROMs ... 4-27 R6541Q One-Chip Intelligent Peripheral

R23257 256K Static ROMs ... 4-27 Controller ... 2-92, 3-258 R2332A 32K NMOS Static ROM ... 4-3 R6545 CRT Controller (CRTC) ... 2-100 R2332B 32K NMOS Static ROM ... 4-3 R6545-1 CRT Controller (CRTC) ... 2-118 R2364A 64K NMOS Static ROM ... 4-7 R6549 Color Video Display Generator

R2364B 64K NMOS Static ROM ... 4-11 (CVDG) ... 2-134 R23C128 128K CMOS ROM ... 4-23 R6551 Asynchronous Communications Interface

R23C64 64K CMOS Static ROM ... 4-15 Adapter (ACIA) ... 2-165 R24 2400 BPS Integral Modem ... 7-143 R65560 Multi-Protocol Communications Controller

R24DC 2400 BPS Direct Connect Modem ... 7-126 (MPCC) ... 2-196 R24DP 2400 BPS Modem (201 C Compatible) ... 7-78 R6592 Single Chip Printer Controller ... 2-185 R24LL 2400 BPS Leased Line Modem ... 7-134 R65COO/21 Dual CMOS Microcomputer ... 3-3 R2424 2400 BPS Full Duplex Modem ... 7-110 R65C02 CMOS Microprocessor (CPU) ... 2-226 R2424DS Modem Device Set ... 7-77 R65Cl02 CMOS Microprocessor (CPU) ... 2-226 R4875 4800/75 BPS Modem ... 7-5 R65C112 CMOS Microprocessor (CPU) ... 2-226 R48DP 4800 BPS Data Pump Modem ... 7-55 R65C21 CMOS Peripheral Interface Adapter

R6265 Double-Density Floppy Disk Controller (PIA) ... 2-242 (DDFDC) ... 2-335 R65C22 Versatile Interface Adapter (VIA) ... 2-254 R6500/1 One-Chip Microcomputer ... 3-105 R65C24 CMOS Peripheral Interface Adapter

R6500/11 One-Chip Microcomputer. ... 3-149 Timer (PlAT) ... 2-276 R6500/12 One-Chip Microcomputer. ... 3-149 R65C29 Dual CMOS Microprocessor ... 3-3 R6500/13 One-Chip Microcomputer. ... 3-189 R65C51 CMOS Asynchronous Communications

R6500/15 One-Chip Microcomputer. ... 3-149 Interface Adapter (ACIA) ... 2-296 R6500/16 One-Chip Microcomputer. ... 3-149 R65C52 CMOS Dual Asynchronous Communications R6500/1E Emulator Device ... 3-136 Interface Adapter (DACIA) ... 2-316 R6500/1EAB Backpack Emulator ... 3-143 R65Fl1 FORTH One-Chip Microcomputer ... 3-36 R6500/1EB Backpack Emulator ... 3-143 R65F12 FORTH One-Chip Microcomputer ... 3-36 R6500/41 One-Chip Intelligent Peripheral R65FKX RSC FORTH Development and

Controller ... 3-224 Kernel ROMs ... 3-68 R6500/42 One-Chip Intelligent Peripheral R65FRX RSC FORTH Development and

Controller ... 2-92, 3-224 Kernel ROMs ... 3-68 R6500/43 One-Chip Intelligent Peripheral R65/11EAB Backpack Emulator ... 3-184 Controller ... 2-92, 3-258 R65/11 EB Backpack Emulator ... 3-184 R6501Q One-Chip Microprocessor ... , . . . . .. . 2-18,3-76 R65/41EAB Backpack Emulator ... " " , '" , . " " " . " " " " 3-253 R650X Microprocessors (CPU) ... 2-3 R65/41EB Backpack Emulator. " ... 3-253

PART NO./DATA BOOK PAGE INDEX (Continued)

R6765 Double·Density Floppy Disk Controller ROC·l020 Rockwell Design Center 8K/32K/64K Target (DDFDC) ... 2·335 RAM Module ... 6·26 R68000 16-Bit Microprocessing Unit (MPU) ... 1-3 ROC·l022 Rockwell Design Center 8K/32K/64K Target

R68265 Double·Density Floppy Disk RAM Module ...•... 6·26

Controller (DDFDC) ... , ...•.. 1·60 ROC-l024 Rockwell Design Center 8K/32K/64K Target

R68465 Double·Density Floppy Disk RAM Module ...•.... 6-26

Controller (DDFDC) ... 1·60 ROC-l030 Multiple Target Development System PROM R68560 Multi·Protocol Communications Controller Programmer Module ... ' ... '. 6·30

(MPCC) ... : ... 1-86 ROC-2000 R6500 Cross Assembler for Intel

R6856l Multi·Protocol Communications Controller Development System ... 6·22 (MPCC) ... 1·86 ROC·2005 R6500 Cross Assembler for Intel Personal R68802 Local Network Controller (LNET) ... '. " ... 1·118 Development System ... 6-24 R68C552 Dual Asynchronous Communications Interlace ROC-310l/2 Low Cost Emulator (LCE) ... 6·9

Adapter (DACIA) ... 1·138 ROC-3XX Rockwell Design Center R6500/'

R8040 Tri·Port Memory ... 8·3 Personality Set ... : ... 6·14 R6050 T-l Serial Transmitter ... , ... , . , ... 8·9 ROC-502 Rockwell Design Center R6502·R65C02

R8060 T-l Serial Receiver ... 8·17 Personality Set ... 6·18 R8070 T-lICEPT Pulse Code Modulation Transceiver .... 8·23 ROC·504 Rockwell Design Center R6502·R65C02

R87C64 64K CMOS UV EPROM ... 4·31 Personality Set ... 6·18 R960P 9600 BPS Data Pump Modem ... 7·20 ROC-509 Rockwell Design Center R6502·R65C02

R96FAX 9600 BPS Facsimile Modem ...• 7·7 Personality Set ...•... ' ... 6·18 R96FT 9600 BPS Fast Train Modem . .' ... .' ... 7·34 SPS·200 Software Preparation System Peripheral

R96FT/SEC 9600 BPS Fast Train Modem with Connector Module ... : ... 6·36 Secondary Channel. ... 7·3 V27P/l 4800 BPS Modem ... ' ... 7·69 RDAA Rockwell Data Access Arrangement Module ... 7·151 V96P/l 9600 BPS Modem .. ,' ... ' ..•... 7-47 ROC·l001/2 Multiple Target Development

System (MTDS) ... 6·3

4

PRODUCT INDEX

R68000 Microprocessor and Peripherals

8-Bit Microprocessors and Peripherals

R6500/* Microcomputers

~M_e_m_O_r_y_p_r_O_d_u_ct_s ________________________________ ~

Intelligent Display Controllers

Microcomputer Development Systems

Integral Modems

T-1 and T-1/CEPT Pulse Code Modulation Protocol Devices

SECTION 1 II

R68000 MICROPROCESSOR AND PERIPHERALS

Page

Product Family Overview. . . 1-2 R68000 16-Bit Microprocessing Unit (MPU) ... 1-3 R68265, R68465 Double-Density Floppy Disk Controller (DDFDC) . . . .. 1-60 R68560 and R68561 Multi-Protocol Communications Controller (MPCC) ... 1-86 R68802 Local Network Controller (LNET) . . . 1-118 R68C552 Dual Asynchronous Communications Interface Adapter (DACIA) ... 1-138

R68000 MICROPROCESSOR AND PERIPHERAL FAMILY 16-bit Speed and Data Capacity, Peripherals to Build Efficient

Systems

Rockwell peripherals give a designer everything the 68000 family promises. They allow you to design' functional systems utilizing all the speed and data handling potential of the 16-bit 68000 family.

First of these are the Rockwell designed 16-bit peripherals-multi-protocol communications controller, double density floppy disk controller, local area network controller-each a significant "first" that eliminates the

"glue parts" between a CPU and peripherals.

Not to be ignored, however, is the very wide and complete family of 8-bit devices-processors, peripherals, memory, single-chip microcomputers-compatible with the R68000 family. All of the R6500 family of devices described in this Data Book are directly compatible with the R68000 bus. They often provide efficient, economical and very flexible ways of implementing system designs.

The Rockwell R68000 16-bit microprocessor (MPU) operates at clock speeds of 4, 6, 8, 10 or 12.5 MHz to match essentially any application.

The R68561 multi-protocol communications controller (MPCC) is the highest throughput communications device ever made commercially available. It operates up to

4 Mbits/sec and supports all major communication protocols.

It's available to work with either 16-bit or 8-bit busses and can be adapted to function with essentially any of today's more common busses.

The R68465 double density floppy disk controller (DDFDC) is an intelligent device thaI can run up to four disk drives without the many support devices previously required.

The R68802' provides a flexible local area network (LNET) controller for the R68000. It supports both the IEEE 802.3 and Ethernet' standards based on the proven CSMA/CD technique together with network statistics.

The R68C552 provides an easily implemented, program controlled interface between 16-bit microprocessor-based systems and serial communication data sets and modems.

This device is the first CMOS.ACIA in the industry.

Rockwell lets you build efficient and economical 16-bit systems through families of 16-bit and 8-bit peripherals, all compatible. No other supplier offers you more.

• R68802 is a trademark of the Rockwell International Corp .

• Ethernet is a trademark of the Xerox Corp.

R68000/R6500 Peripheral Migration

1-2

R68000

R68000

'1' ^Rockwell 16-BIT MICROPROCESSING UNIT (MPU)

PRELIMINARY

DESCRIPTION

The R68000 microprocessor is designed for high performance where operational computation and versatility is required. The R68000 provides powerful mass-memory handling capability and architectural features designed to fit the broad range of 16-bit needs. The Rockwell family of 16-bit products also includes a wide range of peripherals that will allow complete system design and manufacture.

31 16 15 87 0

DO 01 02 03 EIGHT 04 DATA 05 REGISTERS 06

07

3' 16 15 0

f- ^I

-

f- ^I I

-

f-

-

I ^I I

- ^-

AO A1 A2 SEVEN A3 ADDRESS A4 REGISTERS

-

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-

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^AS A6

--USER-STACKPrnNTER-(USP)-- A7 TWO STACK

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POINTERS

31

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15 87

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R6BOOO Registers

Document No. 68650N01

PROGRAM COUNTER STATUS REGISTER

The R68000 offers seventeen 32-bit registers in addition to the 32-bit program counter and a 16-bit status register. The first eight registers (DO-D7) are used as data registers for by1e (B-bit), word (16-bit), and long word (32-bit) data operations. The second set of seven registers (AO-A6) and the system stack pOinter may be used as software stack pointers and base address registers. In addition, these registers may be used for word and long word address operations. All 17 registers may be used as Index registers.

FEATURES

• 16M byte (8M word) Linear Addessing Range

• 14 Operand Addressing Modes

• 56 Powerful Instruction Types

• Instruction Set Supports Structured High-Level Languages

• Pipelining Instruction Execution

• 32-Bit Program Counter

• 16-Bit Data Bus

• 23-Line Address Bus

• 32-Bit Data and Address Registers Including:

- Eight General Purpose Data Registers - Seven Address Registers

- Two Stack Pointers (User, Supervisory)

• All 17 Registers Can Be Index Registers

• Memory Mapped Peripheral Devices

• Vector Generated Exception Processing

• Seven Unique Autovectors for Interrupt Service Routines

• Trace Mode for Software Debugging

• Operations Occur on Five Main Data Types -Bit

-BCD - Byte -Word - Long Word

• Asynchronous and Synchronous Peripheral Interface Capability

• Many Peripheral Chips Available

- R68560 Multi-Protocol Communications Controller - R68465 Double Density Floppy Disk Controller - R68802 Local Network Controller

• Up to 12.5 MHz Input Clock

• + 5 VDC Power Supply

Product Description Order No. 700 Rev. 5, October 1984

II

R68000

04 64 05

03 2 63 06

02 3 62 07

01 4 61 08

DO 5 60 09

AS 6 59 010

UOS 7 58 011

lOS 8 57 012

R/W 9 56 013

OTACK 10 55 014

BG 11 54 015

BGACK 12 53 GNO

BR 13 52 A23

VCC 14 51 A22

ClK 15 50 A21

GNO 16 49 VCC

HALT 17 48 A20

RESET 18 47 A19

VMA 19 46 A18

E 20 45 A17

VPA 21 44 A16

BERR 22 43 A15

IPl2 23 42 A14

IPll 24 41 A13

IPlO 25 40 A12

FC2 26 39 All

FCl 27 38 Al0

FCO 28 37 A9

Al 29 36 A8

A2 30 35 A7

A3 31 34 A6

A4 32 33 AS

R68000C/P Pin Assignments-64-Pin DIP

ORDERING INFORMATION

Part Package Frequency Temperature

Number Type (MHz) Range (OC)

R68000C4 Ceramic DIP 4

o

to + 70 R68000C6 Ceramic DIP 6

o

to + 70 R68000C8 Ceramic DIP 8

o

^{to + 70}

R68000C10 Ceramic DIP 10

o

to +70 R68000C12 Ceramic DIP 12,5

o

to + 70

R68000J6 Plastic CC 6

o

to +55

R68000J8 Plastic CC 8

o

to +55

R68000Jl0 Plastic CC 10

o

to +55 R68000J12 Plastic CC 12,5

o

to +55

R68000P6 Plastic DIP 6

o

to +55

R68000P8 Plastic DIP 8

o

to +55

R68000P10 Plastic DIP 10

o

to +55 R68000P12 Plastic DIP 12,5

o

to +55 R68000Q6 Plastic QUIP 6

o

to +55 R68000Q8 Plastic QUIP 8

o

to +55 R68000Q10 Plastic QUIP 10

o

to +55 R68000Q12 Plastic QUIP 12,5

o

to +55

1-4

16-Bit MPU

04

1.

⁶⁴

03 2 63

02 3 62

01 4 61

DO 5 60

AS 6 59

UOS 7 58

lOS' 8 57

R/W 9 56

OTACK 10 55

BG 11 54

BGACK 12 53

BR 13 52

VCC 14 51

ClK 15 50

GNO 16 49

HALT 17 48

RESET 18 47

VMA 19 46

E 20 45

VPA 21 44

BERR 22 43

IPl2 23 42

IPll 24 41

IPlO 25 40

FC2 26 39

FC1 27 38

FCO 28 37

Al 29 36

A2 30 35

A3 31 34

A4 32 33

R68000Q Pin Assignments-64-Pin QUIP

OTACK BG BGACK BR VCC ClK GNO GNO

~ HALT R~

VMA ---.E VPA BERR IPl2 IPl1

I~I"'I'"

_Q QI(I)o,.... C'\I (') ~ It) CD,.... ^CQ 0),....,....,....

C>~'"

~~~<QQQQQQQQQQQQQ

PIN 1

o

INDICATOR

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

R68000J Pin Assignments-68-Pin PCC 05 06 07 08 09 010 011 012 013 014 015 GNO A23 A22 A21 VCC A20 A19 AlB A17 A16 A15 A14 A13 A12 A11 A10 A9 AS A7 A6 A5

013 014 015 GNO GNO A23 A22 A21 VCC A20 A19 A18 A17 A16 A15 A14 A13

R68000

SIGNAL DESCRIPTION

The following paragraphs briefly describe the input and output signals and also reference (if applicable) other paragraphs that contain more detail about the function being performed. Bus operation during the various machine cycles and operations is also discussed. The input and output signals can be functionally organized into the groups shown in Figure 1.

Note

The terms assertion and negation are used to avoid con- fusion when dealing with a mixture of "active-low" and

"active-high" signals. The terms assert, or assertion, indi- cates that a signal is active, or true, independent of whether that voltage is low or high. The term negate, or negation, indicates that a signal is inactive or false.

ADDRESS BUS (A1 THROUGH A23). This 23-bit, unidirectional, three-state bus can address eight megawords of data. It pro- vides the address for bus operation during all cycles except inter- rupt cycles. During interrupt cycles, address lines A 1, A2, and A3 encode the interrupt level to be serviced while address lines A4 through A23 are all set high.

DATA BUS (DO THROUGH 015). This 16-bit, bidirectional, three-state bus is the general purpose data path. It transfers and accepts data in either word or byte length. During an interrupt acknowledge cycle, an external device supplies the vector number on data lines DO-D7.

ASYNCHRONOUS BUS CONTROL. Asynchronous data transfers are handled using the following control signals: address strobe, read/write, upper and lower data strobes, and data transfer acknowlege. These signals are explained in the follow- ing paragraphs.

PRO- { CESSOR STATUS R6500 { PERIPH- ERAL CONTROL

SYSTEM { CONTROL

VCd2) GNO(2) CLK

FCO

FC1 R68000

FC2 MPU

E VMA VPA BERR RESET

HALT

ADDRESS BUS) A1-A23 A>AT~

BUS) VAS ...

00-015

RIW UOS LOS

DTAcK

BR BG BGACK IPLO IPL1 IPL2

}

ASYNCHRO- NOUS BUS CONTROL

} BUS ARBITRA- TION CONTROL

} INTERRUPT CONTROL

Figure 1. Input and Output Signals

16-Bit MPU

Address Strobe (AS). The AS output indicates that there is a valid address on the address bus.

ReadlWrlte (RIW). The Rm output defines the data bus transfer as a read or write cycle. The

RiW

signal also works in conjunction with the upper and lower data strobes as explained in the follow- ing paragraph.

Upper and Lower Data Strobes (UDS, LOS). The UDS and LDS outputs control the data on the data bus, as shown in Table 1.

When the Rm line is high, the processor reads from the data bus as indicated. When the

RiW

line is low, the processor writes to the data bus as shown.

Data Transfer Acknowledge (DTACK). The DTACK input indi- cates that the data transfer is completed. When the processor recognizes DTACK during a read cycle, data is latched and the bus cycle terminated. When DTACK is recognized during a write cycle, the bus cycle terminates. Refer to ASYNCHRONOUS VERSUS SYNCHRONOUS OPERATION.

BUS ARBITRATION CONTROL. These three signals form a bus arbitration circuit to determine which device will be the bus master device.

Bus Request (BR). The BR input indicates to the processor that some other device desires to become the bus master. This input can be externally ORed with all other devices that could be bus masters.

Bus Grant (BG). The BG output indicates to all other potential bus master devices that the processor will release bus control at the end of the current bus cycle.

Bus Grant Acknowledge (BGACK). The BGACK input indicates that some other device has become the bus master. This signal cannot be asserted until the following four conditions are met:

1. a bus grant (BG) has been received,

2. address strobe (AS) is inactive which indicates that the processor is not using the bus

Table 1. Data Strobe Control of Data Bus

UOS LOS R/W 08-015 00-07

High High - No valid data No valid data Low Low High Valid data bits Valid data bits

8-15 0·7

High Low High No valid data Valid data bits 0-7

Low High High Valid data bits

No valid data

~ 8-15

Low Low Low Valid data bits Valid data bits

8-15 0-7

High Low Low Valid data bits Valid data bits

0-7" 0-7

Valid data bits Valid data bits

Low High Low 8-15 8-15"

"These conditions are a result of current Implementation and may not appear on future deVices.

R68000

3. data transfer acknowledge (DTACK) is inactive which indicates that neither memory nor peripherals are using the bus, and

4. bus grant acknowledge (BGACK) is inactive which indicates that no other device is still claiming bus mastership.

INTERRUPT CONTROL (IPLO, IPL 1, IPL2). These input pins indicate the encoded priority level of the device requesting an ihterrupt. Level seven is the highest priority while level zero indi- cates that no interrupts are requested. Level seven cannot be masked. IPLO is the least significant bit while IPL2 is the most significant bit. To insure an interrupt is recognized, the inter- rupt control lines (IPLX) must remain stable until the processor signals interrupt acknowledge (FCO, FC1, and FC2 all high).

SYSTEM CONTROL. The system control inputs either reset or halt the processor or indicate to the processor that bui; errors have occurred. The three system control inputs are explained in the following paragraphs.

Bus Error (BERR). The BERR input informs the processor that a problem exists with the cycle currently being executed.

Problems may be a result of:

1. nonresponding devices,

2. interrupt vector number acquisition failure,

3. illegal access request as determined by a memory manage- ment unit, or

4. other application dependent errors.

The Bus Error (BERR) signal interacts with the HALT signal to determine if exception processing should be performed or the current bus cycle should be retried.

Refer to BUS ERROR AND HALT OPERATION paragraph for additional information about the interaction of the bus error and halt signals.

Reset (RESET). This bidirectional signalli~e acts to reset (initiate a system initialization sequence) the processor and system in response to an external reset signal. An internally generated reset (result of a RESET instruction) resets all external devices while not affecting the internal state of the processor. A total system reset (processor and external devices) is the result of external HALT and RESET signals applied simultaneously. Refer to RESET OPERATION paragraph for additional information.

Halt (HALT). The bidirectional HALT line, when driven by an external device, will cause the processor to stop' at the comple- tion of the current bus cycle. Halting the processor using HALT causes all control signals to gel: inactive and all three-state lines to go to their high-impedance state. Refer to BUS ERROR AND HALT OPERATION paragraph for additional information about the interaction between the HALT and BERR signals.

When the processor has stopped executing instructions, such as in a double bus fault condition, the HALT line is driven by the processor to indicate to external devices that the processor has stopped. Refer to paragaph on Double Bus Faults.

1-6

16-Bit MPU

R6500 PERIPHERAL CONTROL. These control signals are used to allow the interfacing of synchronous R6500 peripheral devices with the asynchronous R68000. These signals are explained in the following paragraphs.

Enable (E). The E output signal is the standard enable signal (¢2 clock) common to all R6500 type peripheral devices. The period for this output is ten R68000 clock periods (six clocks low; four clocks high). Enable is generated by an internal ring counter which may come up in any state (i.e., at power on, it is impossible to guarantee phase relationship of E to CLK). E is a free-running clock and runs regardless of the state of the bus on the MPU.

Valid Peripheral Address (VPA). The VPA input indicates that the device or region addressed is a R6500 family device and that data transfer should be synchronized with the enable (E) signal. This input also indicates that the processor should use automatic vectoring for an interrupt. Refer to INTERFACE; WITH R6500 PERIPHERALS.

Valid Memory Address (VMA). The VMA output indicates to R6500 peripheral devices that there is a valid address on the address bus and that the processor is synchronized to enable.

This signal only responds to a valid peripheral address (VPA) input which indicates that the peripheral is a R6500 family device.

PROCESSOR STATUS (FCD, FC1, FC2). These function code outputs indicate the state (user or supervisor) and the cycle type currently being executed, as shown in Table 2. The information indicated by the function code outputs is valid whenever address strobe (AS) is active.

CLOCK (CLK). The clock input is a TTL-compatible signal that is internally buffered for development of the internal clocks needed by the processor. The clock input should not be gated off at any time and the clock signal must conform to minimum and maximum pulse width times.

SIGNAL SUMMARY. Table 3 summarizes all the signals dis- cussed in the previous paragraphs.

Table 2. Function Code Outputs

FC2 FCI FCO Cycle Type

Low Low Low (Undefined, Reserved)

Low Low High User Data

Low High Low User Program

Low High High (Undefined, Reserved).

High Low Low (Undefined, Reserved)

High Low High Supervisor Data

High High Low Supervisor Program High High High Interrup't Acknowledge

R68000 16-Bit MPU

Table 3. Signal Summary

Signal Name Mnemonic

Address Bus A1-A23

Data Bus DO-D15

Add ress Strobe AS

Read/Wnte R/W

Upper and Lower Data Strobes UDS, LOS Data Transfer Acknowledge DTACK

Bus Request BR

Bus Grant BG

Bus Grant Acknowledge BGACK Interrupt Priority Level IPLO, IPL 1, IPL2

Bus Error BERR

Reset RESET

Halt HALT

Enable E

Valid Memory Address VMA

Valid Peripheral Address VPA Function Code Output FCO, FC1, FC2

Clock CLK

Power Input VCC

Ground GND

'Open drain.

I

REGISTER DESCRIPTION AND DATA ORGANIZATION

STATUS REGISTER. The status register contains the eight level interrupt mask as well as the condition codes; extend (X), negative (N), zero (Z), overflow (V), and carry (e). Additional status bits indicate that the processor is in a trace (T) mode and/or in a supervisor (8) state.

SYSTEM BYTE

.

11 USER BYTE'

.

15 13 10 8 4 0

IT~S~12Hlo_xINlzlvlcl

TRACE LODE

I ^IN~T

^EXTE1NDI

^{\1 I}

STATE ZERO

SUPERVISOR MASK NEGATIVE

'I

'CONDITION CODE REGISTER

Status Register

OVERFLOW CARRY

Hi-Z

Input/Output Active State On HALT On BGACK

Output High Yes Yes

Input/Output High Yes Yes

Output Low No Yes

Output Read-High

No Yes

Write-Low

Output Low No Yes

Input Low No No

Input Low No No

Output Low No No

Input Low No No

Input Low No No

Input Low No No

Input/Output Low No' No'

Input/Output Low No' No'

Output Output Input Output Input Input Input

High No No

Low No Yes

Low No No

High No Yes

High No No

-

- -

- - -

I

OPERAND SIZE

Operand sizes are defined as follows: a byte equals 8 bits, a word equals 16 bits, and a long word equals 32 bits. The operand size for each instruction is either explicitly encoded in the instruc- tion or implicitly defined by the instruction operation. Implicit instructions support some subset of all three sizes.

DATA ORGANIZATION IN REGISTERS

The eight data registers support data operands of 1, 8, 16, or 32 bits. The seven address registers together with the active stack pointer support address operands of 32 bits.

DATA REGISTERS. Each data register is 32 bits wide. 8y1e operands occupy the low order 8 bits, word operands the low order 16 bits, and long word operands the entire 32 bits. The least significant bit is addressed as bit zero; the most signifi- cant bit is addressed as bit 31. Wh'en a data register is used as either a source or destination operand, only the appropriate low-order portion is changed; the remaining high order portion is neither used nor changed.

D

R68000 16-Bit MPU

15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

BYTE 000000

WORD ,00000

BYTE 000001 BYTE 000002

WORD tOOO02

BYTE 000003 I

WORD FFFFFE

i

BYTE FFFFFE

I

BYTE FFFFFF

Figure 2. Word Organization In Memory

ADDRESS REGISTERS. Each address register and the stack pointer is 32 bits wide and holds a full 32-bit address. Address registers do not support byte sized operands. Therefore, when an address register is used as a source operand, either the low order word or the entire long word operand is used depending upon the operation size. When an address register is used as the destination operand, the entire register is affected regardless of the operation size. If the operation size is word, any other operands are sign extended to 32 bits before the operation is performed.

DATA ORGANIZATION IN MEMORY

Bytes are individually addressable with the high order byte having an even address the same as the word, as shown in Figure 2. The low order byte has an odd address that is one higher than the word address. Instructions and multi-byte data are accessed only on word (even by1e) boundaries. If a long word datum is located at address n (n even), then the second word of that datum is located at address n + 2.

The data types supported by the R68000 are: bit data, integer data of 8, 16, or 32 bits, 32-bit addresses and binary coded decimal data. Each of these data types is put in memory, as shown in Figure 3. The numbers indicate the order in which data is accessed from ·the processor.

BUS OPERATION

The following paragraphs explain control signal and bus opera- tion during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. . DATA TRANSFER OPERATIONS. Transfer of data between devices involves the following signals:

• Address Bus Al through A23

• , Data Bus DO through D15

• Control Signals

1-8

The address and data buses are separate parallel buses which transfer data using an asynchronous bus structure. In all cycles, the bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle. In addition, the bus master is responsible for deskewing the acknowledge and data signals from the slave device.

The following paragraphs explain the read, write, and read- mOdify-write cycles. The indivisible read-modify-write cycle is the method used by the R68000 for interlocked multiprocessor communications.

Read Cycle. During a read cycle, the processor receives data from memory or a peripheral device. The processor reads by1es of data in all cases, and for a word (or double word) operation, the processor reads both upper and lower bytes simultaneously by asserting both upper and lower data strobes. When the instruction specifies by1e operation, the processor uses an internal AO bit to determine which byte to read and then issues the data strobe required for that byte. When the AO bit equals zero, the upper data strobe is issued, and when the AO bit equals one, the lower data strobe is issued. The processor correctly positions the received data internally.

A word read cycle flow chart is given in Figure 4. A byte read cycle flow chart is given in Figure 5. Read cycle timing is given in Figure 6. Figure 7 details word and by1e read cycle operations.

Write Cycle. During a write cycle, the processor sends bytes of data to memory or a peripheral device, If the instruction specifies a word operation, the processor writes both bytes.

When the instruction specifies a byte operation, the processor uses an internal AO [:lit to determine Which by1e to write and then issues the data strobe required for that byte. When the AO bit equals zero, the upper data strobe is issued and when the AO bit equals one, the lower data strobe is issued. A word write cycle flow chart is given in Figure 8. A byte write cycle flow chart is given in Figure 9. Write cycle timing is given in Figure 6.

Figure 10 details word and byte write cycle operation.

- - LONG WORD 2 - - - -

ADDRESSES 1 ADDRESS

=

^{32 BITS}

15 14 13 12 11 10 9 8 7 6 5 4 3 2

o

MSB HIGH ORDER

- - ADDRESS 0- - - -

LOW ORDER LSB

- - ADDRESS 1- - - -

- - -ADDRESS 2 - - - -

MSB

=

MOST SIGNIFICANT BIT LSB

=

LEAST SIGNIFICANT BIT

DECIMAL DATA

2 BINARY CODED DECIMAL DIGITS

=

^{1 BYTE}

15 14 13 12 11 10 9

MSD BCD 0

I

^{BCD 1}

BCD 4

I

^{BCD 5}

MSD

=

MOST SIGNIFICANT DIGIT LSD

=

LEAST SIGNIFICANT DIGIT

8 7 6 5 4

LSDI BCD 2

I

^{BCD 6}

Figure 3. Data Organization In Memory

3 2 0

I BCD 3

I

^{BCD 7}

R68000

BUS MASTER SLAVE

ADDRESS DEVICE 1) SET RIW TO READ

2) PLACE FUNCTION CODE ON FCO-FC2 3) PLACE ADDRESS ON A1-A23_

4) ASSERT ADDRESS STROBE (AS) 5) ASSERT UPPER DATA STROBE (UDS) AND

LOWER DATA STROBE (LOS)

+

INPUT DATA 1) DECODE ADDRESS

2) PLACE DATA ON 00-015

3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK)

, I

ACQUIRE DATA 1) LATCH DATA

2) NEGATE UDS AND LOS 3) NEGATE AS

TERMINATE CYCLE

+

1) REMOVE DATA FROM 00-015 2) NEGATE DlACK

START NEXT CYCLE

+

Figure 4. Word Read Cycle Flow Chart

Read-Modify-Write Cycle. The read-modify-write cycle performs a read, modifies the data in the arithmetic-logic unit, and writes the data back to the same address. In the R68000 this cycle is indivisible in that the address strobe is asserted throughout the entire cycle. The test and set (TAS) instruction uses this cycle to provide meaningful communication between processors in a multiple processor environment. TAS is the only instruction that uses the read-modify-write cycles. Since the test and set instruc- tion only operates on bytes, all read-modify-write cycles are byte operations. A read-modify-write cycle flow chart is given in Figure 11 and a timing diagram is given in Figure 12.

BUS ARBITRATION. Bus arbitration is a technique used by master-type devices to request, be granted, and knowledge bus mastership. In its simplest form, it consists of:

1. asserting a bus mastership request,

2. receiving a grant that the bus is available at the end of the current cycle, and

3. acknowledging that mastership has been assumed.

1-10

16-Bit MPU

BUS MASTER --.~~~ SLAVE ~~

ADDRESS DEVICE 1) SET RIW TO READ

2) PLACE FUNCTION CODE ON FCO-FC2 3) PLACE ADDRESS ON A1-A23_

4) ASSERT ADDRESS STROBE (AS)_

5) ASSERT UPPER DATA STROBE (UDS) OR LOWER DATA STROBE (LOS) (BASED ON AO)

I

.1

INPUT DATA 1) DECODE ADDRESS

2) PLACE DATA ON 00-07 or 08-015 (BASED ON UDS OR LOS)

3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK)

.1

J

ACQUIRE DATA 1) LATCH DATA

2) NEGATE UDS OR!LDS 3) NEGATE AS

•

TERMINATE CYCLE 1) REMOVE DATA FROM 00-015 OR 08-015 2) NEGATE DTACK

START NEtT CYCLE

Figure 5. Byte Read Cycle Flow Chart

Figure 13 is a flow chart showing the detail involved in a request from a single device. Figure 14 is a timing diagram for the same operation. This technique allows processing of bus requests dur- ing data transfer cycles.

The timing diagram shows that the bus request is negated at the time that an acknowledge is asserted. This is true for a system consisting of the processor and one device capable of bus mastership. However, in systems having a number of devices capable of bus mastership, the bus request line from each device is ORed to the processor. In this system, it is easy to see that there could be more than one bus request being made. The timing diagram shows that the bus grant signals negate a few clock cycles after the transition of the acknowledge (BGACK) signal.

However, if the bus requests are still pending, the processor will assert another bus grant within a few clock cycles after nega- tion. This additional assertion of bus grant allows external arbitra- tion circuitry to select the next bus master before the current bus master has completed its requirements. The following para- graphs provide additional information about the three steps in the arbitration process.

R68000 16-Bit MPU

CLK

H H >-

AS

\ / ^\

\ ^/

r----===~--~/ \~ ____________ ^~r-

\I-_-,r---\ r-

UDS

LDS

\ _I

^r---~\

r---\ r-

R/W

\

\ / r- ----.:==~---'/ _\ /r---\ r

DTACK

D8-D15

( ) ) >-

DO-D7

( ) ) >-

FCO-FC2

::x X

^~

_______

^~X~

____________________

^~~

I ..

^READ

---~~---WRITE--~ .. I ..

...

I ..

- - - S L O W READ---...

~I

Figure 6. Read and Write Cycle Timing Diagram

SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7

H H >--

I

I \ I \ ~

I \ ^~

I \ I

;---\ I \ r--

) ( ) - -

) )

X X >--

DO-D7~~~~~~~~~~~~~~~~~~~~~~~~~~~~~====

FCO-FC2

::::x _______

^{. . J}

·INTERNAL SIGNAL ONLY

f.--WORD READ-_*,"I---... 1 . . ODD BYTE READ ... 1 . . EVEN BYTE REAO--..\

Figure 7. Word and Byte Read Cycle Timing Diagram

Requesting the Bus. External devices capable of becoming bus masters request the bus by asserting the bus request (BR) signal.

This ORed signal (although it need not be constructed from open collector devices) indicates to the processor that some external device requires control of the external bus. The processor, at a lower bus priority level than the external device, will relinquish the bus after it has completed the last bus cycle it has started.

If no acknowledge is received before the bus request signal goes inactive, the processor will continue processing when it detects that the bus request is inactive. This allows ordinary processing to continue if the arbitration circuitry inadvertently responded to noise.

Receiving the Bus Grant. Normally the processor asserts bus grant (BG) as soon as possible after internal synchronization. The only exception occurs when the processor has made an inter- nal decision to execute the next bus cycle but has not progressed far enough into the cycle to have asserted the address strobe (AS) signal. In this case, bus grant will not be asserted until one clock after address strobe is asserted to indicate to external devices that a bus cycle is being executed.

The bus grant signal may be routed through a daisy-chained network or through a specific priority-encoded network. The proc- essor is not affected by the external method of arbitration as long as the protocol is obeyed.

II

R6S000 16-Bit MPU

BUS MASTER SLAVE BUS MASTER SLAVE

I 1

ADDRESS DEVICE Aiju"ES:> UI:VI"'t:

1) PLACE FUNCTION CODE ON FCO-FC2 1) PLACE FUNCTION CODE ON FCO-FC2

2) PLACE ADDRESS ON A1-A23_ 2) PLACE ADDRESS ON A1-A23_

3) ASSEI!!: ADDRESS STROBE (AS) 3) ASSERT ADDRESS STROBE (AS)

4) Set R/W TO WRITE

5)

PLACE DATA ON DO-D7 or D8-D15 (ACCORDING 4) Set R/W TO WRITE

5) PLACE DATA ON DO-D15

6) ASSERT UPPER DATA STROBE (UDS) AND TO AO)

LOWER DATA STROBE (LDS) 6) ASSERT UPPER DATA STROBE (UDS) OR

LOWER DATA STROBE (LDS) (BASED ON AO)'

,

INPUT DATA

--'-

INPUT DATA 1) DECODE ADDRESS

2) STORE DATA ON DO-D7 If LDS IS ASSERTED STORE DATA ON D8-D15 IF UDS IS ASSERTED 3) ASSERT DATA TRANSFER

ACKNOWLEDGE (DT ACK)

i J

1) DECODE ADDRESS 2) STORE DATA ON DO-D15 3) ASSERT DATA TRANSFER

ACKNOWLEDGE (DTACK)

t I

TERMINATE OUTPUT TRANSFER 1) NEGATE UDS AND LDS

2) NEGATE AS TERMINATE OUTPUT TRANSFER

1) NEGATE UDS OR LDS 2) NEGATE AS

3) REMOVE DATA FROM DO-D15 4) SET R/W TO READ

3) REMOV.! DATA FROM DO-D7 OR D8-D15 4) SET R/W TO READ

~

TERMINATE CYCLE

J

1) NEGATE DTACK

t

TERMINATE CYCLE 1) NEGATE DTACK

• I •

START NEXT CYCLE START NEXT CYCLE

Figure 8_ Word Write Cycle Flow Chart Figure 9_ Byte Write Cycle Flow Chart SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO 51 S2 S3 54 S5 S6 57

CLK

AO"

AS=~==~---~(~==~~======~ __ ^~==~ __ ^~

UDS \

I

LDS ---~,----!r---~

R / W J \

DTACK \

D8-D15 DO-D7

===>--<=~~~~~~~~~~~ ====>---C

FCO-FC2

.J(.,.-_ _ _ _ _ _ --'

"INTERNAL SIGNAL ONLY

~

WORD WRITE ..

I..

ODD BYTE WRITE

_I"

EVEN BYTE WRITE--!

Figure 10. Word and Byte Write Cycle Timing Diagram

1-12

R68000 16-Bit MPU

BUS MASTER SLAVE

II

ADDRESS DEVICE

1) SET R/W TO READ

•

2) PLACE FUNCTION CODE ON FCO-FC2 INPUT DATA

3) PLACE ADDRESS ON A1-A23 1) DECODE ADDRESS

4) ASSERT ADDRESS STROBE (AS)_ 2) PLACE DATA ON 00-07 OR 08-015 5) ASSERT UPPER DATA STROBE (UDS) OR 3) ASSERT DATA TRANSFER ACKNOWLEDGE

LOWER DATA STROBE (LOS) (DTACK)

• • I

ACQUIRE DATA

1) LATCH DATA TERMINATE CYCLE

2) NEGATE UDS OR LOS 1) REMOVE DATA FROM 00-07 OR 08-015

3) START DATA MODIFICATION 2i NEGATE DTACK

I

• •

START OUTPUT TRANSFER

1) SET RiW TO WRITE INPUT DATA

2) PLACE DATA ON 00-07 or 08-015 1) STORE DATA ON 00-07 OR 08-015 3) ASSERT UPPER DATA STROBE (UDS) OR 2) ASSERT DATA TRANSFER ACKNOWLEDGE

LOWER DATA STROBE (LOS) (DTACK)

• I

TERMINATE OUTPUT TRANSFER

~

1) NEGATE UDS OR LOS

2) NEGATE AS TERMINATE CYCLE

3) REMOVE DATA FROM 00-07 OR 08-015 1) NEGATE DTACK 41 SET RiW TO READ

, I

START NEXT CYCLE

Figure 11. Read-Modify-Write Cycle Flow Chart

""1 . . - - - -INDIVISIBLE CYCLE

---I~~I

Figure 12. Read-Modify-Write Cycle Timing Diagram

R68000

PROCESSOR REQUESTING DEVICE

REQUEST THE BUS 1) ASSERT BUS REQUEST (BR)

I

GRANT BUS ARBITRATION

+

1) ASSERT BUS GRANT (BG)

I

I +

ACKNOWLEDGE BUS MASTERSHIP 1) EXTERNAL ARBITRATION DETERMINES

NEXT BUS MASTER

2) NEXT BUS MASTER WAITS FOR CUR- RENT CYCLE TO COMPLETE 3) NEXT BUS MASTER ASSERTS BUS

GRANT ACKNOWLEDGE (BGACK) TO TO BECOME NEW MASTER 4) BUS MASTER NEGATES BR

,

I

I

TERMINATE ARBITRATION.

1) NEGATE BG (AND WAIT FOR

I

BGACK TO BE NEGATED)

I

,

OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFER (READ AND

WRITE CYCLEl?) ACCORDING TO THE SAME RULES THE PROCESSOR USES.

•

RELEASE BUS MASTERSHIP 1) NEGATE BGACK

I

RE-ARBITRATE OR RESUME

+

I

PROCESSOR OPERATION

Figure 13. Bus Arbitration Cycle Flow Chart

Acknowledgment of Mastership. Upon receiving a bus grant (BG), the requesting device waits until address strobe (AS), data transfer acknowledge (DTACK), and bus grant acknowledge (BGACK) are negated before issuing its own BGACK. The nega- tion of the address strobe indicates that the previous master has completed its cycle, while the negation of bus grant acknowledge indicates that the previous master has released the bus. (If address strobe is asserted no device is allowed to "break into"

a cycle.) The negation of data transfer acknowledge indicates the previous slave has terminated its connection to the previous master. In some applications data transfer acknowledge may not be required. In this case the devices would use the address strobe. When bus grant acknowledge is issued the device is bus master. Only after the bus cycle(s) is (are) completed should bus grant acknowledge be negated to terminate bus mastership.

1-14

16-Bit MPU

The bus request from the granted device should be dropped after bus grant acknowledge is asserted. If a bus request is still penaing, anotner DUS grant wlil be asserted within a few clocks of the negation of bus grant. Refer to Bus Arbitration Control section. The processor does not perform any external bus cycles before it reasserts bus grant.

BUS ARBITRATION CONTROL. The bus arbitration control unit in the R68000 is implemented with a finite state machine. A state diagram of this machine is shown in Figure 15. All asynchronous signals to the R68000 are synchronized before being used inter- nally. This synchronization is accomplished in a maximum of one cycle of the system clock, assuming that the asynchronous input setup time (#47) has been met (see Figure 16). The input signal is sampled on the falling edge of the clock and is valid internally after the next falling edge. If BR and BGACK meet the asynchronous set-up time tASI (#47), then tBGKBR (#37A) can be ignored. If BR and BGACK are asserted asynchronously with respect to the clock, BGACK has to be asserted before BR is negated.

As shown in Figure 15, input signals labeled Rand A are inter- nally synchronized on the bus request and bus grant acknowledge pins respectively. The bus grant output is labeled G and the internal three-state control signal T. If T is true, the address, data, and control buses are placed in a high-impedance state when AS is negated. All signals are shown in positive logic (active high) regardless of their true active voltage level.

State changes (valid outputs) occur on the next rising clock edge after the internal signal is valid.

A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in Figure 17. The bus arbitration sequence while the bus is inactive (i.e., executing internal opera- tions such as a multiply instruction) is shown in Figure 18.

If a bus request (BR) is made at a time when the MPU has already b~n a bus cycle but AS has not been asserted (bus state SO), BG will not be asserted on the next rising edge. Instead BG will be delayed until the second rising edge following its inter- nal assertion. This sequence is shown in Figure 19.

BUS ERROR AND HALT OPERATION. In a bus architecture that requires a handshake from an external device, the possibility exists that the handshake might not occur. Since different systems will require a different maximum response time, a bus error input is provided.

External circuitry must be used to determine the duration between address strobe and data transfer acknowledge before issuing a bus error signal. When a bus error signal is received, the processor has two options: initiate a bus error exception sequence or try running the bus cycle again.

R68000 16-Bit MPU

I \

BG

\ I \ I

BGACK

\ I \

PROCESSOR~ DMA DEVICE

~I·

^PROCESSOR

~I·

DMA DEVICE ~

Figure 14. Bus Arbitration Cycle Timing Diagram

Ri\"

RA R

=

BUS REQUEST INTERNAL

A

=

BUS GRANT ACKNOWLEDGE INTERNAL G = BUS GRANT

T

=

THREE·STATE CONTROL TO BUS CONTROL LOGIC² X

=

DON'T CARE

1. STATE MACHINE WILL NOT CHANGE STATE IF BUS IS IN SO OR S1. REFER TO BUS ARBITRATION CONTROL FOR ADDITIONAL INFORMATION.

2. THE ADDRESS BUS WILL BE PLACED IN THE HIGH IMPEDANCE STATE IF T IS ASSERTED AND AS·

NEGATED.

Figure 15. State Diagram of R68000 Bus Arbitration Unit

INTERNAL SIGNAL VALIDl EXTERNAL SIGNAL],

SAMPLED , ,

CLK I

BGACK---~

'THIS DELAY TIME IS EQUAL TO PARAMETER #33, ICHGL

Figure 16. Timing Relationship of External Asynchronous Inputs to Internal Signals

Bus Error Operation. When BERR is asserted, the current bus cycle is terminated. If BERR is asserted before the falling edge of 52, A5 will be negated in 57 in either a read or write cycle.

As long as BERR remains asserted, the data and address buses will be in the high-impedance state. When BERR is negated, the processor Will begin stacking lor exception processing.

Figure 20 is a timing diagram for the exception sequence. The sequence is composed of the following elements:

1. stacking the program counter and status register, 2. stacking the error information,

3. reading the bus error vector table entry, and 4. executing the bus error handler routine.

R68000

BUS RELEASED FROM THREE BUS THREE STATED---, STATE AND PROCESSOR

BG ASSERTED STARTS NEXT BUS CYCLE

BR VALID INTERNAL BGACK NEGATED INTERNAL

BR SAMPLED BGACK SAMPLED

BR ASSERTED BGACK NEGATED

16-Bit MPU

CLK BR BG BGACK

A1·A23

AS

SO 51 52 S3 54 55 56 57 SO 51

UDS LOS

•

^PROCESSOR

-I-

ALTERNATE BUS MASTER

-I-

Figure 17. Bus Arbitration During Processor Bus Cycle

\

PROCESSOR

•

BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE---, BGACKNEGATED _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - ,

BG ASSERTED AND BUS THREE STATED----..., BR VALID INTERNAL _ _ _ _ _ _ _ ---, BR SAMPLED - - - , BR ASSERTED---:t..

CLK

50.51 525354555657

BR ________________

~\======~~I

BG \

I

BGACK \ /

SO 51 52 S3 54

'---~

A1.A23:~:j~~========~~==========~~========================;=~(~~===

AS \ /

~

UDS

\~----~/,---~---~

LOS \

I

^~

FCO·FC2 ~---~

-:J..============})---C====

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ T - - - -

OTACK - - - -____

'--1

00·015 --===-::!-(=======)~:::-::=:::::_--_:::::==:_:;:_:::::::;:---_:::=::::::_

_{PROCESSOR •}

I.

BUS INACTIVE _

I_

ALTERNATE BUS MASTER •

I

^!ROCESSO~

Figure 18. Bus Arbitration with Bus Inactive

1·16

R6S000 16-Bit MPU

BUS RELEASED FROM THREE

BR ASSERTED STATE AND PROCESSOR

BR SAMPLED STARTS NEXT BUS CYCLE - - - ,

BUS THREE S T A T E D l l BGACK NEGATED INTERNAL

BG ASSERTED BGACK SAMPLED - - - ,

BR VALID INTERNAL BGACK NEGATED

II

SO Sl S2 S3 S4 S5 S6 S7 SO Sl S2 S3 S4 S5 S6 S7 SO Sl BR

'--..:========:::::;-____ ^__'1

BG \

1

BGACK---~======~\======~

^__

~I

A1-A23

==>--<2~:;====2)==-==---=----_:=~( ;;====;>-e

AS~ \~ ______ __'f'---'~~

____

^~r____

UDS --.lr---~\

f'

^~'-

___ --'r____

LOS

-.I \'-______ -'f'

^~'-

___ --'r____

FCO-FC2

~ 'C...

R/W -1~---""""\.

__________________ F---

DTACK-~~

^__

~~~~~{:=====~--~~~~~~----~\====~===r----=====

00-015 -

PROCESSOR ..

I ..

ALTERNATE BUS MASTER ..

I.

PROCESSOR

.. ..

Figure 19. Bus Arbitration During Processor Bus Cycle Special Case

AS \~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - J

LOS UDS \

R/W

D T A C K - - - -

00-015

=::::==~(~~~~~~~~;;;;;;;;;;;;;;;;;;;;;;;;C=j

FCO-2

J ~-~=======

BERR _________________________ \~================~

HALT

I JNITIATi-I.. RESPONSE FAILURE -.~j...I----BUS ERROR DETECTION _""'If+--"-IN;;;;..IT;c.IA;.;;.T;;.;;E;;..Bo;..U,,,SO-

READ ~ "ERROR STACKING

Figure 20. Bus Error Timing Diagram