CMOS-Compatible Ti/Al Ohmic Contacts (Rc < 0.3 Ω mm) for
u-AlGaN/AlN/GaN HEMTs by Low Temperature Annealing (< 450 °C)
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Citation Liu, Zhihong, et al. "CMOS-Compatible Ti/Al Ohmic Contacts (Rc
< 0.3 Ω mm) for u-AlGaN/AlN/GaN HEMTs by Low Temperature Annealing (< 450 °C)." 2014 72nd Device Research Conference, 22-25 June, 2014, Santa Barbara, California, IEEE, 2014, pp. 75–76.
As Published http://dx.doi.org/10.1109/DRC.2014.6872304
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Version Author's final manuscript
Citable link http://hdl.handle.net/1721.1/116106
Terms of Use Creative Commons Attribution-NoDerivatives
CMOS-Compatible Ti/Al Ohmic Contacts (R
c<0.3
mm)
for u-AlGaN/AlN/GaN HEMTs by Low Temperature Annealing (<450
oC)
Zhihong Liu,1 Michael Heuken2, Dirk Fahle2 Geok Ing Ng1,3, and Tomás Palacios,1,4 1
Singapore-MIT Alliance for Research and Technology, 117543, Singapore;
2
AIXTRON SE, Herzogenrath, D-52134,Germany
3
School of EEE, Nangyang Technological University, 639798, Singapore
4
Microsystem Technology Lab, Massachusetts Institute of Technology, 02139-4307, USA
Recently the development of CMOS-compatible fabrication technologies for GaN HEMTs has attracted increasing levels of interest [1]-[4]. A low temperature ohmic contact technology is required for gate-first device fabrication and CMOS-first GaN-Si integration process, however, typical ohmic contacts need annealing at > 800 oC [1], [2]. In the past, we have reported an approach to realize low contact resistance (RC) using CMOS-compatible metal
schemes annealed at 500 oC through an n+-GaN/n-AlGaN/GaN structure [4]. This method has a drawback that the n-doped AlGaN barrier increases the gate leakage current. In this work, we present the first low temperature (<450 oC) CMOS-compatible Ti/Al ohmic contact technology for conventional unintentionally-doped AlGaN/AlN/GaN HEMT structures.
Fig. 1 shows the schematic of the u-AlGaN/AlN/GaN structure, same as that in [2]. Hall measurements show that the wafer has a 2DEG density of 1x1013 cm-2 and mobility of 2100 cm2/Vs. The structure was grown by a conventional MOCVD in a planetary reactor. CMOS-compatible ohmic contacts were formed by a recess etch using low-power BCl3/Cl2
plasma and then Ti/Al (40/200 nm) ohmic metallization. The schematic of the ohmic contact is shown in Fig. 1. Fig. 2 (a) shows the optical micrograph of the TLM patterns after 500 oC RTA. The Ti/Al metal surface remains smooth after 500 oC annealing. Fig. 2(b) shows the I-V characteristics measured between two ohmic metal pads with 6-m distance after RTA at various temperatures. High saturation current was achieved using low-temperature annealing and Au-free ohmic contact. Fig. 2(c) shows the TLM results of total resistance versus pad distance at different temperatures; Fig. 2(d) shows the RC and saturation current after RTA at
various temperatures. Low RC of <0.3 mm was achieved after RTA at 450 oC - 500 oC for 30
s. Fig. 3 shows the lowest RC achieved at various RTA temperatures with a recess depth
optimized at each temperature point. RC<0.5 mm can be achieved over a wide RTA
temperature window from 425 oC to 550 oC. A u-AlGaN/AlN/GaN HEMT was demonstrated through BCl3/Cl2 mesa etching, Ti/Al ohmic contact as abovementioned, and then Ni/Al gate
metallization. Fig. 4 shows the DC characteristics ((a) output characteristics; (b)(c) transfer characteristics and (d) gate current characteristics) of the device. Similar characteristics were achieved compared to those devices fabricated with Au-contained ohmic and gate contact. This shows the great potential of this low-temperature ohmic contact technology.
Acknowledgements - This research was supported by the National Research Foundation Singapore through
REFERENCES:
[1] H. S. Lee, et al., IEEE EDL, 32(2011)623. [2] Z. Liu, et al. APEX, 6(2013)096502. [3] M. V. Hove, et al. EDL, 33(2012)667. [4] Z. Liu, et al, presented on ICNS 2013.
-10 -8 -6 -4 -2 0 2 4 6 8 10 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 400 o C 425 oC 450 o C 475 oC 500 o C 525 oC 550 o C 575 o C C u rre n t (m A /m m ) Voltage (V) Ohmic recess=60 nm Ti/Al=40/200 nm Pad distance=6 m -20 -15 -10 -5 0 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 Igat e ( m A /m m ) Vgate (V) -8 -7 -6 -5 -4 -3 -2 -1 0 10-3 10-2 10-1 100 101 102 103 Vd=1 V Id ra in (m A /mm) Vgate (V)
Fig. 1 Schematic of the wafer structure and source/drain ohmic contact by means of recess.
(a)
Fig. 3 Best ohmic contact results at different annealing temperatures achieved with recess depth optimized at each temperature point.
Fig. 4 (a) DC output (b), (c) transfer and (d) gate characteristics of a GaN HEMT fabricated using the developed low-temperature CMOS-compatible ohmic contact technology. The device has Lg=2 m and Lsd=7
m. The device shows Idmax(Vg=1V)=670 mA/mm, Ron=4.2 mm, gmmax=155 mS/mm,Subthreshold Slope
(SS)=159 mV/dec. Ion/Ioff=2.7x105, Ileak(at Vgd= - 20V) =
5x10-3 mA/mm. (a) (b) 6” High-Resistivity Si (111) Substrate Transition/Seedling layer Gate Drain GaN buffer 1.5 m UID-Al 0.25Ga0.75N 20 nm GaN cap 3 nm AlN spacer 1 nm 2DEG Source Ti/Al Ti/Al 400 500 600 700 800 0.0 0.5 1.0 1.5 2.0 Annealing Temperature (o C) Cont act Resis tance R c ( mm ) Annealing Time: 30s - 60s 0.3 10-10 10-9 10-8 10-7 10-6 10-5 10-4 Speci fic Cont act Resist ivi ty c ( cm 2 ) 0 2 4 6 8 10 12 14 16 18 20 0 100 200 300 400 500 600 700 800 Id ra in ( m A /m m ) Vdrain (V) Vg=+1V -> -6V, Step: -1V -6 -5 -4 -3 -2 -1 0 1 2 0 100 200 300 400 500 600 700 800 Vgate (V) Id ra in ( m A /m m ) 0 20 40 60 80 100 120 140 160 180 Vd=4,6,8,10 V g m ( m S /mm) 400 450 500 550 600 0.1 1 10 100 1000 RC ( mm ) Temperature (oC) -1200 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 Rec 60 nm Ti/Al 40/200nm RTA 30s Current (at V= 10 V ) (mA/mm) 0 3 6 9 12 15 18 21 24 0 20 40 60 80 100 425 o C 450 oC 475 o C 500 oC 525 o C 550 oC 575 o C Rto ta l ( -mm) Pad Distance (m) TLM width=100 m 100 m
Fig. 2 (a) Optical micrograph of TLM patterns after annealing at 500 oC; (b) Current-voltage characteristics of a TLM pattern with pad distance of 6 m annealed at various temperatures; (c) The total resistances versus pad distances in TLM patterns after annealing at various temperatures; (d) Rc and saturation current (10V, 6 m distance)
after annealing at various temperatures. (c)
(d)
(a) (b)
