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Abstract—This paper, proposes a new architecture to reduce the silicon area of the Cartesian feedback (CFB) used to linearize a power amplifier in WCDMA communication standard. The first stage of the previous version consists of two CORDIC structures in vector mode for the phase computation following by a subtractor. Here, we propose to merge these two CORDIC structures to obtain directly the phase difference between the feedback and the direct paths. This approach allows reducing the silicon area as well as the power consumption.
Index Terms—PA linearization, CORDIC, digital design
I. INTRODUCTION
N the field of embedded electronics and particularly radio frequency system, Power Amplifier (PA) is the most critical element in terms of power consumption. Because of its nature when we try to save efficiency of PA it has a nonlinear behavior. The problem is that nonlinear behavior decreases spectral efficiency by transmitting on adjacent channels, what is absolutely forbidden above a certain limit by radio communications standards. The only way to have an efficient system is to use an architecture that increases PA efficiency and keeps its linearity. Several methods already exist to increase PA linearity. Post-distortion is a technique which consists in modifying signal after the PA in order to correct its nonlinearity. One realization of post-distortion was done in [1]. Pre-distortion is another technique which consists in modifying signal before the PA in order to anticipate its nonlinearity. One realization of pre-distortion was done in [2].
Cartesian feedback (CFB) is a technique which makes a control on I and Q signals by a feedback process. The first effective Cartesian feedback system was proposed by J.
Dawson [3]. It was a full analog system. Many others techniques exist and even combinations can been done. But those are ones of the most simple to realize.
This paper will take an interest in CFB realization and particularly in its digital form. CFB technique suffers from practical concerns. Realizations need a phase correction which now is made digitally. A CFB architecture is proposed in [4]
using digital blocks. This architecture has to comply with
precision, frequency and latency constraints. Two solutions are given, one based on LUTs and the other using CORDIC algorithms. An improved architecture based on the not fully pipeline implementation of CORDIC algorithms has been proposed in [5]. This one provides the same functionality but with a better latency and less silicon area. The purpose of this paper is to reuse the CFB implementation proposed in [5] to optimize its architecture in terms of silicon area and power consumption. Those optimizations have been done by a review of architecture.
The paper is organized as follow. In section II we propose a brief recall of the Cartesian feedback principle applied to PA linearization. Then in section III we propose the new architecture and simulation results. Then in section IV we propose a study of synthesis with the 65nm technology from STMicroelectronics. Finally, a conclusion will be drawn.
II. CARTESIAN FEEDBACK A. Principle
Cartesian feedback is a linearization technique used to increase transmitter performances. The effectiveness of the CFB has been studied in [5]. The ACPR is strongly reduced and allows complying the spectral constraints of WCDMA standard.
To make a CFB linearization, the output of the PA is down- converted and signals are compared to input signals (I,Q) to make a self-controlled system. Figure 1 shows a basic scheme of CFB principle regardless of realization.However, the ideal scheme is not available and the system needs a phase correction which first was proposed in [3].
B. Phase correction
Because of up-conversion followed by down-conversion realized by two separate local oscillators, the coupled signals (I,Q) and (IFB,QFB) suffer from mismatch errors. In Cartesian plan (I,Q) this alteration results in a rotation of vector by an unknown angle. The physical explanation of this rotation is the phase shift between oscillators for up and down- conversion. One solution is to make an analog control to force oscillators to have the same phase. Another solution is to compensate this phase directly on I and Q signals in baseband domain. This compensation can be done in an analog form as proposed in [3] or in a digital form [4], [5].
Study and Analysis of a New Implementation of a Mixed-Signal Cartesian Feedback for a Low
Power Zero-IF WCDMA Transmitter
A. Aulery
1,2, D. Dallet
1, B. Le Gal
1, N. Deltimple
1, D. Belot
2, E. Kerherve
11Université de Bordeaux, Laboratoire IMS, CNRS UMR 5218, IPB, Talence, France,
2ST Microelectronics, Minatec, Grenoble, France
I
978-1-4799-0620-8/13/$31.00 ©2013 IEEE
2
C. Digital implementation
Current approaches consist of digital compensation and correction of (I,Q) signals. Digital solution has the advantage to be deterministic, when it doesn’t suffer from deviation over time. More over precision is predetermined. Figure 2 shows mixed analog-digital architecture of a CFB.
D. Constraints
The purpose of this work is to offer strictly the same functionality than [5] with less silicon area, therefore we are considering WCDMA context with the same requirements than in [5]. To dimension the system (number of operators, bus size, etc…) the intended precision is 1°. The frequency is set to 240MHz by ADCs and DACs which is a compromise between frequency and resolution. According to study [6] the maximum latency (Δt) accepted for Cartesian feedback is:
Δt
BW (1)where BW is the bandwidth of input signal. In case of WCDMA with a raised cosine filter, bandwidth is up to
5MHz. That allows a maximum latency of 50ns, which is equivalent to 12 clock cycles of a 240 MHz clock frequency.
E. CORDICs based solution
The actual algorithm used to compute error can be described as follow: 1) – compute the angle between command and measure, 2) – rotate measure vector by the computed angle, 3) – compute error between command and rotated measure.
Figure 3 shows the architecture that realizes this algorithm.
An architecture proposed in [4] realizes this algorithm complying with precision, frequency and latency constraints in 65nm CMOS technology from STMicroelectronics. To synthesize the algorithm, various CORDICs architectures are used. Two CORDICs are used to compute angles of input vectors called atan CORDICs. A third CORDIC is used to realize rotation of vector. An optimized solution using not fully-pipelined CORDICs was proposed in [5].
Based on some mathematical observations, it appears that some intermediate calculations are redundant. The purpose of this paper is to optimize the design proposed in [5] to reduce the silicon area and the power consumption.
III. PROPOSED ARCHITECTURE A. Mathematical study
Existing atan CORDICs architecture allows calculating angles using Cartesian coordinate of vector. CFB algorithm needs two atan blocks followed by a subtraction of the estimated angles. A new architecture has been done merging two atan CORDICs to directly compute difference of angles.
Resulting architecture is scalable like all other CORDIC architecture.
The atan CORDIC computes angle by iterative pseudo- rotations. To increase accuracy of the result, at each iteration, the actual angle is added or subtracted by the angle of the pseudo-rotation depending on the direction. Angles of pseudo- rotation are constant and already known by the system. If θfw
is the estimated angle of command and n is the number of iterations, it will be expressed by:
(2)
It appears that the final result can be stored or generated only by knowing the consecutives directions of pseudo- rotation. On the initial design the two angles θfw andθfb are Figure 1: Global scheme of CFB architecture
Figure 3: Architecture of digital part based on CORDIC
Figure 2: Global scheme of CFB mixed architecture
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estimated by two identical atan CORDIC blocks and then are subtracted. Therefore result of subtraction can be expressed by:
(3)
That means that the result of subtraction can also be stored or generated by knowing the consecutives directions of rotation of the atan CORDICs. The key to reduce redundant calculation is to compute immediately subtraction depending on direction of rotation of the two atan CORDICs.
0, if and same sign
2, if 0 and 0
2, if 0 and 0
(4)
B. Architecture of CORDIC
Initial architecture of atan CORDIC used in [5] is shown Figure 4.
Each horizontal stage is composed of tree operators and corresponds to an iteration of algorithm.As we can see in figure 5 the result of the merged CORDIC architecture is a new design less complex in terms of operators than the one based on two separated atan CORDICs. We can notice that
this design is also scalable in the same way that others CORDICs architectures.
With this new design the precision is the same because the functionality is preserved. The critical path is unchanged so the frequency is also preserved. To keep the same latency we just have to repeat the same pipelining model used in [5].
C. Simulation results
Simulations have been done to confirm that functionality and precision are preserved. Results of Modelsim simulations are depicted Figure 6. Note that 1° precision is not absolute precision and it can never been achieved because of “quantum error” of digital system. But precision is reached in terms of average and standard deviation.
IV. DESIGN SYNTHESIS CONSIDERATIONS
Designs have been synthesized using Design Compiler from Synopsys and 65nm CMOS standard cell libraries from STMicroelectronics. Operating frequency was set to 240 MHz and logical synthesis tool determines resources required to reach this frequency. This synthesis was also done for previous architecture [5] to perform comparison. Two different libraries have been used to fairly evaluate the impact of technological choice on area saving.
The first selected library is a low power, low Vt (CORE65LPLVT), nominal values, 1.0V supply and operating temperature 25°C. The second one is a low power, standard Vt (CORE65LPSVT), worst case values, 1.1V supply and operating temperature 125°C.
The configuration options enable the Design Compiler tool to dissolve blocks for a better optimization. The drawback effect of this optimization comes from the fact that design structure is lost. Area and power consumption estimations for the global designs are summarized in Table I and Table II.
Taking into account the previous and the merged architectures discussed in this paper, almost 8% area saving should be observed. Indeed, three CORDICs with three columns for each were used in [5]. However, column widths are different as each CORDIC has two columns of 20 bit Figure 4: atan CORDIC architecture
Figure 5: Merged atan CORDIC architecture
Figure 6: Phase error result of Merged CFB
4 width and one column of 12 bit width. In the merged
architecture one column of 12 bit width in the first stage was suppressed. Then 12/156 reduction is expected. Tables I show that we achieve about 5% area saving and 5% power saving when targeting the CORE65LPLVT library.
Table I: CFB compilation result at 240 MHz targeting CORE65LPLVT library
Table II: CFB compilation result at 240 MHz targeting CORE65LPSVT library
Regarding Table II, it can be noticed that estimated area and power consumption are higher when targeting the CORE65LPSVT library. Moreover area and power consumption reduction are lower (almost 3% for each instead of 5%). These results are due to the fact that targeted library uses worst case parameters, generating higher cost designs to reach frequency. Moreover the increase of area is not uniform for all modules, that is why the overall area and power consumption reductions are lower.
Table III: Compilation result of all blocks of CFB at 240 MHz targeting CORE65LPLVT library
Table IV: Compilation result of all blocks of CFB at 240 MHz targeting CORE65LPSVT library
Tables III and IV provide a finer analysis of the architecture
cost. Sub-modules have been synthesized independently in order to estimate area saving. In these tables “Phase Incr.”
corresponds to the sum of the two atan CORDICs for the previous design or to the merged CORDIC for our paper.
“Rotation” corresponds to the rotational CORDIC. “Others”
corresponds to registers and operators used to connect modules, inputs and outputs.
Complete design area named “All incr.” is larger but closed to area provided in Table I and II. This difference comes from the fact that the logical synthesis tool has not dissolved the full architecture during synthesis.
This hierarchical results show that area saving on the “phase incr” is close to the theoretical one (11%).
V. CONCLUSION
In this work, we proposed a novel architecture to realize the digital phase correction of the Cartesian Feedback linearization technique. The proposed solution relies on a merged CORDIC architecture which allows performing angle estimation. Mathematical study highlights redundant intermediate calculations and allows modifying architecture.
ModelSim simulations validate the functionality with the 1°
precision required by the system specification. Design Complier was used to synthesize building blocks from VHDL source with a critical path which responds to WCDMA specifications. Moreover, the proposed solution offers 5%
savings in die area compared to the previous work.
REFERENCES
[1] J-H. Tsai, H-Y. Yang, C-C. Kuo, and T-W. Huang, “A Miniature 38-48 GHz MMIC Sub-Harmonic Transmitter With Post-Distortion Linearization” IEEE 2007.
[2] JA. Sills, R. Sperlich, “Adaptive Power Amplifier Linearization by Digital Pre-distortion Using Genetic Algorithms” IEEE 2002 [3] J. L. Dawson, T. H. Lee, ”Automatic Phase Alignment for a
Fully Integrated Cartesian Feedback Power Amplifier System”
IEEE, Solid-State Circuits, vol. 38, pp. 2269--2279, 2003.
[4] M. Abid, N. Delaunay, B. Le Gal, D. Dallet, C. Rebai, N.
Deltimple, E. Kerherve, D. Belot, “Mixed Cartesian Feedback for Zero-IF WCDMA Transmitter“IEEE 2011 Second Latin American Symposium on Circuits and Systems, LASCAS, 2011.
[5] W. Sanaa, N. Delaunay, B. Le Gal, D. Dallet, C. Rebai, N.
Deltimple, D. Belot, E. Kerherve “Design of a Mixed-Signal Cartesian Feedback Loop for a Low Power Zero-IF WCDMA Transmitter” IEEE 2012 Second Latin American Symposium on Circuits and Systems, LASCAS 2012.
[6] A. Katz, ‘‘Linearization: reducing distortion in power amplifiers,’’ IEEE Microwave Magazine, vol.2, no.4, pp.37-49, Dec 2001.
Design Area Power Area gain Power gain Previous CFB 33100 µm² 3.44 mW - - Merged CFB 31400 µm² 3.27 mW 5.14% 4.94 %
Design Area Power Area gain Power gain Previous CFB 46700 µm² 5.52 mW - - Merged CFB 45200 µm² 5.35 mW 3.21% 3.08 %
Table III Previous CFB Saving obtained with merged approach Design Modul(s) Area (µm²) Power
(mW) Area Power
Previous CFB
Phase
incr 20100 2.38 7.5 % 7.2 % Rotation 10800 0.46 0.0 % 0.0 %
Others 3500 0.93 11.4% 1.3%
All incr 34400 3.78 5.5 % 6.0 %
Table IV Previous CFB Saving obtained with merged approach Design Modul(s) Area
(µm²) Power
(mW) Area Power
Previous CFB
Phase
incr 27100 4.17 6.3 % 3.6 % Rotation 17100 0.62 0.0 % 0.0 %
Others 3600 0.93 11.1% 1.3%
All incr 47800 5.72 4.4 % 3.1 %
