Quad/Octal,SimultaneousSampling,24-BitAnalog-to-DigitalConverters FEATURESDESCRIPTIONAPPLICATIONS

(1)

APPLICATIONS

VREFP VREFN AVDD DVDD

TEST[1:0]

FORMAT[2:0]

CLK SYNC PWDN[8:1]

CLKDIV Control

Logic SPI and Frame-

Sync Interface

IOVDD

DGND AGND

DRDY/FSYNC SCLK DOUT[8:1]

DIN Input2

Input1

Input4 Input3

Input6 Input5

Input8 Input7

DS DS DS DS DS DS DS DS PWDN[4:1]

ADS1278

Four Digital Filters

AVDD DVDD

TEST[1:0]

FORMAT[2:0]

CLK SYNC CLKDIV Control

Logic SPI and Frame-

Sync Interface

IOVDD

DGND AGND

DRDY/FSYNC SCLK DOUT[4:1]

DIN

ADS1274

MODE[1:0]

Eight Digital Filters VREFP VREFN

Input2 Input1

Input4 Input3

DS DS DS DS

• Simultaneously Measure Four/Eight Channels Based on the single-channelADS1271, the ADS1274 (quad) and ADS1278 (octal) are 24-bit, delta-sigma

• Up to 128kSPS Data Rate

(ΔΣ) analog-to-digital converters (ADCs) with data

• AC Performance:

rates up to 128k samples per second (SPS), allowing 62kHz Bandwidth

simultaneous sampling of four or eight channels. The 111dB SNR (High-Resolution Mode) devices are offered in identical packages, permitting

–108dB THD drop-in expandability.

• DC Accuracy:

Traditionally, industrial delta-sigma ADCs offering 0.8µV/°C Offset Drift

good drift performance use digital filters with large 1.3ppm/°C Gain Drift passband droop. As a result, they have limited signal

• Selectable Operating Modes: bandwidth and are mostly suited for dc High-Speed: 128kSPS, 106dB SNR measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the High-Resolution: 52kSPS, 111dB SNR

offset and drift specifications are significantly weaker Low-Power: 52kSPS, 31mW/ch

than respective industrial counterparts. The ADS1274 Low-Speed: 10kSPS, 7mW/ch

and ADS1278 combine these types of converters,

• Linear Phase Digital Filter allowing high-precision industrial measurement with

• SPI™ or Frame-Sync Serial Interface excellent dc and ac specifications.

• Low Sampling Aperture Error The high-order, chopper-stabilized modulator

• Modulator Output Option (digital filter bypass) achieves very low drift with low in-band noise. The onboard decimation filter suppresses modulator and

• Analog Supply: 5V

signal out-of-band noise. These ADCs provide a

• Digital Core: 1.8V usable signal bandwidth up to 90% of the Nyquist

• I/O Supply: 1.8V to 3.3V rate with less than 0.005dB of ripple.

Four operating modes allow for optimization of speed, resolution, and power. All operations are controlled

• Vibration/Modal Analysis directly by pins; there are no registers to program.

• Multi-Channel Data Acquisition The devices are fully specified over the extended industrial range (–40°C to +105°C) and are available

• Acoustics/Dynamic Strain Gauges

in an HTQFP-64 PowerPAD™ package.

• Pressure Sensors

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments, Inc.

SPI is a trademark of Motorola, Inc.

(2)

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site atwww.ti.com.

Over operating free-air temperature range unless otherwise noted⁽¹⁾

ADS1274, ADS1278 UNIT

AVDD to AGND –0.3 to +6.0 V

DVDD, IOVDD to DGND –0.3 to +3.6 V

AGND to DGND –0.3 to +0.3 V

Momentary 100 mA

Input current

Continuous 10 mA

Analog input to AGND –0.3 to AVDD + 0.3 V

Digital input or output to DGND –0.3 to DVDD + 0.3 V

Maximum junction temperature +150 °C

ADS1274 –40 to +125 °C

Operating temperature range

ADS1278 –40 to +105 °C

Storage temperature range –60 to +150 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Inputs

Full-scale input voltage (FSR⁽¹⁾) VIN= (AINP – AINN) ±VREF V

Absolute input voltage AINP or AINN to AGND AGND – 0.1 AVDD + 0.1 V

Common-mode input voltage (VCM) VCM= (AINP + AINN)/2 2.5 V

High-Speed mode 14 kΩ

High-Resolution mode 14 kΩ

Differential input impedance

Low-Power mode 28 kΩ

Low-Speed mode 140 kΩ

DC Performance

Resolution No missing codes 24 Bits

fCLK= 32.768MHz⁽²⁾ 128,000 SPS

High-Speed mode

fCLK= 27MHz 105,469 SPS⁽³⁾

Data rate (f_DATA) High-Resolution mode 52,734 SPS

Low-Power mode 52,734 SPS

Low-Speed mode 10,547 SPS

Integral nonlinearity (INL)⁽⁴⁾ Differential input, V_CM= 2.5V ±0.0003 ±0.0012 % FSR⁽¹⁾

Offset error 0.25 2 mV

Offset drift 0.8 µV/°C

Gain error 0.1 0.5 % FSR

Gain drift 1.3 ppm/°C

High-Speed mode Shorted input 8.5 16 µV, rms

High-Resolution mode Shorted input 5.5 12 µV, rms

Noise

Low-Power mode Shorted input 8.5 16 µV, rms

Low-Speed mode Shorted input 8.0 16 µV, rms

Common-mode rejection fCM= 60Hz 90 108 dB

AVDD 80 dB

Power-supply rejection DVDD fPS= 60Hz 85 dB

IOVDD 105 dB

V_COMoutput voltage No load AVDD/2 V

(1) FSR = full-scale range = 2V_REF.

(2) fCLK= 32.768MHz max for High-Speed mode, and 27MHz max for all other modes. When fCLK> 27MHz, operation is limited to Frame-Sync mode and V_REF≤2.6V.

(3) SPS = samples per second.

(4) Best fit method.

(4)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC Performance

Crosstalk f = 1kHz, –0.5dBFS⁽⁵⁾ –107 dB

High-Speed mode 101 106 dB

VREF= 2.5V 103 110 dB

High-Resolution mode Signal-to-noise ratio (SNR)⁽⁶⁾

VREF= 3V 111 dB

(unweighted)

Low-Power mode 101 106 dB

Low-Speed mode 101 107 dB

Total harmonic distortion (THD)⁽⁷⁾ VIN= 1kHz, –0.5dBFS –108 –96 dB

Spurious-free dynamic range 109 dB

Passband ripple ±0.005 dB

Passband 0.453 fDATA Hz

–3dB Bandwidth 0.49 fDATA Hz

High-Resolution mode 95 dB

Stop band attenuation

All other modes 100

High-Resolution mode 0.547 fDATA 127.453 fDATA Hz

Stop band

All other modes 0.547 f_DATA 63.453 f_DATA Hz

High-Resolution mode 39/fDATA s

Group delay

All other modes 38/fDATA s

High-Resolution mode Complete settling 78/f_DATA s

Settling time (latency)

All other modes Complete settling 76/fDATA s

Voltage Reference Inputs

fCLK= 27MHz 0.5 2.5 3.1 V

Reference input voltage (V_REF)

(V_REF= VREFP – VREFN) f_CLK= 32.768MHz⁽⁸⁾ 0.5 2.5 2.6 V

Negative reference input (VREFN) AGND – 0.1 AGND + 0.1 V

Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1 V

High-Speed mode 1.3 kΩ

High-Resolution mode 1.3 kΩ

ADS1274

Reference Input impedance Low-Power mode 2.6 kΩ

Low-Speed mode 13 kΩ

High-Speed mode 0.65 kΩ

High-Resolution mode 0.65 kΩ

ADS1278

Reference Input impedance Low-Power mode 1.3 kΩ

Low-Speed mode 6.5 kΩ

Digital Input/Output (IOVDD = 1.8V to 3.6V)

VIH 0.7 IOVDD IOVDD V

V_IL DGND 0.3 IOVDD V

VOH IOH= 4mA 0.8 IOVDD IOVDD V

VOL IOL= 4mA DGND 0.2 IOVDD V

Input leakage 0 < V_{IN DIGITAL}< IOVDD ±10 µA

High-Speed mode⁽⁸⁾ 0.1 32.768 MHz

Master clock rate (fCLK)

Other modes 0.1 27 MHz

(5) Worst-case channel crosstalk between one or more channels.

(6) Minimum SNR is ensured by the limit of theDC noisespecification.

(7) THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.

(8) f_CLK= 32.768MHz max for High-Speed mode, and 27MHz max for all other modes. When f_CLK> 27MHz, operation is limited to Frame-Sync mode and VREF≤2.6V.

(5)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply

AVDD 4.75 5 5.25 V

DVDD 1.65 1.8 1.95 V

IOVDD 1.65 3.6 V

AVDD 1 10 µA

Power-down current DVDD 1 15 µA

IOVDD 1 10 µA

ADS1274

High-Speed mode 50 75 mA

High-Resolution mode 50 75 mA

ADS1274

AVDD current Low-Power mode 23 35 mA

Low-Speed mode 5 9 mA

ADS1274

DVDD current Low-Power mode 10 15 mA

Low-Speed mode 2.5 4.5 mA

High-Speed mode 0.15 0.5 mA

High-Resolution mode 0.075 0.3 mA

ADS1274

IOVDD current Low-Power mode 0.075 0.3 mA

High-Speed mode 285 420 mW

High-Resolution mode 275 410 mW

ADS1274

Power dissipation Low-Power mode 135 210 mW

Low-Speed mode 30 55 mW

ADS1278

ADS1278

AVDD current Low-Power mode 44 64 mA

Low-Speed mode 9 14 mA

ADS1278

DVDD current Low-Power mode 12 17 mA

High-Speed mode 0.25 1 mA

High-Resolution mode 0.125 0.5 mA

ADS1278

IOVDD current Low-Power mode 0.125 0.5 mA

High-Speed mode 530 785 mW

High-Resolution mode 515 765 mW

ADS1278

Power dissipation Low-Power mode 245 355 mW

Low-Speed mode 50 80 mW

(6)

AINN7⁽¹⁾ AINP7⁽¹⁾ AINN8⁽¹⁾ AINP8⁽¹⁾

AVDD AGND PWDN1 PWDN2 PWDN3 PWDN4 PWDN5⁽¹⁾ PWDN6⁽¹⁾ PWDN7⁽¹⁾ PWDN8⁽¹⁾

MODE0 MODE1 AINP2

AINN2 AINP1 AINN1 AVDD AGND DGND TEST0 TEST1 CLKDIV SYNC DIN DOUT8⁽¹⁾ DOUT7⁽¹⁾ DOUT6⁽¹⁾ DOUT5⁽¹⁾

AINN3 AINP3 AINN4 AINP4 AVDD AGND VREFN VREFP VCOM AGND AVDD AINP5(1) AINN6(1) AINP6(1)

AINN5(1)

DOUT4 DOUT3 DOUT2 DOUT1 DGND IOVDD IOVDD DGNDDGND DVDD CLK SCLK DRDY/FSYNC FORMAT2 FORMAT1 FORMAT0

ADS1274/ADS1278

AGND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

(PowerPAD Outline)

NOTE: (1)Boldfacepin names indicate additional pins for the ADS1278; see pin descriptions.

ADS1274/ADS1278 PIN DESCRIPTIONS

PIN

NAME NO. FUNCTION DESCRIPTION

6, 43, 54,

AGND Analog ground Analog ground; connect to DGND using a single plane.

58, 59

AINP1 3 Analog input

AINP3 63 Analog input ADS1278: AINP[8:1] Positive analog input, channels 8 through 1.

AINP5 51 Analog input ADS1274: AINP[8:5] Connected to internal ESD rails. The inputs may float.

AINP[4:1] Positive analog input, channels 4 through 1.

(7)

AINN1 4 Analog input

AINN3 64 Analog input ADS1278: AINN[8:1] Negative analog input, channels 8 through 1.

AINN5 52 Analog input ADS1274: AINN[8:5] Connected to internal ESD rails. The inputs may float.

AINN[4:1] Negative analog input, channels 4 through 1.

AVDD 5, 44, 53, 60 Analog power supply Analog power supply (4.75V to 5.25V).

VCOM 55 Analog output AVDD/2 Unbuffered voltage output.

VREFN 57 Analog input Negative reference input.

VREFP 56 Analog input Positive reference input.

CLK 27 Digital input Master clock input.

CLK input divider control: 1 = 32.768MHz (High-Speed mode only) / 27MHz

CLKDIV 10 Digital input

0 = 13.5MHz (low-power) / 5.4MHz (low-speed) DGND 7, 21, 24, 25 Digital ground Digital ground power supply.

DIN 12 Digital input Daisy-chain data input.

DOUT1 20 Digital output DOUT1 is TDM data output (TDM mode).

DOUT2 19 Digital output

DOUT3 18 Digital output ADS1278: DOUT[8:1] Data output for channels 8 through 1.

DOUT5 16 Digital output ADS1274: DOUT[8:5] Internally connected to active circuitry; outputs are driven.

DOUT6 15 Digital output DOUT[4:1] Data output for channels 4 through 1.

DRDY/ 29 Digital input/output Frame-Sync protocol: frame clock input; SPI protocol: data ready output.

FSYNC

DVDD 26 Digital power supply Digital core power supply (+1.65V to +1.95V).

FORMAT0 32 Digital input

FORMAT[2:0] Selects Frame-Sync/SPI protocol, TDM/discrete data outputs,

fixed/dynamic position TDM data, and modulator mode/normal operating mode.

IOVDD 22, 23 Digital power supply I/O power supply (+1.65V to +3.6V).

MODE0 34 Digital input MODE[1:0] Selects High-Speed, High-Resolution, Low-Power, or Low-Speed mode operation.

MODE1 33 Digital input

PWDN1 42 Digital input

PWDN3 40 Digital input ADS1278: PWDN[8:1] Power-down control for channels 8 through 1.

PWDN5 38 Digital input ADS1274: PWDN[8:5] must = 0V.

PWDN[4:1] Power-down control for channels 4 through 1.

SCLK 28 Digital input/output Serial clock input, Modulator clock output.

SYNC 11 Digital input Synchronize input (all channels).

TEST0 8 Digital input TEST[1:0] Test mode select: 00 = Normal operation 01 = Do not use 10 = Do not use 11 = Test mode

TEST1 9 Digital input

(8)

CLK

t_CPW

t_SD t_SCLK

t_DIST

t_DOHD t_SPW

Bit 23 (MSB) Bit 22 Bit 21

t_SPW t_DOPD

t_CD

t_DS

t_MSBPD

t_DIHD

· · ·

t_CONV DRDY

SCLK

DOUT

DIN

TIMING REQUIREMENTS: SPI FORMAT

For T_A= –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.

SYMBOL PARAMETER MIN TYP MAX UNIT

tCLK CLK period (1/fCLK)⁽¹⁾ 37 10,000 ns

tCPW CLK positive or negative pulse width 15 ns

t_CONV Conversion period (1/f_DATA)⁽²⁾ 256 2560 t_CLK

t_CD⁽³⁾ Falling edge of CLK to falling edge of DRDY 22 ns

t_DS⁽³⁾ Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 t_CLK

tMSBPD DRDY falling edge to DOUT MSB valid (propagation delay) 16 ns

tSD(3) Falling edge of SCLK to rising edge of DRDY 18 ns

t_SCLK⁽⁴⁾ SCLK period 1 t_CLK

t_SPW SCLK positive or negative pulse width 0.4 t_CLK

t_DOHD^{(3) (5)} SCLK falling edge to new DOUT invalid (hold time) 10 ns

tDOPD(3) SCLK falling edge to new DOUT valid (propagation delay) 32 ns

tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns

t_DIHD⁽⁵⁾ Old DIN valid to falling edge of SCLK (hold time) 6 ns

(1) f_CLK= 27MHz maximum.

(2) Depends on MODE[1:0] and CLKDIV selection. SeeTable 6(fCLK/fDATA).

(3) Load on DRDY and DOUT = 20pF.

(4) For best performance, limit fSCLK/fCLKto ratios of 1, 1/2, 1/4, 1/8, etc.

(5) t_DOHD(DOUT hold time) and t_DIHD(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns.

(9)

SCLK FSYNC

DOUT

DIN

t_DOHD t_FPW

t_SCLK t_SPW t_SF

t_SPW

t_FRAME

t_FPW t_FS

t_DIHD t_MSBPD

t_DIST

Bit 23 (MSB) Bit 22 Bit 21

t_DOPD CLK

t_CPW t_CS

TIMING REQUIREMENTS: FRAME-SYNC FORMAT

For T_A= –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.

SYMBOL PARAMETER MIN TYP MAX UNIT

All modes 37 10,000 ns

tCLK CLK period (1/fCLK)

High-Speed mode only 30.5 ns

t_CPW CLK positive or negative pulse width 12 ns

t_CS Falling edge of CLK to falling edge of SCLK –0.25 0.25 t_CLK

t_FRAME Frame period (1/f_DATA)⁽¹⁾ 256 2560 t_CLK

tFPW FSYNC positive or negative pulse width 1 tSCLK

tFS Rising edge of FSYNC to rising edge of SCLK 5 ns

t_SF Rising edge of SCLK to rising edge of FSYNC 5 ns

t_SCLK SCLK period⁽²⁾ 1 t_CLK

t_SPW SCLK positive or negative pulse width 0.4 t_CLK

tDOHD(3) (4) SCLK falling edge to old DOUT invalid (hold time) 10 ns

tDOPD(4) SCLK falling edge to new DOUT valid (propagation delay) 31 ns

t_MSBPD FSYNC rising edge to DOUT MSB valid (propagation delay) 31 ns

t_DIST New DIN valid to falling edge of SCLK (setup time) 6 ns

t_DIHD⁽³⁾ Old DIN valid to falling edge of SCLK (hold time) 6 ns

(1) Depends on MODE[1:0] and CLKDIV selection. SeeTable 6(f_CLK/f_DATA).

(2) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of f_CLK.

(3) t_DOHD(DOUT hold time) and t_DIHD(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns.

(4) Load on DOUT = 20pF.

(10)

10 100 1k Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140 -160

Amplitude(dB)

10k 100k

High-Speed Mode fIN= 1kHz, 0.5dBFS- 32,768 Points

10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80

-100 -120 -140 -160

Amplitude(dB)

10k 100k

High-Speed Mode fIN= 1kHz, 20dBFS- 32,768 Points

1 10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140 -160 -180

Amplitude(dB)

10k 100k

High-Speed Mode Shorted Input 262,144 Points

-35 -28 -21 -14 -7 0 7 14 21 28 35

Output ( V)m 25k

20k

15k

10k

5k

0

NumberofOccurrences

High-Speed Mode Shorted Input 262,144 Points

10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80

-100 -120 -140 -160

Amplitude(dB)

10k 100k

High-Resolution Mode fIN= 1kHz, 0.5dBFS- 32,768 Points

10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80

-100 -120 -140 -160

Amplitude(dB)

10k 100k

High-Resolution Mode fIN= 1kHz, 20dBFS- 32,768 Points

OUTPUT SPECTRUM OUTPUT SPECTRUM

Figure 1. Figure 2.

OUTPUT SPECTRUM NOISE HISTOGRAM

(11)

1 10 100 1k Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140 -160 -180

Amplitude(dB)

10k 100k

High-Resolution Mode Shorted Input 262,144 Points

-24.5 -21.0 -17.5 -14.0 -10.5 -7.0 -3.5 0 3.5 7.0 10.5 14.0 17.5 21.0 24.5

Output ( V)m 25k

20k

15k

10k

5k

0

NumberofOccurrences

High-Resolution Mode Shorted Input 262,144 Points

10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80

-100 -120

-140 -160

Amplitude(dB)

10k 100k

Low-Power Mode fIN= 1kHz, 0.5dBFS- 32,768 Points

10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80

-100 -120

-140 -160

Amplitude(dB)

10k 100k

Low-Power Mode fIN= 1kHz, 20dBFS- 32,768 Points

1 10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140 -160 -180

Amplitude(dB)

10k 100k

Low-Power Mode Shorted Input 262,144 Points

-37 -32 -26 -21 -16 -11 -5 0 5 11 16 21 26 32 37

Output ( V)m 25k

20k

15k

10k

5k

0

NumberofOccurrences

Low-Power Mode Shorted Input 262,144 Points

(12)

1 10 100 Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140 -160

Amplitude(dB)

1k 10k

Low-Speed Mode fIN= 100Hz, 0.5dBFS- 32,768 Points

1 10 100

Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140 -160

Amplitude(dB)

1k 10k

Low-Speed Mode fIN= 100Hz, 20dBFS- 32,768 Points

0.1 1 10 100

Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140 -160 -180

Amplitude(dB)

1k 10k

Low-Speed Mode Shorted Input 262,144 Points

-35 -28 -21 -14 -7 0 7 14 21 28 35

Output ( V)m 25k

20k

15k

10k

5k

0

NumberofOccurrences

Low-Speed Mode Shorted Input 262,144 Points

10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140

THD,THD+N(dB)

10k 100k

High-Speed Mode VIN= 0.5dBFS-

THD+N

THD

-120 -100 -80 -60 -40 Input Amplitude (dBFS) 0

-20 -40 -60 -80 -100 -120 -140

THD,THD+N(dB)

-20 0 High-Speed Mode

f_IN= 1kHz

THD+N

THD

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

vs FREQUENCY vs INPUT AMPLITUDE

(13)

10 100 1k Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140

THD,THD+N(dB)

10k 100k

High-Resolution Mode VIN= 0.5dBFS-

THD+N

THD

-20 -40 -60 -80 -100 -120 -140

THD,THD+N(dB)

-20 0 High-Resolution Mode

f_IN= 1kHz

THD+N THD

10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140

THD,THD+N(dB)

10k 100k

Low-Power Mode VIN= 0.5dBFS-

THD+N

THD

-20

-40

-60

-80

-100

-120

-140

THD,THD+N(dB)

-20 0 Low-Power Mode

f_IN= 1kHz

THD+N THD

10 100 1k

Frequency (Hz) 0

-20 -40 -60 -80 -100 -120 -140

THD,THD+N(dB)

10k Low-Speed Mode

VIN= 0.5dBFS-

THD+N THD

-20

-40

-60

-80

-100

-120

-140

THD,THD+N(dB)

-20 0 Low-Speed Mode

THD+N THD

(14)

-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 Offset Drift (mV/°C)

400 350 300 250 200 150 100 50 0

NumberofOccurrences

Multi-lot data based on 20 C intervals over the° range 40 C to +105- ° °C.

-15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Gain Drift (ppm/ C)° 900

800 700 600 500 400 300 200 100 0

NumberofOccurrences

25 units based on 20 C intervals over the° range 40 C to +105- ° °C.

Outliers: T < 20 C- °

0 50 100 150 200 250 300 350

Time (s) 40

30 20 10 0 -10 -20 -30 -40

NormalizedOffset(V)m

400 ADS1278 Low-Speed Mode

ADS1278 High-Speed and High-Resolution Modes ADS1278 Low-Power Mode

ADS1274 High-Speed and High-Resolution Modes

0 50 100 150 200 250 300 350

Time (s) 40

30 20 10 0

-10 -20

-30 -40

NormalizedGainError(ppm)

400 ADS1274/78 High-Speed and High-Resolution Modes

ADS1278 Low-Speed Mode ADS1278 Low-Power Mode

-1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000

Offset ( V)m 40

35 30 25 20 15 10 5 0

NumberofOccurrences

High-Speed Mode 25 Units

-4000 -3600 -3200 -2800 -2400 -2000 -1600 -1200 -800 -400 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000

Gain Error (ppm) 90

80 70 60 50 40 30 20 10 0

NumberofOccurrences

OFFSET DRIFT HISTOGRAM GAIN DRIFT HISTOGRAM

OFFSET WARMUP DRIFT RESPONSE BAND GAIN WARMUP DRIFT RESPONSE BAND

OFFSET ERROR HISTOGRAM GAIN ERROR HISTOGRAM

(15)

-1500 -1400 -1300 -1200 -1100 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0

100 200 300 400 500 600 700 800 900

1000 1100 1200 1300 1400 1500 Channel Gain Match (ppm)

100 90 80 70 60 50 40 30 20 10 0

NumberofOccurrences

-1500 -1400 -1300 -1200 -1100 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0

100 200 300 400 500 600 700 800 900

1000 1100 1200 1300 1400 1500 Channel Offset Match ( V)m

70 60 50 40 30 20 10 0

NumberofOccurrences

-40 -20 0 20 40 60 80 100

Temperature ( C)° 100

50 0 -50 -100 -150 -200 -250 -300

NormalizedOffset(V)m

300 250 200 150 100 50 0 -50 -100

NormalizedGainError(ppm)

120 125 Offset

Gain

2.40 2.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60

VCOM Voltage Output (V) 20

18 16 14 12 10 8 6 4 2 0

NumberofOccurrences

AVDD = 5V 25 Units, No Load

-40 -20 0 20 40 60 80 100

Temperature (°C) 1.36

1.34 1.32 1.30 1.28 1.26 1.24 1.22

ReferenceInputImpedance(k)W

13.6 13.4 13.2 13.0 12.8 12.6 12.4 12.2

120 125 High-Speed and

High-Resolution Modes

Low-Speed Mode

50 100 150 200 250 300 350 400 450 500 550 600 650 700

Sampling Match Error (ps) 40

35 30 25 20 15 10 5 0

NumberofOccurrences

30 units over 3 production lots, inter-channel combinations.

ADS1278 ADS1274

ADS1278

CHANNEL GAIN MATCH HISTOGRAM CHANNEL OFFSET MATCH HISTOGRAM

OFFSET AND GAIN

vs TEMPERATURE VCOM VOLTAGE OUTPUT HISTOGRAM

ADS1274/ADS1278 ADS1274 REFERENCE INPUT DIFFERENTIAL SAMPLING MATCH ERROR HISTOGRAM IMPEDANCE vs TEMPERATURE

(16)

-40 -20 0 20 40 60 80 100 Temperature (°C)

0.68 0.67 0.66 0.65 0.64 0.63 0.62

6.8 6.7 6.6 6.5 6.4 6.3 6.2

120 125 High-Speed and

Low-Speed Mode

-40 -20 0 20 40 60 80 100

Temperature (°C) 14.4

14.3 14.2 14.1 14.0 13.9 13.8 13.7 13.6 13.5 13.4

AnalogInputImpedance(k)W

28.8 28.6 28.4 28.2 28.0 27.8 27.6 27.4 27.2 27.0 26.8

120 125 Low-Power Mode High-Speed and

-40 -20 0 20 40 60 80 100

Temperature (°C) 155

150 145 140 135 130 125 120 115

120 125 Low-Speed Mode

-40 -20 0 20 40 60 80 100

Temperature ( C)° 10

8

6

4

2

0

INL(ppmofFSR)

120 125

-2.0 -2.5

V_IN(V) 10

8 6 4 2 0 -2 -4 -6 -8 -10

LinearityError(ppm)

-1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 T = 40 C- °

T = +25 C°

T = +125 C°

T = +105 C°

0

V_REF(V) 14

12 10 8 6 4 2 0

Linearity(ppm)

-100 -104 -108 -112 -116 -120 -124 -128

THD(dB)

3.5 THD

0.5 1.0 1.5 2.0 2.5 3.0

Linearity

THD: f_IN= 1kHz, V_IN= 0.5dBFS-

SeeElectrical CharacteristicsforV_REFOperating Range.

ADS1278 REFERENCE INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL IMPEDANCE

IMPEDANCE vs TEMPERATURE vs TEMPERATURE

ANALOG INPUT DIFFERENTIAL IMPEDANCE INTEGRAL NONLINEARITY

vs TEMPERATURE vs TEMPERATURE

LINEARITY ERROR LINEARITY AND TOTAL HARMONIC DISTORTION

vs INPUT LEVEL vs REFERENCE VOLTAGE