Interfacing the DP8422A to an Asynchronous Port B in a Dual 68020 System

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Interfacing the DP8422A to an Asynchronous Port B in a Dual 68020 System AN-617

National Semiconductor Application Note 617 Chris Koehle July 1989

Interfacing the DP8422A to an Asynchronous Port B in a Dual 68020 System


This application note explains interfacing the DP8422A DRAM controller to two 68020 microprocessors that are running at the same frequency, but asynchronously to each other. This application note is a supplement to AN-539 (In- terfacing the DP8420A/21A/22A to the 68020) and is in- tended to show synchronization logic and timing require- ments for a Port B CPU that is running asynchronous to the DP8422A. It is assumed that the reader is already familiar with the 68020 access cycles and the DP8422A modes of operation.


This design shows all of the logic necessary to interface an asynchronous 20 MHz 68020 to the DP8422A Port B control inputs. This design is a worst case example and includes some logic that would not be needed in slower systems (i.e., 68000@10 MHz). In our example, a Port B access begins when the asynchronous 68020 places a valid address on the address bus and asserts the address strobe, AS. In or- der to synchronize this signal to the DP8422A, it is run through two DQ flip-flops, which are clocked by Port A’s input clock. The first DQ is run by an inverted clock in order to reduce the synchronization delay time by (/2T. Once AREQB is asserted, the access request is latched on the DP8422A and an access will start. If GRANTB is asserted, signaling Port B control of the access port, and a refresh is not in progress, the DP8422A will assert an access RAS.

The transfer acknowledge signal, ATACKB is also asserted from AREQB asserting (or from the same edge of clock that starts RAS for a delayed access). AREQB also runs through two DQ flip-flops before being input as DSACK to the 68020B. These two flip-flops serve a dual purpose, one be- ing to synchronize the ATACKB signal to the 68020B clock, and the other is to provide 1T of delay for the ATACKB signal.

Once DSACK is sampled as asserted by the 68020, AS is negated, signifying an end to the present access. AS negat- ing is used to negate the DSACK input by presetting the two flip-flops connected to this input. This is done to guarantee that the 68020B DSACK signal is negated prior to the next access request being valid. The ‘‘Q’’ output that is connect- ed to the DSACK input on the 68020 is also run through 1(/2T of delay (2DQ’s) before it is used to preset the flip-flop that drives AREQB. The preset is used to negate the AREQB signal and to hold it negated for the required AREQB negated pulse width as specified by the DP8422A.

AS is also used to preset this signal so AREQB does not get asserted in instances where there are not back-to-back ac- cesses. The 1(/2T delay is used so that the AREQB signal is negated after data is sampled by the 68020. In addition to the parameters calculated in AN-539, these additional pa- rameters are included to show how the synchronizing logic still meets the necessary setup times required by the sys- tem (the ‘‘$’’ symbol refers to a DP8422A parameter, and the ‘‘Ý’’ symbol refers to a 68020 parameter).

$101 AREQB Asserted Setup to CLK High (The DP8422A-25 needs 7 ns) e1 TCPbtPHL(74F74 DQ Flip-Flop) e50 nsb8 ns

e42 ns

Ý47a DSACK Asserted Setup Time (68020 needs 5 ns) (/2TCPbtPHL(74F74) 25 nsb8 ns 17 ns

AS negated pulse width guarantees the DP8422A meets AREQB negated pulse width ($117) through the preset of DQ flip-flop which is connected to AREQB input.

C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.


TL/F/10441 – 1

FIGURE 1. Dual Porting with the DP8422A with an Asynchronous Port B

Synchronizing Logic for a Dual 68020 Asynchronous System

TL/F/10441 – 2



68020 Asynchronous Port BÐSingle Access

TL/F/10441 – 3

Back to Back Accesses where DQ Catches AS Negated Pulse in between Accesses

TL/F/10441 – 4



AN-617 Interfacing the DP8422A to an Asynchronous Port B in a Dual 68020 System

Back-to-Back Accesses where DQÝ1 Does Not Catch AS Negated Pulse in between Accesses

TL/F/10441 – 5



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