aDS SCIENTIFIC

SOS 910 COMPUTER Logic Layouts, Current and History

SOS 900551C

April 1966

This publication supersedes SDS 900551A dated April 1965 and SDS 900551 B dated December 1964.

aDS

SCIENTIFIC DATA SYSTEMS. 1649 Seventeenth Street. Santa Monica, Calif . • (213) 871-0960

@1964, 1965, 1966, Scientific Data Systems, Inc.

$21.00

PREFACE

This printing of the 910 logic layouts applies to all SDS 910 Computers.

1. Current sheets are the latest revisions. (See page 137.) 2. History sheets start with Revision L. (See page 137.)

3. Revis ion sheets may be suppl ied separately and should be collated by the user.

910 DIRECTORY

87 Add 42 Ji10 122 X-y Selector 34 PI, P2 70 Ts, Ts* 19 W4W5W6w9+

86 Ag 97 Ji10 (scope) 123 X-V Selector 35 P3 thru P6 97 Ts (scope) W9 WI0 Wl1)

86 An 42 (0'0 Tp 10) 124 X-V Selector 36 P7 thru PIO 67 (Tsm) 22 W5

97 An (scope) 89 (0'0 T 24 Go) 125 Z Driver 37 Pll thru P14 15 (Tsm) 32 rNSW6 W9)

84 Anr 42 (0'0 T24 Ia Go) 126 Z Driver

,

68 (An C23), (An C23) 72 Ji13 127 Z Driver 45 Ql, Q2, Q2* 73 (Tsm) 25 W7, W8

85 Ar 73 (0'3 T24) 128 Sense Amp & Discriminator 46 Q3 32 (Tsw) 30 W9

84 Aw 72 Ji14 thru ~ 129 Sense Amp & Discriminator 13 (Q3 Q4) 73 (Tsw) 19 [W9 WIO Wll W12

65 Go 130 Sense Amp & Discriminator 46 Q4 73 (Tsy)

....

86 Bn 131 Sense Amp & Discriminator 47 Q5, Q6 48 (Ts (Jif4 + Sk + PO) ) 21 WIO

97 Bn (scope) 62 [Ha It light] 132 Sense Amp & Discriminator 48 TO, TO*, TO 31 Wll

81 Bnr 65 Ht 133 Selector Control 51 Rf 48 TO (scope) 26 W12

81 Br

53 Ia 134 Selector Control -20 Rp 54 (TO Ex) 18 W13, W14

81 Bw

91 Ib 135 Current & Voltage Regulator 92 Rt 49 (T5 - TO)

72 Buc = (Eom C10 CTI)

67 Int 68 Rti 49 (T9)

83 Xn

93 Ioc 77 N5, N6, N7, N8 28 R1 49 (T1O)

97 Xn (scope)

74 CdO thru Cd 11 78 N9., NI0 27 R2 49 (T21 + T22)

75 Cd12 thru Cd23 99 Ip 1 thru Ip4

79 Nll, N12 24 R3, R4 50 (T22 - T17), (T22 - T17)* 82 Xnr

67 Ir 82 Xw

61 C9, C9*

99 Is 1 thru 154 80 N13, N14 27 R5 50 (T23)

87 Xz

62 Cp

94 Ix 28

",120

63 Cs, CSI

19 [l1w] , [12w] 39 Oc 16 RTM 48 T24, T24*

90 Cxi 95 Of 73 Sc 91 Yx

61 Cxm, Cxm^l 55 Rf* 42 Oxc 52 Sk 16 Wc 87 Yz

96 Cz 66 Sks 26 We 30 Y9

64 CO 10

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55

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33 Zwp

50 (C3 + C4) 12 (ll) thru (l7) 92 (01 02 03 04) 73 Sxc, Sxn, Sxp 16 (:Nf (:NO + W9) )

56 C4 thru C7 11 (l8) thru (114) 90 (01 02 03 00 la) 93 Sys 21 Wh 33 Zwl thru Zw6

57 C8 thru C11 90 (01 02 0405 06 ~) 76 51 thru 54 32 Whs :lAN";~" fit'.~)

100 <kDthru@

58 C12 thru C15 1 Mc 92 (01 03 04 J(16) 77 S5 thru S8 23 Wn

59 C16 thru C19

ru*

60 C20 thru C23 14 (Mg Qi) = Rw 93 (01 ~ Rf Dc C23 T24) 79 S11, S12 14 Wr

1011

60 C23* (C23) 14 (M~ Q2) 80 S13, S14 16 Ws thru Pin locator

97 C23 (scope) .13 Mr 43 02 91 Wx 112

62 C24 1 Ms 42 (0203 001~ 49 Tp*, Tp, Tp 17 Ww

13 Mwt 42 (02 + 03 + Ji10 + Ia) 48 (Tp End $I) 31 WO 113 Modu Ie locator

88 Dc 1 Mxc 97 (Tp End Sk Go Mo) 22 W4 114 Module locator

2 MoMg 44 03 (scope) 32 (:N4) =

32 Ecw 3 Ml thru M4 92 (03 04 Ts) 50 (ip l24), (ip T24)* (Il4W5 W6 W9 + 136 DIRECTORY

97 Ecw (scope) 4 M5 thru M8 92 (ro 0406 F21s)

69 En 5 M9 thru M12

TAB IDENTIFICATION:

19 (En+@) 6 M13thruM16 44 04, 05, 06

39 End 7 M 17 thru M20 ^I l"'/z,·;.:,r<:"J

Tab 1 l ^{' - -... ~} ; ... ,.!..-"--'

93 Eom 8 M21 thru M24 71 (06 Ji12) Memory, M Register I"~ [: IS

54 Ex Tab 2 W Buffer

'.: 'Nhs, ) Tab 3 Centra I Processor

40 Fl Memory Section 100 Pal thru Pa8

Tab 4 Pin # 1 Module locators

91 (FT F3 Is) 115 Address Decode 62 [Parity Er light]

Tab 5 Memory Decoding, Regu lators

[To @

42 (FT ~ Ts) 116 Address Decode 100 Photo Reader

Tab 6 Manual Index (137) & Plug Modules ^{i'3E H}

91 ( (F lInt) (T22 - T17) 117 X-V Selector 90 Pin

71 (Fl ~ 15 Wp + 01 ~4 118 X-V Selector 38 Pg Tab 7 I/O Signal Identification

Tab 8 Power Wiring and Parts Complement 2.s-

[

+ 02.96 + 03 J(16) 119 X-V Selector 99 Priority interrupt

41 F2 120 X-V Selector 68 Pot 1, Pot 2 Tab 9 High-Speed Interlace Modification

40 ^{F3 121} X-V Selector 98 PO Tab 10 Reference Schematics

25

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