L L adaptec, inc.

L

L

I

_L....;

adaptec, inc.

ACB-4000

OEM Manual

ACB-4000

5%" Winchester Disk Controller OEM Manual

March, 1984

@ adoptee, ine. •

Additional copies of this manual. or other Adaptec literature may be obtained from:

Adaptec, Inc.

Literature Department 580 Cottonwood Drive Milpitas, CA 95035

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without prior written consent of Adaptec, Inc.

1.0 Introduction

1.1 Basic Description ... 1-1 1.2 Feature Set ... 1-2 2.0 Physical Specifications

2.1 Size ... 2-1

2.2 Power Requirements ... 2-1 2.3 Environmental Limits ... 2-1 3.0 Host and Drive Interfaces

3.1 Host Adapter Interface ... 3-1

3.1.1 Host Adapter Interface-Physical ... 3-1 3.1.2 Host Adapter Interface-Electrical ... 3-3 3.2 Disk Drive Interface ... 3-4

3.2.1 Disk Drive Interface-Physical . , ... 3-4 3.2.2 Disk Drive Interface-Electrical ... 3-6 4.0 Host Interface Protocol

4.1 ACB-4000 SCSI Features ... 4-1 4.2 General Description of SCSI ... 4-1 4.3 Bus Signals ... , .... 4-2

4.3.1 Busy (BSY) ... 4-2 4.3.2 Select (SEL) ... 4-2

4.3.3 Control/Data (C/O) '" . , ... 4-2 4.3.4 Input/Output (I/O) ... , ... ,. 4-2 4.3.5 Message (MSG) ... 4-2 4.3.6 Request (REQ) ... 4-2 4.3.7 Acknowledge (ACK) .. , .. ' ... 4-2 4.3.8 Attention (ATN) '" . , ... 4-2 4.3.9 Reset (RSl1 ... 4-2

4.3.10 Data Bus (DB: 7-0) ... 4-3 4.4 Bus Phases ... 4-3

4.4.1 Bus Free Phase . , ... 4-3 4.4.2 Selection Phase ... , ... 4-3

4.4.3 Information Transfer Phases ... 4-4 4.4.3.1 Command Phase ... 4-5 4.4.3.2 Data Phase ... 4-5 4.4.3.3 Status Phase ... 4-5 4.4.3.4 Message Phase ... 4-5

4.4.4 Signal Restrictions Between Phases ... 4-6 4.5 Bus Conditions ... 4-6

4.5.1 Attention Condition ... 4-6 4.5.2 Reset Condition ... 4-6 4.6 Phase Sequencing ... 4-7 4.7 Timing ... 4-7

4.7.1 Aborted Selection Time ... 4-7 4.7.2 Bus Clear Delay ... 4-7

4.7.3 Bus Set Delay ... 4-7 4.7.4 Bus Settle Delay ... 4-7 4.7.5 Cable Skew ... 4-7 4.7.6 Deskew Delay ... 4-7

4.7.7 REQ Response Timeout ... 4-8 4.7.8 Reset Hold Time ... 4-8

4.7.9 Select Timeout ... 4-8 5.0 Message Specification

5.1 Message System ... 5-1

5.1.1 Single Byte Message ... 5-1

5.1.1.1 Command Complete ... 5-1 6.0 Command Specifications

6.1 General Description ... 6-1

6.2 Command and Status Structure ... 6-1

6.2.1 Command Descriptor Block (CDB) ... 6-1 6.2.2 Class Code ... 6-2

6.2.3 Operation Code ... 6-2 6.2.4 Logical Unit Number ... 6-2 6.2.5 Command Specific Bits ... 6-2 6.2.6 Logical Block Address ... 6-2 6.2.7 Number of Blocks ... 6-3 6.2.8 Control Byte ... 6-3 6.3 Command Descriptions " ... 6-3

6.3.1 Class 00 Command Descriptions ... 6-3 6.3.1.1 Test Unit Ready ... 6-4

6.3.1.2 Rezero Unit ... 6-4 6,3.1.3 Request Sense, . , , ... ^{I •} 6-4 6.3.1.4 Format Unit ... 6-4 6.3.1.5 Read ... 6-8 6.3.1.6 Write ... 6-8 6.3.1.7 Seek ... 6-9 6.3.1.8 Trans!ate ... 6~10

6.3.1.9 Write Data Buffer ... 6-11 6.3.1.10 Read Data Buffer ... . 6-11 6.3.1.11 Mode Select ... 6-12 6.3.1.12 Mode Sense ... 6-15 6.3.1.13 Start/Stop Unit ... 6-15 6.3.1.14 Receive Diagnostic ... 6-16 6.3.1.15 Send Diagnostic ... 6-17

6.3.2 Class 01 Command Descriptions ... 6-19 6.3.2.1 Read Capacity ... 6-19

6.3.2.2 Read ... 6-20 6.3.2.3 Write ... 6-20

6.3.2.4 Write and Verify ... 6-21 6.3.2.5 Verify ... 6-22

6.3.2.6 Search Data Equal ... 6-22

6.4 Completion Status Byte ... 6-26 6.4.1 Request Sense ... 6-26 6.5 Sense Bytes ... 6-27

Appendices

A Installation Section and Introduction to SASI/SCSI 1.0 Introduction ... A-1

2.0 The Bus and Interface ... A-1 3.0 Setting Up the Hardware ... A-2 4.0 Talking to the Controller ... A-3 5.0 SASI/SCSI Handshaking ... A-4 6.0 . The Commands ... A-5

7.0 A Sample Format Sequence ... A-6 8.0 Sample Driver Routine ... A-7

B Optional Command Recognition in the ACB-4000 1.0 Using the Expanded Command Set ... B-1

1.1 Definition ... B-1

1.2 Use of Optional Command Set ... B-1

ACB-4000 511i' Hard Disk

The Adaptec ACB-4000 5%" Hard Disk Controller board interfaces ST506-type Winches- ter disk drives to any ANSI X3T9.2 SCSI (Small Computer System Interface) standard host adapter interface.

BASIC DESCRIPTION 1.1

The ACB-4000 controller supports standard SCSI features plus extensions and controls two Seagate ST-506/412 or equivalent Winchester drives.

FEATURE SET 1.2

1) The ACB-4000 utilizing a 1K, dual-ported buffer, eliminates the need for sector interleaving. This allows the host to read a track of data in a single revolution of the disk.

2) The ACB-4000 auto-configures to any size, previously formatted, 5%" drive, eliminating the need for host initialization of the controller for various drive types.

3) The ACB-4000 handles defects on a sector level transparent to the host. Since no alternate tracks are used, lengthy seeks to alternate tracks are eliminated and disk capacity is maximized.

4) The ACB-4000 guarantees maximum data integrity by utilizing a 32-bit ECC on both the data and ID fields. The computer-generated code provides correction of single-burst 8-bit errors.

5) The ACB-4000 offers variable sector lengths from 256 bytes to 1K bytes. The sector length is programmed at format time.

6) The ACB-4000 supports a high-speed data search where a programmed full sector bit pattern can be compared for an equal or unequal bit pattern within a range of sectors.

SIZE 2.1

The ACB-4000 is designed to fit in the form factor of a standard 5%" drive, The physical dimensions of the controller are as follows:

Length:

Width:

Height:

Weight:

7.75 inches (19.7 cm) 5.75 inches (14,6 cm) 0.75 inches ( 1,9 cm) 1 pound, with packaging

POWER REQUIREMENTS 2.2

+5 VDC ± 5% at 1,5 amps (max,) +12 VDC ± 10% at 300 mA (max,)

Power is applied through J3, 4-pin AMP connector, The recommended mating con- nector is AMP PIN 1-480424-0, J3 pins are numbered as shown in Figure 2-1,

+12V +12V RETURN +5V RETURN

+5V Figure 2-1.

Connector J3 Pin Assignments

ENVIRONMENTAL LIMITS 2.3

Temperature FIC Humidity (non-cond,) Altitude, ft,

Operating 32/0 to 131/55 10% to 95%

Sea Level to 10,000

Storage -40/-40 to 167175 10% to 95%

Sea Level to 20,000

HOST ADAPTER INTERFACE 3.1

The Adaptec ACB-4000 controller interfaces to a host adapter according to the proposed ANSI X3T9.2 Standard (SCSI). The data bus is a bidirectional 8-bit parallel interface.

3.1.1

HOST ADAPTER INTERFACE-PHYSICAL

A 50-pin flat ribbon connector is provided at J4. The 3M PIN 3425-3000 cable connec- tor is recommended.

Single ended drivers and receivers allow a maximum cable length of 20 feet (6 meters) between the host adapter and the controller. All signals are low true. All odd pins are grounded. Figure 3-1 shows the SCSI bus pin assignments.

Figure 3-2.

ACB-4000 Board '"

"!

on tI

...

,..:

.50

, . . - - - 5.75 ±.02 ---t~

o--r::w:::J-o ^U28

o--wu-o

oC401

o-C47_

~~ o~

a 0 0 0

I

~ TP11

~

^Ul0

af

^{U25 U26}

~ ~I

^{~ U27}

~ ~ ~~!

1~

^CR601

^{9 ~}

C26 a 0 U12 o--r::w--o

C27 Ul1

1=

1 ~91 ~ ^I ~ I~ ~ ~~ ~ 1~ ~

PU~:R s.

^{Jl 20 2 JO}

0

²⁰

0 0 0 0 0 0 0 0 0 0 '-o~o~o~o~o-o-o-o-o~o aooooooooo aooooooooo

3.1.2 HOST ADAPTER INTERFACE-ELECTRICAL

All signals are low true and use open collector drivers terminated with 220 ohms to +5 volts (nominal) and 330 ohms to ground at each end of the cable.

Each signal driven by the controller has the following output characteristics:

True (Signal Assertion) = 0.0 to 0.4 VDC @ 48 mA (max.) False (Signal Non-Assertion) = 2.5 to 5.25 VDC

Adaptec controllers use a 7438 open collector driver to meet this specification.

Each signal from the host to the controller must have the following characteristics:

True (Signal Assertion) = 0.0 to 0.8 VDC @ .4 mA (max.) False (Signal Non-Assertion) = 2.0 to 5.25 VDC

A 74LS14 receiver with hystereSiS meets this specification.

Figure 3-3 shows an example of proper bus termination.

CONTROLLER TYPICAL HOST ADAPTOR +5

7438

74LS240

20 FEET (6 METERS) MAXIMUM

330[1

220[1

330[1

74LS14

Figure 3-3.

Host Adapter Bus Termination

3.2 DISK DRIVE INTERFACE

The ACB-4000 controller complies with the standard ST-506/412 interface.

A system interconnect diagram is shown in Figure 3-4. Board layout for connector positioning is shown in Figure 3-2.

J4

J2

34 PIN CONTROL/DATA EDGE

JO

20 PIN SOCKET

/ / ' l _ _ _ _ 3""- DATA

"~---~/

DRIVE 1

HOST INTERFACE 50 PIN SOCKET

J1 20 PIN SOCKET

DC POWER

Figure 3-4.

System Interconnect Diagram

J3 4 PIN SOCKET

3.2.1

DISK DRIVE INTERFACE-PHYSICAL

DRIVE 2

J2 is a 34-pin edge connector to which all drive control lines are daisy chained.

Maximum cable length is 20 feet (6 meters). The suggested mating connector for this ribbon cable is 3M PIN 3402-0000.

The pins are numbered 1 through 34 with the even pins located on the component side of the controller board. Pin 2 is the pin closest to the power connector (J6). Table 3-1 shows pin assignments for connector J2.

JO and J1 are the radial data connectors to each disk drive. Maximum cable length should not exceed 20 feet (6 meters). Suggested mating sockets for these connectors is 3M PIN 3421 Series. Table 3-2 shows pin assignments for connectors JO and J1.

GND RTN SIGNAL

PIN PIN

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

GND RTN SIGNAL

PIN PIN

2 1

4 3

6 5

8 7

9,10

12 11

13 14

16 15

17 18

20 19

SIGNAL NAME Reduced Write Current/Head Select 2³ Head Select 22

Write Gate Seek Complete Track 0

Write Fault Head Select 2°

Reserved Head Select 21 Index

Ready Step

Drive Select 1 Drive Select 2 Drive Select 3 Drive Select 4 Direction In

SIGNAL NAME Drive Selected

Reserved

Res~rved

Reserved Reserved GND

MFM Write Data MFM Write Data GND

MFM Read Data MFM Read Data GND

Table 3-1.

J2 Connector Pin Assignment

Table 3-2.

JO and J1 Connector Pin Assignment

Figure 3-5.

Control Driver/

Receiver lines

Figure 3-6.

ACB-4000 Data Receiver/Driver

3.2.2 DISK DRIVE INTERFACE-ELECTRICAL

The last physical drive on the control bus daisy chain must be terminated with a resistor pack provided by the drive manufacturer. The control signal driver/receiver electrical specifications are shown in Figure 3-5.

+5

7438 20 FT(MAXJ

The control signals are specified at:

True = 0.0 VDC to 0.4 VDC @ I = -48 mA (max.)

False = 2.5 VDC to 5.25 VDC @ I = +250

f-lA.

(open collector)

The read and write MFM data lines are differential signals, present on connectors JO and J1. The Adaptec receiver/driver pairs meet the required RS-422 specifications.

Figure 3-6 shows these lines for the ACB-4000.

CONTROLLER 100ft DISK

-L>---l ^[>-

MC3487 1000

-<J~J _ _ ^<11----

75175

ACB-4000 SCSI FEATURES 4.1

This section describes in detail the SCSI protocol with the extensions which are imple- mented in the Adaptec ACB-4000 controller. The extended functions of the SCSI standard not supported by the ACB-4000 are command chaining and disconnection and reconnection. When designing systems for the ACB-4000 series, you may go directly from the "bus free" phase to the "selection" phase in the protocol description.

GENERAL DESCRIPTION OF SCSI 4.2

This system interface provides an efficient method of communication between com- puters and peripheral I/O devices. The eight-port, daisy-chained bus defined by this specification supports the following features:

o Single or multiple host system.

o Multiple peripheral devices and device types.

o Bus contention resolution through arbitration on a prioritized basis.

o Asynchronous data transfer at up to 1.5 MBytes/sec.

o Host-to-host communication.

Communication on the bus is allowed between two bus ports at a time. A maximum of eight bus ports are allowed. Each port is attached to a device (e.g. controller or host adapter).

When two devices communicate with each other on the bus, one acts as an INITIATOR and the other acts as a TARGET. The TARGET (typically a controller) executes the operation. A device will usually have a fixed role as an INITIATOR or TARGET, but some devices may be able to assume either role.

An INITIATOR may address up to two peripheral I/O devices that are connected to an ACB-4000 TARGET. The TARGET will provide a ''virtual controller" for each of these devices, appearing to the system as two separate controller/device pairs.

Certain bus functions are assigned to the INITIATOR and certain bus functions are assigned to the TARGET. The INITIATOR may arbitrate for the bus and select a particular TARGET. The TARGET may request the transfer of COMMAND, DATA, STATUS or other information on the bus.

Data transfers on the bus are asynchronous and follow a defined REQUEST/

ACKNOWLEDGE handshake protocol. One eight-bit byte of information may be trans- ferred with each handshake.

4.3 BUS SIGNALS

The nine control signals and eight data signals are described below:

4.3.1 BUSY (BSY)

BSY is an "or-tied" signal which indicates that the bus is in use.

4.3.2 SELECT (SEL)

SEL is an "or-tied" signal used by an INITIATOR to select a TARGET or by a TARGET to reselect an INITIATOR.

4.3.3 CONTROUDATA (C/O)

c/o

is a TARGET-driven signal to indicate whether CONTROL or DATA information is on the data bus. Assertion indicates CONTROL.

4.3.4 INPUT/OUTPUT (I/O)

I/O is a TARGET-driven Signal which controls the direction of data movement on the data bus relative to an INITIATOR. Assertion indicates INPUT to the INITIATOR.

4.3.5 MESSAGE (MSG)

MSG is a TARGET-driven Signal indicating the MESSAGE phase.

4.3.6 REQUEST (REQ)

REQ is a TARGET-driven signal indicating a request for a REQ/ACK data transfer handshake.

4.3.7 ACKNOWLEDGE (ACK)

ACK is an INITIATOR-driven signal indicating acknowledgment of a REQ/ACK data transfer handshake.

4.3.8 ATTENTION (ATN)

ATN is an INITIATOR-driven signal indicating the ATTENTION condition.

4.3.9 RESET (RST)

RST is an "or-tied" signal indicating the RESET condition.

4.3.10 DATA BUS (DB: 7-0)

Eight data bit signals comprise the DATA BUS. DB(7) is the most significant bit and has the highest priority during arbitration. Significance and priority decrease with decreas- ing bit number.

Each of the eight data signals DB(7) through DB(O) is uniquely assigned as a TARGET or INITIATOR bus address (i.e., DEVICE ID) which is normally assigned and "strapped" in the device during system configuration. In order to obtain the bus during arbitration, a device asserts its assigned data bit (DEVICE ID) and leaves the other data bits in the passive (non-driven) state.

BUS PHASES 4.4

The SCSI bus implemented by the ACB-4000 has six distinct operational phases and cannot be in more than one phase simultaneously.

D BUS FREE Phase

D SELECTION Phase

D COMMAND Phase }

D DATA Phase Information Transfer Phases

D STATUS Phase

D MESSAGE Phase

4.4.1 BUS FREE PHASE

The BUS FREE phase, indicating that the bus is available for use, is invoked by the deassertion and passive release of all bus signals. All active devices must deassert and passively release all bus signals (within a BUS CLEAR DELAY) after deassertion of BSY and SEL.

Devices sense BUS FREE when both SEL and BSYare not asserted (simultaneously within a DESKEW DELAY) and the RESET condition is not active.

4.4.2 SELECTION PHASE

The SELECTION phase allows an INITIATOR to select a TARGET. The INITIATOR waits a minimum of BUS SETTLE DELAY (after detecting BUS FREE) before driving the DATA bus with the TARGET ID and (optionally) its own ID. After two DESKEW DELAYS, the INITIATOR can assert SEL.

On detecting the simUltaneous condition (within one DESKEW DELAY) of SEL its own ID asserted, and BSYand I/O not asserted, the selected TARGET examines the DATA bus for the INITIATOR ID and responds by asserting BSY.

After a minimum of two DESKEW DELAYS (following the detection of BSY from the TARGET), the INITIATOR deasserts SEL and may change the DATA signals.

Table 4-1.

Information Transfer Phase

The INITIATOR may "time our' the SELECTION phase by deasserting the ID bits on the bus. If (after a SELECTION RESPONSE TIME plus two DESKEW DELAYS) BSY has not been asserted, SEL may be deasserted. The TARGET must drive BSY within a SELECTION RESPONSE TIME of detecting SEL and its own ID.

4.4.3 INFORMATION TRANSFER PHASES

The COMMAND, DATA, STATUS and MESSAGE phases are all used to transfer data or control information through the DATA bus. The actual contents of the information is beyond the scope of this section.

The C/D, I/O and MSG signals are used to differentiate the various INFORMATION TRANS- FER phases. Note that these signals are not valid without REQ asserted. See Table 4-1.

SIGNAL

MSG C/D

0 0

0 0

0 1

0 1

1 0

1 0

1 1

1 1

Notes:

o ⁼ Signal Deassertion 1 = Signal Assertion INIT = Initiator TARG = Target

DIRECTION OF I/O PHASE NAME INFORMATION TRANSFER

0 DATA OUT Phase (lNIT to TARG) 1 DATA IN Phase (INIT from TARG) 0 COMMAND Phase (INIT to TARG) 1 STATUS Phase (INIT from TARG) 0 Not Used

1 Not Used

0 MSG OUT Phase (INIT to TARG) 1 MSG IN Phase (INIT from TARG)

The INFORMATION TRANSFER phases use the REQ/ACK handshake to control data trans- fer. Each REQ/ACK allows the transfer of one byte of data. The handshake starts with the TARGET asserting the REQ signal. The INITIATOR responds by asserting the ACK signal. The TARGET then deasserts the REQ signal and the INITIATOR responds by deasserting the ACK signal.

With I/O signal asserted, data will be input to the INITIATOR from the TARGET. The TARGET must ensure that valid data is available on the bus (at the INITIATOR port) before the assertion of REQ at the INITIATOR port. The data remains valid until the assertion of ACK by the INITIATOR. The TARGET should compensate for cable skew and the skew of its own drivers.

With the I/O signal not asserted, data will be output from the INITIATOR to the TARGET.

The INITIATOR must ensure valid data on the bus (at the TARGET port) before the assertion of ACK on the bus. The INITIATOR should compensate for cable skew and the skew of its own drivers. Valid data remains on the bus until the TARGET deasserts REQ.

During each INFORMATION TRANSFER phase, the BSY line remains asserted, the SEL line remains deasserted, and the TARGET will continuously envelop the REQ/ACK hand- shake(s) with the C/D, I/O and MSG signals in such a manner that these control signals are valid for a BUS SETILE DELAY before the REQ of the first handshake and remain valid until the deassertion of ACK at the end of the last handshake.

4.4.3.1 COMMAND PHASE

The COMMAND phase allows the TARGET to obtain command information from the INITIATOR.

The TARGET asserts the C/D signal and deasserts the I/O and MSG signals during the REQ/ACK handshake(s) of this phase.

4.4.3.2 DATA PHASE

The DATA phase includes both the DATA IN phase and the DATA OUT phase.

The DATA IN phase allows the TARGET to INPUT data to the INITIATOR. The TARGET asserts the I/O signal and deasserts the C/D and MSG signals during the REQ/ACK handshake(s) of this phase.

The DATA OUT phase allows the TARGET to obtain OUTPUT data from the INITIATOR. The TARGET deasserts the C/D, I/O and MSG signals during the REQ/ACK handshake(s) of this phase.

4.4.3.3 STATUS PHASE

The STATUS phase allows the TARGET to send status information to the INITIATOR.

The TARGET asserts C/D and I/O and it deasserts the MSG signal during the REQ/ACK

handshake(s) of this phase. .

4.4.3.4 MESSAGE PHASE

The MESSAGE phase includes the MESSAGE IN and MESSAGE OUT phases.

The MESSAGE IN phase allows the TARGET to INPUT a message to the INITIATOR. The TARGET asserts C/D, 110 and MSG during the REQ/ACK handshake(s) of this phase.

The MESSAGE OUT phase allows the TARGET to obtain a message from the INITIATOR.

The TARGET may invoke this phase only in response to the ATIENTION condition cre- ated by the INITIATOR. In response to the ATTENTION condition, the TARGET asserts C/D and MSG and deasserts the I/O signal during the REQ/ACK handshake(s) of this phase.

4.4.4 SIGNAL RESTRICTIONS BETWEEN PHASES

When the BUS is between phases, the following restrictions apply to the bus signals:

D The BSY, SEL REQ and ACK signals may not change.

D The C/D, I/O, MSG and DATA signals may change.

D The ATN and RST signals may change as defined under the descriptions for the ATTENTION and RESET conditions.

4.5 BUS CONDITIONS

The bus has two asynchronous conditions: the ATTENTION condition and the RESET condition. These conditions cause certain BUS DEVICE actions and can alter the bus phase sequence.

4.5.1 ATTENTION CONDITION

ATTENTION allows the INITIATOR to signal the TARGET of a waiting IDENTIFY message. The TARGET may access the message by invoking a MESSAGE OUT phase.

The INITIATOR creates the ATTENTION condition by asserting ATN at any time except during the BUS FREE phase. The TARGET responds when ready with the MESSAGE OUT phase. The INITIATOR keeps ATN asserted if more than one byte is to be transferred.

The INITIATOR can deassert the ATN signal during the RESET condition, during a BUS FREE phase, or while the REQ signal is asserted and before the ACK signal is asserted during the last REQ/ACK handshake of a MESSAGE OUT phase.

4.5.2 RESET CONDITION

The RESET condition, created by the assertion of RST, is used to immediately clear all devices from the bus and to reset these devices and their associated equipment as defined in the controller specification.

RESET can occur at any time and takes precedence over all other phases and condi- tions. Any device (whether active or not) can invoke the RESET condition. On RESET, all devices will immediately (within a BUS CLEAR DELAY) deassert and passively release all bus signals except RST itself. A TARGET capable of continuing an I/O operation after being interrupted by RESET will clear any I/O operation that has not been established.

The RESET condition stays on for at least one RESET HOLD TIME. During the RESET condition, no bus signal except RST can be assumed valid.

Regardless of the prior bus phase, the bus resets to a BUS FREE phase (and then starts a normal phase sequence) following a RESET condition.

PHASE SEQUENCING 4.6

Phases are used on the bus in a prescribed sequence. In all systems, the RESET condition can interrupt any phase and is always followed by the BUS FREE phase. (Any other phase can also be followed by the BUS FREE phase.)

The normal progression is from BUS FREE to SELECTION, and from SELECTION to one or more of the INFORMATION TRANSFER phases (COMMAND, DATA, STATUS or MESSAGE).

There are no restrictions on the sequencing between INFORMATION TRANSFER phases.

A phase may even follow itself (e.g., a DATA phase may be followed by another DATA phase).

TIMING 4.7

A timing chart is provided in Figure 4-1. Unless otherwise indicated, the delay time measurements for each device are calculated from signal conditions existing at the device BUS PORT. Delays in the bus cable need not be considered for these measurements.

4.7.1 ABORTED SELECTION TIME: 200 microseconds (max.)

The maximum delay allowed from SELECT detection until a BSY response is generated by a TARGET (or INITIATOR) during SELECTION. This is not SELECT TIMEOUT.

4.7.2 BUS CLEAR DELAY: 650 nanoseconds (max.)

The maximum time allowed for a device to stop driving all bus signals after the release of BSY when going to BUS FREE.

4.7.3 BUS SET DELAY: 1.1 microseconds (max.)

The maximum time from detection of BUS FREE until BSY is driven.

4.7.4 BUS SETTLE DELAY: 450 nanoseconds (min.) 4.7.5 CABLE SKEW: 10 nanoseconds (max.)

The maximum difference in propogation time allowed between any two bus signals when measured between any two bus ports.

4.7.6 DESKEW DELAY: 45 nanoseconds (min.)

4.7.7 REQ RESPONSE TIMEOUT: 250 milliseconds (min.)

The delay allowed between assertion of REQ by the TARGET and time out (due to lack of ACK from the INITIATOR).

4.7.8 RESET HOLD TIME: 25 microseconds (min.)

The minimum time during which RST is asserted. No maximum.

4.7.9 SELECT TIMEOUT: 250 milliseconds (min.)

The delay allowed for a BSY response from a TARGET before time out during SELECTION.

- -

---,

IBusyl ·BSV ^\

, ,

(Selectl ·SEL

IContlotfOatal ·CIO

,

(Input/Output I ·110

(ReqllesH 'RED

(Acknowledge) ·ACK

(AttentlOnl ·ATN ,

(Messagel ·MSG

(ReSell ·RST

IOata Bill BI7-0 p,

,

Bus Free

Note

OBm ~ ~1~~te;ltg;:~~~~~\gi~or arbltrallOn Note

DBW) = Data parity (oddl Parity IS not valid dUring arbitratIOn The use of panty IS a system optIOn Note

In a tYPical system a computer's host adapter Will act as the

Iflilldtor '(Inri an 110 deVice scontrol umt Will act as the "target'

"B us S8 I d I " eay = max lme fro m check f"b 0 us free" (BSY & SELL not assert ed) unti assertion Of "BSY" and 10 (1.8 115).

"Bus free delay" = min time bus must be left free (800 ns).

"Bus clear delay" = time to clear from bus after drop of "BSY" for bus free phase or asserting of BEL for arbitration phase by other device (800 ns).

- ''Arbitration delay" = min time from asserting "BSY" to check if arbitration is won (2.2 ..,5).

NBus settle delay" (400 ns)

I - ^~

^rr

, ,

--v

Syslems wilh "

, I no arbitration ^u

, _I start here. , ,

,

I

^,

, ,

, , , , , , ,

r0j~",';.""

, ,

, ,

, , , ,

, ,

: {jff~'

,

I :

, , ,

:

, ,

Arbitration lD's

Initiator tries to get bus

ARBITRATION

~

^PHASE

=l

~

After inotlalor sees

l

~~~~~~~i~~Et~' are not

~~~~~.r~b~~ ~~!S a delay' and a max of

~~~~r~~t ,~~~y'~~~~ts

own ID on the data bus,

After the "arbitration

l

delay," the initiator checks the data bus and clears Itself from arbit~ation if a higher

~~~~r~;~II~ ~nB:~~ bus

If "SEL' IS asserted

l

during arbitration by another deVice, the Imtiator Will immedia- tely, clear itself from arbitration (Within

"bus clear delay" time)

II the mitlator deter- mmes that ItS own 10 IS the highest asserted, then It may n~t change any lines until after waiting two "bus sellie delays 'I

,

_,

, , _, ,,'

, , _{, ,}

, ,

i i

,

,

D

Initiator 10 & target ID

lSICMD~ ^---"

Initiator has bus and selects target J~~~~~3~~;~ts" imtiator

SELECTION COMMAND PHASE

~

^PHASE

==;

~

lnol'ator asserls data bus

K== L

Target asserls

L

^~Ith desired,target's ID &

Its own (lflillatorllD

~~!ei~:t~t~~~~~~~·~~~~'~"

L

'·CfD and does not assert 1/0" or

"MSG"

L

l

l L

l

The selected target s~~s the conditIOn of "BSV not asserted while "SEL" & Its lDare asserted, The target

~'%~VO~dS by assertlflg

After t~o "deskew delays' the imtlator drops "SEL and may change the data lines

Note: Alter imtiator drops

"SEL" it is the only bus deVice that can assert

"ACK" and ATN land Ihe data 1mes if ··110" is not asserted (mdicatlflg out- put from imtiator)

Note: After t~e target se~s

~h~~~lf~'~~~ ~!~~c~r~:: ^IS

can assert "BSV," "C/D,"

"1/0," "MSG," "RED,"land the data lines if '·'/0"

IS asserted (indicating input to the initiator)

After a "bus

L

setlle delay" tar- get asserts "REO Initiator puts data (command) on

L

Ihe bus and asserts

"ACK"

Target walts a

"deskew delay

L

takes the data &

then drops ·'REO "

Note: To maintain ANSI

L

compatibilIty. Initiator

should deskew the data Initiator drops '-ACK' & data,

~ote: In systems in ~hlch the arbitration phase is not

(~j~~~~n'~§~l~~~~r~~~~~~~~lsi~~\ehc~~ ~!IPSU! free phase

"bus settle ,delay," Th~n the Initiator ass~rts the data bus With the deSired target's ID and ItS own (initiator) ID Then after two "deskew delays" the imtiator asserts "SEL"

T~en as described a,bove. the target resp-onds With "BSV" and the Initiator drops '·SEL .

~ ^{, ,}

n ^,

,

I:';:MD byle

.,

'r

.,

'r

,

---,

I,f Read peripheral deViC~: , ,

---

JJ

~~~I;p~i;:a~d~v~e-

--- ---

'~I~f-'--

, ,

f "

r--r.. --

^I--..

IT~1

^{, ,}

, _I , , ,

,

_I

, _, , ,

, ,

_, ^, _,

,

I i

First data (read peripheral) I Last data (read peripheral)

' r - "'\ Valid ~I r -)~ahdl

~~ Val, ,

First data (wrtte peripheral) t ^{Last data} (~rite peripheral) Target "requests" data

transfer with mitlator A

I

~DTAPHASE~

bRead peropheral dev,ce

L

Target asserts "110" and does not assert "CID' or

L

"MSG: Targel then watts atle~st a "bus sell Ie delay" befofe asserting "REO' Target also put,s data on the bust at least

L

"deskew delay' before the assertion of "REO"

Imtlator takes data and asserts "ACK,"

L ^{Data are} no longer guaranteed valid LTarget drops 'REO,

L Imtlator drops "ACK "

~

Write peropheral deVICe

LTarget asserts '·REO" a!1d does not assert --110," --C/O" or "MSG,'

L

Initiator asserts '·ACK" & data

L Target walls a "deskew delay," then takes the data & then drops "REO,"

L

Dala are no longer guaranleed valid

L Initiator drops "ACK"

- -

-,.. ^r---

Deskew Delay Tlme·(45 ns) This delay allows for 45 ns receiver skew and 10 ns cable skew

:'

, , ^{, ,}

, , ,

,

,,\

,

, , , , , ,

: :

, _,

; ,

, I ^,

..<~ ,

"'It::"status byte Status byte Target

"requests"

Initiator to take status

STATUS

L ~ (~~~,~~ ~

status)

!~~~~,It~r,eo"s

l

anddoesnOI

assert "MSG ' After a "bus settle delay,' It asserts

"RED,"

Target also asserts data

l

{slatuslat least a "des-

~:fu~ee!,~!O

IMlatortakes

L

data and asserts

"ACK,"

Data are no long-

L

~~p'~aranleed

!~E~~~' ^drops

L

L

Initialordrops

"ACK" in response to the drop WRED,"

Note: In theory, more than one status byte could be sent,

-

"Reset hold time" = 25.,..5

"SEL" response timeout -250 rns

"MAX cable skew" .. 10 ns

I

I

^{, ,}

~

^{, ,}

^{f~- -}

, ,

, ,

, ,

, , , , ,

_, I

i

^{, ,}

I : _:

, ,

, ,

, ,

: I

}~).

^{, , : ,----}

~essage ^{byte :}

Target "requests'

Imllator to take available

message MESSAGE

r ,,:::~., ~

!~~~et r/~~,rts

""". ~

~

^fREE; BUS

~ T~:::~;OPS

L

ifldlcate that the bus IS f~ee

l

'MSG 'After 'hussettle d~l(ly II am'ls"RED.' T.lIQct also ao,serts data

l

tmcssagelat least a "des-

~:~,d:I~~D "

Nole Message

~enl here

L

(I)uld Indicate wmmanddone Illterrupt llullator takes

L

^{rt ..} lIaandasserts 'ACK Oat a are no long-

l

~:lR~aranteed l~f~et drops Thp.I' Iflitlator

L

orO\lS"ACK"in n'sponsetothe dIOIJO' "AEO "

Nlltc In theory mOle than once lIIessage byte lould be sent

Target and Iflltlator get off the bus (within "bus clear delay"

tlmelm preparation for a sub- sequent arbitration

Note ThiS IS an example of a tYPical bus seQuence, It IS nOI a definition of bus protocol

Figure 4-1.

Bus Timing Chort

MESSAGE SYSTEM 5.1

The message system allows communication between an INITIATOR and TARGET for purposes of physical path management. This section defines the messages and lists their assigned codes (in HEX),

Normally, the first message sent by the INITIATOR after the SELECTION phase is IDENTIFY (to establish the physical path), After reselection, the TARGETs first message is also IDENTIFY, Under certain conditions, an INITIATOR may send SELECTIVE RESET or BUS DEVICE RESET as the first message,

The ACB-4000 controller only supports the COMMAND COMPLETE message and does not respond to the ATN signal except during selection, Only COMMAND COMPLETE need be implemented in an ACB-4000 environment,

5,1.1 SINGLE BYTE MESSAGE

5.1.1.1 COMMAND COMPLETE

(DOH)

This code is sent from the TARGET at the completion of command execution (or at the end of a series of linked commands) to direct the INITIATOR to indicate COMMAND COMPLETE to the host.

This message does not imply good ending status; STATUS must be checked to deter- mine end conditions.

GENERAL DESCRIPTION 6.1

This section of the Adaptec Controller Manual details the SCSI command set and related information.

By defining a fixed block structure using a simple, logical address scheme, the 1/0 interface can support device independence. In addition, by including the logical block address as a component of the command structure, physical requirements (such as SEEK) can be imbedded within the basic READ and WRITE requests.

This interface, despite its simplicity, is capable of providing the high level of perfor- mance required in multi-host/multi-task environments. Powerful functions, such as search, are included to enhance random access applications, and single-command, multi-block transfers are included to simplify sequential operations.

COMMAND AND STATUS STRUCTURE 6.2

6.2.1 COMMAND DESCRIPTOR BLOCK (CDB)

An 1/0 request to a device is made by passing a Command Descriptor Block (CDB) to the controller. The first byte of the CDB is the command class and operation code. The remaining bytes specify the Logical Unit Number (LUN), block starting address, control byte and the number of blocks to transfer. Commands are categorized into two classes supported by Adaptec controllers.

The SCSI Command Descriptor Block contains reserved bytes (for future SCSI defini- tion). The ACB-4000 requires that those bytes be set to zero or the command will be rejected.

Class 0: 6-Byte commands.

Class 1: 10-Byte commands.

Figures 6-1 and 6-2 show typical command descriptor block formats.

BIT

BYTE 7 6 5 4 3 2

00 01 02 03 04 05*

'Control Byte

1

o

Figure 6-1.

Class 00 Commands (6-Byte Commands)

Figure 6-2.

Class 01 Commands

(10 Byte Extended Block Address)

BIT

BYTE 7 6 5 4 3 2 1

o

00 01 02 03 04 05 06 07 08 09*

'Control Byte

6.2.2 CLASS CODE

The class code can be 0 to 7, but only 0 and 1 are used at this time.

6.2.3 OPERATION CODE

The operation code for each class allows 32 commands (00 to 1FH)' 6.2.4 LOGICAL UNIT NUMBER

Logical unit numbers allow eight devices per controller. The ACB-4000 accomodates two devices per controller which must be devices 0 and 1.

6.2.5 COMMAND SPECIFIC BITS

Byte 01, bits 01-04 specify options which depend upon the particular command.

6.2.6 LOGICAL BLOCK ADDRESS

Class 0 commands contain 21-bit starting block addresses while class 1 supports 32-bit block addressing.

The "block" concept implies that the host and controller have "preset' the number of bytes of data to be transferred. You will note that the concept of sector is replaced by block.

6.2.7 NUMBER OF BLOCKS

A variable number of blocks may be transferred under a single command. Class 00 commands may transfer up to 256 blocks, while class 01 commands may transfer up to 64K blocks. A zero block number count defaults to the maximum value.

6.2.8 CONTROL BYTE

All bits in the control byte are reseNed and must be zero.

COMMAND DESCRIPTIONS 6.3

The following section describes and details the complete command set for the ACB-4000 controller.

6.3.1 CLASS 00 COMMAND DESCRIPTIONS The following is a series of command descriptions.

OP CODe COMMAND OP CODe COMMAND

00 TEST UNIT READY OF TRANSLATE

OJ REZERO UNIT 13 WRITE BUFFER

03 REQUEST SENSE 14 READ BUFFER

04 FORMAT UNIT 15 MODE SELECT

08 READ 1A MODE SENSE

OA WRITE 1B START/STOP UNIT

OB SEEK 1C RECEIVE DIAGNOSTIC

1D SEND DIAGNOSTIC

Table 6-1.

Class 00

Command Code Summary

Figure.6-3.

TEST UNIT READY Command

Figure 6-4.

REZEROUNIT Command

6.3.1.1 TEST UNIT READY (OOH)

BIT

BYTE 7 6 5 4 3 ^{2 1}

a

00 01 02 03 04 05*

'Control Byte

This command returns zero status if the requested unit is powered on and ready. If not ready, a check condition will be set in the status byte. Possible errors are Drive Not Ready (04H) and Write Fault (03H).

6.3.1.2 REZERO UNIT (01H)

BIT

BYTE 7 6 5 4 3 2 1

o

00 01 02 03 04 05*

'Control Byte

This command sets the selected drive to track zero and then sends completion status.

Possible error returns are No Seek Complete (02H), Drive Not Ready (04H) and No Track Zero (06H).

6.3.1.3 REQUEST SENSE (03H)

See Paragraph 6.4 for details of the complete command as well as a complete discussion of returned sense data.

6.3.1.4 FORMAT UNIT (04H)

The control unit will write from index to index aliiD and data fields with a block size as specified by an immediately previous MODE SELECT (15H) command. If no MODE SELECT (15H) command has been executed, the previous data block size will be used.

On unformatted disks or those whose format is determined bad (sense byte error code 1CH returned following a READ), a MODE SELECT (15H) command is required prior to the format command. Data fields are completely written with 6CH unless otherwise specified in the format command.

BIT

BYTE 7 6 5 4 3 2 ¹

o

00 01

02

03 04 05*

'Control Byte

Byte 01 is used to indicate if a list of defect locations is appended and whether a unique fill character is required. Bit 04 indicates that defect data is appended to the command block and must be set if a defect list is present. The defect list must be less than 1024 bytes long. Bit 03 is defined by the SCSI specification as an indication that the defect list appended is a complete list. This bit must also be set if a defect list is present. Bit 02 indicates that bits 01 and 00 are used to further define the format and must be set if either a defect list or unique fill character is present. Bit 01 indicates that a unique fill character is contained in the next byte (byte 02). If this bit is not set, the ACB-4000 will fill all data fields with a "6C" data pattern. Bit 00 indicates the format of the appended defect list. This bit set to zero refers to a cylinder, head and byte format and must be used if defect data is present.

The ID fields will be interleaved as specified in bytes 3 and 4 of the CDB (byte 4, bit 0 LSB). The ACB-4000 controller does not require interleaving because of a high speed buffer control. An interleave number of 1 results in sequentiallD fields being written on the disk. Any interleave number greater than 1 and one less than the total sectors per track result in interleaved formatting. A 0 in this field will cause the default interleave factor of 2 to be used. By using an interleave of 2 or greater, the ACB-4000 can format 33 256-byte sectors per track rather than the normal 32 sectors. (See Appendix A for details.) Note that byte 3 must always be zero and also that the value in byte 4 must not exceed the number of sectors per track minus one. An error code of 24H (Bad Argument) will be returned if either of these rules is violated.

Figure 6-5.

FORMAT UNIT Command

Table 6-2, FORMAT UNIT Defect Options

The interleave number is equivalent to the number of disk revolutions required to sequentially read one track, An example of an interleave number of 3 with 256-byte sectors follows:

P - 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 F - 00 23 12 01 24 13 02 25 14 03 26 15 04 27 16 05 28 P - 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 F - 17 06 29 18 07 30 19 08 31 20 09 32 21 10 33 22 11 P = Physical sector count

F = Formatted sector locations (with interleave of 3) Table 6-2 defines the use of the data and list format bits:

FMT

DATA CMPLT BIT 02 BIT 00 DEFINITION

0 0 0 0 Format with no appended defect information,

1 1 1 0 Format with appended defect information, Defect locations are in cyl., head and byte displacement format.

The following is the format for the appended defect list. The list includes the physical coordinates of known media flaws in cylinder, head and bytes from index, All defects must be listed in ascending order,

BYTE 00

01 02 03 04 05 06 07 08 09 10 11

8N-4 to BN+3

Note:

7

See example in Appendix A.

BIT

6 5 4 3 2 1 0

If data errors are noted by the controller while reading the defect list, all formatting is stopped and a Bad Argument error (24H) is returned to the host.

If, in time, other defects appear on a drive, the contents of the entire drive should be backed up and a new format operation performed. To identify the physical locations of the troublesome blocks use the TRANSLATE command. The new defect locations must then be added and sorted into the complete list.

The defect skipping technique implemented by the ACB-4000 is at the sector level and does not require time-consuming seeks to spare track locations.

Therefore, the tracks specified by a drive manufacturer as "spare" may be utilized for data, increasing the effective capacity of the device.

Figure 6-6.

Defect Data Block

Figure 6-7.

READ Command

Figure 6-8.

WRITE Command

6.3.1.5 READ (D8H)

BIT

BYTE 7 6 5 4 3 2 1 0

00 01 02 03 04 05*

'Control Byte

This command transfers (to the host) the specified number of blocks starting at the specified logical starting block address.

The control unit will verify a valid seek address and proceed to seek to the specified starting logical block address. When the seek is complete the controller then reads the starting address data field into the buffer, checks ECC and begins DMA data transfer.

Subsequent blocks of data are transferred into the buffer in a similar manner until the block count is decremented to zero. Cylinder switching is transparent to the user. On a data ECC error, the block is reread up to five times to establish a solid error syndrome.

Only then is correction attempted. Correction is done directly into the data buffer transparent to the host.

Blocks containing uncorrectable data errors will be transferred to the host prior to an ending check status. A REQUEST sense will return an uncorrectable data error (11 H)' 6.3.1.6 WRITE (DAHl

BIT

BYTE 7 6 5 4 3 2 1

o

00 01 02 03 04 05*

'Control Byte

This command transfers (to the target device) the specified number of blocks starting at the specified logical starting block address, The controller seeks to the specified logical starting block, When the seek is complete, the controller transfers the first block into its buffer and writes its buffered data and its associated ECC into the first logical sector,

Subsequent blocks of data are transferred as available from the FIFO buffer until the block count is decremented to zero. Cylinder switching and defect skipping are transparent to the user.

The ACB-4000 also supports corresponding extended READ and WRITE commands using the class 01 CDB format.

6.3.1.7 SEEK (OBH)

BIT

BYTE 7 6 5 4 3 2 1

o

00 01 02 03 04 05*

'Control Byte

This command causes the selected drive to seek to the specified starting address. The ACB-4000 returns completion status immediately after the seek pulses are issued and head motion starts, allowing it to free the bus and accept further commands prior to actual seek completion. Note: Any command received for a unit with a seek in progress wiJl immediately complete with a command completion status of busy (bit 3 set). This is done to allow the host to use the SCSI bus to do other processing while waiting for seek complete.

The drive is stepped to the addressed track position but no ID field verification is attempted.

All ACB-4000 uses an implied seek on READ, WRITE and SEARCH commands obviating the need for issuance of SEEK commands with each operation.

Figure 6-9.

SEEK Command

Figure 6-10.

TRANSLATE Command

Figure 6-11.

TRANSLATE Data

6.3.1.8 TRANSLATE (OFH)

BIT

BYTE 7 6 5 4 3 2 1

o

00 01 02 03 04 05*

'Control Byte

This command performs a logical address to physical address translation and returns the physical location of the requested block address in a cylinder, head, bytes from index format. This data can be used to build a defect list for the FORMAT command.

Eight bytes are returned in the format of defect descriptors required by FORMAT.

If there is a data error in the ID field, an error status will be returned. It is then necessary to TRANSLATE the blocks before and after the targeted block to determine the loca- tion of the target block. The use of interleaved sectors and formatted (skipped) defects may complicate the determination of the error location.

BIT

BYTE 7 6 5 4 3 2 1 0

00 01 02 03 04 05 06 07

6.3.1.9 WRITE DATA BUFFER (13H)

BIT

BYTE 7 6 5 4 3 2 1 0

00 01 02 03 04 05*

'Control Byte

This command serves buffer RAM diagnostic purposes. The controller will fill the buffer with 1K bytes of data from the host. There is no guarantee that this data will not be overwritten by other operations initiated by other INITIATORs.

6.3.1.10 READ DATA BUFFER (14H)

BIT

BYTE 7 6 5 4 3 2 1 0

00 01 02 03 04 05*

'Control Byte

READ DATA BUFFER will pass the host 1K of data from the buffer. It is intended for RAM diagnostic purposes. The same caveat applies to this as to write buffer. In addition, although data remains in the buffer after normal data operations, the ordering of the data found there may vary.

Figure 6-12.

WRITE DATA BUFFER Command

Figure 6-13.

READ DATA BUFFER Command

Figure 6-14.

MODE SELECT Command

Figure 6-15.

MODE SELECT Parameter list

6.3.1.11 MODE SELECT (15H)

This command is used in ACB controllers to specify format parameters and should always preceed the FORMAT command. When a blown format error (code 1C) is detected due to the controller being unable to read the drive information from a drive already formatted, the user should use this command to inform the controller about the drive information. Then the drive should be backed up and reformatted.

BIT

BYTE 7 6 5 4 3 2 1 0

00 01 02 03 04 05*

'Control Byte

Byte 4 of the command specifies the number of information bytes to be passed with the command. A minimum of twelve bytes (OCH) must be specified. If drive parame- ters are being specified the count should be 22 bytes (16H).

The parameter list is four bytes long with the first three bytes reserved (zero filled). The fourth byte contains the length in bytes of the extent descriptor list; this is always eight.

(Only a single extent is supported.)

BIT

BYTE 7 6 5 4 3 2 1 0

00 01 02 03

BIT

BYTE 7 6 5 4 3 2 1 0

00 01 02 03 04 05 06 07

Byte 0 of the extent descriptor list specifies the data density of the drive. Current ACB products support only MFM and a value of 00 in this byte is required. Bytes 1, 2 and 3 are reserved and must be zero, specifying that the entire drive is to be formatted.

Bytes 5 through 7 are used to specify the data block size. The block size must not be less than 256 or exceed the RAM buffer capacity which is 1024 characters.

The extent descriptor list and following drive parameter list are a single large data block which follows the command. The ACB-4000 must be set up with a value 256, 512 or 1024 bytes.

Any violation of the above constraints will result in Check status with an error code of 24H, indicating an invalid argument in parameter data.

BIT

BYTE 7 6 5 4 3 2 1 0

00 01 02 03 04 05 06 07 08 09

Figure 6-16.

Extent Descriptor List

Figure 6-17.

Drive Parameter List