~ZiKG August 1989

~ZiKG

August 1989

Z8@Family

Design Handbook

, INTRODUCTION·

, , " " ,

Zilog.was~Qun~jrr1974.

inOSt

microprocessor

microprocessor. . .

With the unp~leled success of the ZS() CPU, the name Zilog became synonomous with quality, design integrity, and complete company support elements that , remaill integral to Zilog today.

Headquartered in Campbell, California, Zilog draws upon the services and skills of the most talented high technology minds in the industry. Zilog's Nampa, Idaho manufacturing facility, and assembly plant in the Philippines are the best of their size today. They provide Zilog customers with a tbtal solution, from engineering, to production, to worldwide on-time delivery of the growing family of Zilog microprocessor and peripheral products.

ZS Family Design Handbook Table of Contents

Z8 NMOS MCU Microcomputers Z8600

Z8601/11 Z860~/13 Z8671 Z8681 182 Z8691

MCU 2K 28-pin MCU 2K14K

MCU Protopak 2K14K

MCU with Basic/Debug Interpreter MCU ROMless

MCU ROMless Z8 CMOS MCU Microcomputers

Z86C08 Z86COO/C10/C20 Z86C11

Z86C21/C12 Z86E21 Z86C27 Z86C91

MCU 2K 18-pin MCU 4K18K 28-pin MCU4K

MCU8K MCU8KOTP

Digital Television Controller MCU ROMless

Z8 Application Notes and Technical Articles Memory Space and Register Organization App Note A Programmer's Guide to the Z8 MCU

Z8 Subroutine Library . A Comparison of MCU Units Z86xx Interrupt Request Registers Z8 Family Framing

Z8 MCU Technical Manual Super8 MCU Microcomputer

Z8800/01 Z8820 Z8822

MCU ROMless MCU8K MCU 8K Protopak

SuperS Application Notes and Technical Articles Getting Started with the Zilog Super8

Polled Asynchronous Serial Operation with the SuperS Using the Super8 Interrupt Driven Communications Using the SuperS Serial Port with DMA

Generating Sine Waves with Super8 Generating DTMF Tones with Super8

A Simple Serial Parallel Converter Using the Super8

Page

13 30 50 71

89 105 117 134 134 155 179

200 202 227 277 291 292

295

431 431 431

463 467 473 479 485 491 495

Sup~r8 Technic~1 Manual Military Electrical Specifications

Z8611 Z8681

MCU4K MCU ROMless - Packaging Information

Ordering Information

503

637 661 673 681

~ Zirm Product Specification

FEATURES

• Complete microcomputer, 2K bytes of ROM, 128 bytes of RAM, and 22 I/O lines.

• 144-byte register file, including 124 general-purpose registers, four I/O port registers, and 14 status and control registers.

• Vectored, priority interrupts for I/O and counter/timers.

• Two programmable 8-bit counter/timers, each with a 6-bit programmable prescaler.

GENERAL DESCRIPTION

The Z8600 microcomputer introduces a new level of sophistication to single-chip architecture. Compared to earlier single-chip microcomputers, the Z8600 offers: .

• faster execution

• more efficient use of memory

• more sophisticated interrupt, input/output, and bit manipulation capabilities

TIMING ( _ RESET

AND _

CONTROL OS

{

- PO.

. . - . P01

PORTO - - PO,

... P03 , ... P04 PO.

{ _ P 2 ' ... P22 PORT 2 _ _ P2, ... P24 ... P2s ... GND

Z8600 MCU

Figure 1. Pin Functions

CLOCK

PORT 3

PORT 1

Z8600Z8®

Microcomputer

August 1989

• Register Pointer so that short, fast instructions can access anyone of the nine working register groups.

• On-chip oscillator that accepts crystal or external clock drive.

.8MHz

• Single + 5 power supply-all pins TIL-compatible.

• Average instruction execution time of 2.2 J.ls,

maximum 1.5 J.ls. .

• easier system expansion

Under program control, the MCU can be tailored to the needs of its user. It can be configured as a stand-alone microcomputer with 2K bytes of internal ROM. In all configurations, a large number of pins remain available for I/O.

The MCU is offered in a 28 pin Dual-In-Line-Package (DIP) (Figu res 1 and 2).

+5V P3,

XTAL2 P3,

XTAL1 P2.

RESET P2.

os

P3. P2,

GNO P2,

PO. P"

PO, P"

PO, P"

PO, P"

PO • P"

PO • P12 .

p'.

Figure 2. Pin ASSignments

PINQESdRlPTlbNS

PS. Data Stibbe(output, active LoW).' Data Strobe is activated once fOr each memory transfer.

POcrPOs,P1o-P17. P21-P2S. P310 P3s. P36./10 Port lines (bidirectional, TIL-compatible). These 22 110 lines are grouped in four ports that can be configured under program control for 110.

ARCHITECTURE

The MCU's architecture is characterized by a flexible 110 scheme, an efficient register and address space structure, and a number of ancillary features that are helpful in many.

applications. (Figure 3).

Microcomputer applications demand powerful 110 capabilities. The MCU fulfills this with 22 pins dedicated to input and output. These lines are grouped in four ports and are configurable under software control to provide timing, status signals, and parallel 110.

(BIT PIlOGRAMMABLE) I/O

RESET; Reset (input, active Low). RESET initializes the MCV. When RESET' is deactivated, program execution begins from internal program location OOOCH:

XTAL1. XTAL2. Crysta/1, Crysta/2 (time-base input and output). These pins connect 'a parallel-resonant 8 MHz crystal to the on-chip dock oscillator and buffer.

Two basic internal address spaces are available to support this wide range of configurations: program memory-and the register file. The 144-byte random-access register file is composed of 124 general-purpose registers, four 110 port registers, and 14 control and status registers.

To unburden the program from coping with real-time problems such as countingltiming, two counter/timers with a large number of user-selectable modes are offered on-chip.

1/0 1/0

(BYTE PROGRAMMABLE)

Figure 3. Functional Block Diagram

ADDRESS SPACES

Program Memory. The 16-bit program counter addresses 2K byt~s of program memory space as shown in Figure 4.

The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain three 16-bit vectors that correspond to the three available interrupts.

Register File. The 144-byte register file includes four I/O port registers (Ro-R3), 124 general-purpose registers (R4-R127) and 14 control and status registers (R241-R255)' These registers are assigned the address locations shown in Figure 5.

2047

Instructions can access registers directly Qr indirectly with an a-bit address field. The MCU also allows short 4-bit register addressing using the Register Pointer (one of the control registers). In the 4-bit mode, the register file is divided into nine working-register groups, each occupying 16 contiguous locations (Figure 6). The Register Pointer addresses the starting location ofthe active working-register group.

Stacks. An a-bit Stack Pointer (R255) is used for the internal stack that resides within the 124 general-purpose registers (R4-R127)'

ON·CHIP

LOCATION 255 254 253 252 251 250 249 , 248 247 248 24S 244 243 242 241

127

,2 1

o

LOCATION OF FIRST BYTE OF INSTRUCTION EXECUTED AFTER RESET

INTERRUPT VECTOR (LOWER BYTE) INTERRUPT VECTOR (UPPER BYTE)

STACK POINTER (BITS 7-0) RESERVED REGISTER POINTER PROGRAM CONTROL FLAGS INTERRUPT MASK REGISTER INTERRUPT REQUEST REGISTER INTERRUPT PRIORITY REGISTER

PORTS 0-1 MODE PORT 3 MODE PORT 2 MODE TO PRESCALER TIMER/COUNTER 0

T1 PRESCALER TIMER/COUNTER 1

TIMER MODE

NOT IMPLEMENTED

GENERAL·PURPOSE REGISTERS

PORTa PORT 2 PORT 1 PORTO

Figure 5. Register File

ROM

~

11 IRQ5

10 IRQS

8 IRQ4

8 IR04

7 RESERVED

8 RESERVED

5~ ^IRQ2

4io" IR02

3 RESERVED

2 RESERVED

1 RESERVED

0 RESERVED

Figure 4. Program Memory Map

IDENTIFIERS SPL

-_{ I

I

r7r8'5 r4 I ^{00 0 0} I

THE UPPER NIBBLE OF THE REGISTER FILE AD 253 RP

FLAGS IMR IRQ IPR P01M P3M P2M PREO TO PRE1 T1 -TMR

DRESS

>---PROVIDED BY THE REGISTER POINTER SPECIF IES

P3 P2 P1 PO

THE ACTIVE WORKING-REGISTER GROUP.

--

--.

--.

--

f--.- SPECIFIED WORKING· REGISTER GROUP

..

f - - - 1 - - -

'---

Figure 6. Register Pointer 127

15 THE LOWER NIBBLE OF THE REGISTER FILE ADDRESS PROVIDED BY THE INSTRUCTION POINTS TO THE SPECIFIED REGISTER.

3

COUNTER/TIMERS

The MCU contains two 8-bit programmable counter/timers (To and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler can be driven by internal or external clock sources; however, the To prescaler is driven by the internal clock only.

The 6-bit prescalers can divide the input freqvency of the clock source by any number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request-IR04 (To) or IROs (T 1 )---,is generated.

The counters can be started, stopped, restarted to continue, or restarted from the initial value. The counters can also be programmed to stop upon reaching zero (single-pass

1/0

The MCU has 22 lines dedicated to input and output grouped in four ports. Under software control, the ports can be programmed to provide address outputs, timing, status signals, and parallel I/O. All ports have active pull-ups and pull-downs compatible with TTL loads.

Port 0 can be programmed as an I/O port.

Port 1 can be programmed as a byte I/O port.

INTERRUPTS

The MCU allows three different interrupts from three sources, the Port 3 line P31 and the two counter/timers.

These interrupts are both maskable and prioritized. The Interrupt Mask register globally or individually enables or disables the three interrupt requests. When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register.

All interrupts are vectored. When an interrupt request is granted, an interrupt machine cycle is entered. This disables CLOCK

The on-chip oscillator has a high-gain parallel-resonant amplifier for connection to a crystal or to any suitable external clock source (XTAL 1 = Input, XTAL2. = Output).

Crystal source is connected across XTAL 1 and XTAL2 using the recommended capacitors (C1 ~ 15 pI) from each pin to ground. The specifioations are as follows:

mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read any time without disturbing their value or count mode.

The clock source for T1 is user-definable and can be the internal microprocessor clock (4 MHz maximum) divided by four, or an external signal input via Port 3. The Timer Mode register configures the external timer input as an external clock (1 MHz maximum), a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. The counter/timers can be programmably cascaded by connecting the To output to the input of T1.

Port 3 line P3fi also serves as a timer output (TOUT) through which To, T 1 or the internal clock can be output.

Port 2 can be programmed independently as input or output and is always available for I/O operations. In addition, Port 2 can be configured to provide open-drain outputs.

Port 3 can be configured as I/O or control lines. P31 is a general purpose input or can be used for an external interrupt request signal (IR02). P3s and P36 are general purpose outputs. P36 is also used for timer input (TIN) and output (TOUT) signals.

all subsequent interrupts, saves the Program Counter and status flags, and branches to the program memory vector locations reserved for that interrupt. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request.

Polled interrupt systems are also supported. To accom- modate a polled structure, any or all of the interrupt inputs can be masked and the Interrupt Request register polled to determine which of the interrupt requests needs service.

• AT cut, parallel resonant

• Fundamental type, 8 MHz maximum

• Series resistance, Rs ~ 100n

INSTRUCTION SET NOTATION

Addressing Modes. The following notation is used to describe the addressing modes and instruction operations . as shown in the instruction summary.

IRR Indirect register pair or indirect working-register pair address

Irr Indirect working-register pair only X Indexed address

DA Direct address RA Relative address

1M Immediate

R Register or working-register address r Working-register address only

IR Indirect-register or indirect working-register address

Ir Indirect working-register address only RR Register pair or working register pair address Symbols. The following symbols are used in describing the instruction set.

dst src cc

@

Destination location or contents Source location or contents Condition code (see list) Indirect address prefix SP

PC FLAGS

RP

IMR

Stack pointer (control registers 254-255) Program counter

Flag register (control register 252) Register pointer (control register 253) Interrupt mask register (control register 251) CONDITION CODES

Value. Mnemonic

1000 Always true

0111 C Carry

1111 NC No carry

0110 Z Zero

1110 NZ Not zero

1101 PL Plus

0101 MI Minus

0100 OV Overflow

1100 NOV No overflow

0110 EO Equal

1110 NE Not equal

Assignment of a value is indicated by the symbol "+-': For example.

dst +-dst + src

indicates that the source data is added to the destination data and the r~sult is stored in the destination location. The notation "addr(n)" is used to refer to bit "n" of a given location. For example,

dst(7) refers to bit 7 of the destination operand.

Flags. Control Register R252 contains the following six flags: .

C Carry flag Z Zero flag S Sign flag V Over'flow flag

o

o

*

X Undefined

Meaning. Flags Set

C = 1 C=O Z = 1 Z=O S=O S = 1 V=l V=O Z = 1 Z=O

1001 GE Greater than or equal (S XOR V) = 0

0001 LT Less than (SXORV) = 1

1010 GT Greater than [ZOR(SXORV)i = 0

0010 LE Less than or equal [ZOR (SXORVjJ = 1

1111 UGE Unsigned greater than or equal C =0

0111 ULT Unsigned less than C = 1

1011 UGT Unsigned greater than (C = 0 AND Z = 0) = 1

0011 ULE Unsigned less than or equal (CORZ) = 1

0000 Never true

5

INSTRUCTION FORMATS

OPC MODE

del/Ire OR It •• oldoUlre

I

OPC dll

lOR I.

VALUE

OPC MODE do. ore

MODE OPC dst/src lreldst

OR 11 1 1 01 ore

do.

I

VALUE

I

OPC

J

do. OPC

CCF, DI, EI, IRET, NOP, RCF, RET, SCF INCr One-Byte Instructions

CLR, CPL, DA, DEC, OPC MODE

DECW, INC, INCW, POP, Ire OR • • • 0

PUSH, RL, RLC, RR,

RRC, SRA, SWAP dol OR • • • 0

JP, CALL (Indlract)

OPe MODE

do. OR 11 1 1 01

SRP VALUE

MOD OPC

ore OR 1 1 1 0 ADC, ADD, AND,

cp, OR, SBC, SUB, do. OR 1 1 1 0

TCM, TM,XOR

MODE OPC

LD, LOC, LDCI dstlsrc

ADDRESS

LD cc OPC

DAu DAL

LD

rn

DJNZ,JR DAL

ADC, ADD, AND, CP, src LD, OR, SBC, SUB,

TCM, TM,XOR do.

ADC, ADD, AND, CP, do. LD, OR, SBC, SUB,

TCM, TM, XOR

LD Ire do.

LD

JP

CALL

1\No-Byte Instructions Three-Byte Instructions

Figure 7. Instruction Formats

INSTRUCTION SUMMARY

AddrMode Opcode Flags Affected AddrMode Opcode Flags Affected

Instruction Byte Instruction Byte

and Operation dst src (Hex) C Z S V 0 H and Operation dst src (Hex) CZSVDH ADCdst,srQ (Note 1) 10 *' *' *' *'

o

*' *' *' * , - -

dst-dst + src + C dSt'- src

ADDdst,src (Note 1) 00

*' *' *' *'

o

x--

dst - dst + src dst-OAdst IR 41

ANDdst,src (Note 1) 50 - * * ' 0 - - DECdst R 00 - * * ' * - -

dst - dst AND src dst-dst - 1 IR 01

CALLdst OA 06

- - - -

SP-SP - 2 IRR 04 dst-dst - 1 IR 81

@SP - PC; PC - dst

01

CCF EF * - - - IMR(7)-0 8F - - - - , - -

C-NOTC

DJNZr,dst RA rA - - - -

CLRdst R BO - - - r-r-1 r=O-F

dst-O IR B1 if r #"0

COMdst R 60 - * * 0 - - PC-PC + dst

dst-NOTdst IR 61 Range: +127, -128

INSTRUCTION SUMMARY (Continued)

Instruction and Operation

Addr Mode Opcode Flags Affected Byte

dst src (Hex) ICZSVDH EI

IMR(7)-1

9F

INCdst

dst-dst + 1

rE -***--

r = 0 - F

INCWdst dst-dst + 1

R

IR

RR

IR

20 21

IRET BF

FLAGS - @SP; SP - SP + 1 PC-@SP;SP-SP + 2; IMR(7)-1 JPcc,dst

ifcc is true PC-dst JRcc,dst ifcc is true,

PC-PC + dst Range: + 127, -128 LD dst,src

dst-src

OA IRR RA

r R r X

r- Ir R

1m R

X r Ir r R R IR R 1M IR 1M IR R LDC dst,src r Irr

dst-src Irr

LDCI dst,src Ir Irr

dst·- src Irr Ir

r-r + 1; rr-rr + 1 NOP

ORdst,src (Note 1) dst - dst OR src

POPdst R

dst-@SP; IR

SP-SP + 1

PUSHsrc R

SP -SP - 1; @SP":-src IR RCF

C-O RET

PC-@SP;SP-SP+ 2

cD c=O-F

30 cB c=O-F

rC r8 r9 r = 0 - F

C7 07 E3 F3 E4 E5 E6 E7 F5 C2 02 C3 03 FF 40

50

70 71 CF

AF

* * * * * *

0 - - - - -

Addr Mode Opcode Instruction

and Operation dst

RLdst c~ R

~IR RLCdst~R

c , , IR

RR dst

l[ri

lciJ

RRC dst

l{ri:ciJ

c , 'IR

src

SBC dst,src (Note 1) dst-dst-src-C

SCF C-1

SRA dst

LiiJ

W

RP-src

1m SUBdst,src

dst - dst - src

(Note 1)

SWAPdst

5?

I ' D ' I I R TCM dst,src (Neite 1) (NOT dst) AND src

TM dst,src dstANO src XORdst,src dst - dst XOR src

(Note 1) (Note 1)

Byte (Hex) 90 91 10 11

EO

E1 CO C1 3D

OF DO 01 31

20 FO F1 60 70 BO

Flags Affected CZSVDH

* * * * - -

* * .* *

* * * * - -

* * * * - -

1 - - - - -

* * * 0

X**X--

NOTE 1: These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode nibble is found in the instruction set table above. The second nibble is expfessed symbolically by a D in this table, and its value is found in the following table to the right of the applicable addressing mode pair.

For example, the opcode of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13.

AddrMode

dst src

R R R IR

Ir R IR 1M 1M

Lower Opcode Nibble

7

REGISTERS (Continued)

R248P01M PORT 0 AND 1 MODE REGISTER

(F8H; Write Only)

P04-PO, MODE

~ l~~

OUTPUT = 00 ~

L

INPUT", 01 01, '" INPUT

RESERVED , S{A;~N~~~~C;~ON

P10·P17 MODE 00 '" BYTE OUTPUT 01 ", BYTe INPUT 11 '" HIGH·IMPEDANCE os

R2491PR

INTERRUPT PRIORITY REGISTER (F9H; Write Only) I~I~I~I~I~I~I~I~I

~_,,:J II ^II.

DON'T CARE 524 = 010

542 = 011 245 = 100

DON'T CARE 425 = 101

254 = 110

DON'T CARE RESERVED = ¹¹¹

R250lRQ

INTERRUPT REQUEST REGISTER (FAH; Read/Write) I~I~I~I~I~I~I~I~I

RESERVED

==r- ^c=

IRQ4 = T(I IRQ5 '" T1

R2511MR INTERRUPT MASK REGISTER

(FBH; Read/Write)

I' ^c=

(Do::: IROO) L - - - R E S E R V E D ' - - - 1 ENABLES INTERRUPTS

REGISTE'R POINTER

R252 FLAGS FLAG REGISTER (FCH; Read/Write)

lli!~~

, ~USER ^{flAG F2}

HALF CARRY FLAG

.

DECIMAL ADJUST flAG OVERFLOW FLAG SIGN FLAG ZERO .FLAG CARRY FLAG

R253 RP REGISTER POINTER

(FDH; Read/Write)

R255SPL STACK POINTER (FFH; Read/Write)

Figure 8. Control Registers (Continued)

OPCODEMAP

~----6.5 6.5 6.5 6.5 10.5

DEC DEC ADD ADD ADD

R, IR, f1 f2 f1·lr2 R2·Rl

6S 6.5 6S 6.S 10.S

RLC RLC ADC ADC ADC

R, IR, f1·r2 f1,lr2 R2,R,

6S 6,S 6,S 6,S 10,S

INC INC SUB SUB SUB

R, IR, f1·f2 f1, lr2 R2,R,

80 6,1 6,5 6,5 10,5

JP SRP SBC SBC SBC

IRR, 1M rl J 2 f1, lr2 R2,R,

8,S 8,S 6,S 6,S 10,S

4 DA DA OR OR OR

R, IR, f1,f2 f1, lr2 R2,R,

1O,S 10,5 6,S 6,S 10,5

POP POP AND AND AND

R, IR, f1·f2 f1, lr2 R2,R,

6,S 6,S 6,5 6,5 10,5

6 COM COM TCM TCM TCM

R, IR, f1·r2 f1, lr2 R2·R, 10112.1 12114,1 6,S 6,5 10,S

PUSH PUSH TM TM TM

i e.

R2 IR2 f,J2 f1·lr2 R2,R,

J!

,Q ,Q - - - - -

z

DeCW DECW

RR, IR,

:;;

0. 0.

::>

6.5 6,S

RL RL

R, IR,

10,5 1O.S 6S 6.5 10.5

A INCW INCW CP CP CP

RR, IR, f1 J2 f,.lr2 R2,R,

6,5 6,S 6,S 6,S 10,5

B CLR CLR XOR XOR XOR

R, IR, rlJ2 f1·lr2 R2,R , 6,5 6.5 12,0 18,0 C RRC RRC LDC LOCI

R, IR, r,.lrr2 Ir1,lrr2

6,5 6,5 12,0 18,0 20.0

o SRA SRA LDC LOCI CALL"

R, IR, f2, lrr 1 Ir2,lrr1 IRR,

6,S 6,5 6,5 10,5

E RR RR LD LD

R, IR, r" IR2 R2,R,

85 8.5 6,S

SWAP SWAP LD

R, IR, Ir1·f2

10 5 10.5

ADD ADD

IR2·R, R,.IM 10.S 1O.S

ADC ADC

IR2,R, R,IM 1O,S la,S

SUB SUB

IR2,R, R"IM 10.5 1O,S

SBC SBC

IR2,R, R

"IM 10,S 1O,S

OR OR

IR2,R, R"IM 10,5 10,5

AND AND

IR2,R, R"IM 10,5 10,5

TCM TCM

IR2·R, R,.IM 10,5 10.5

TM TM

IR2,R,

f---

R"IM

10,S 10,5

CP CP

IR2,R, R,IM 1O.S 10 5

XOR XOR

IR2,R, R,.1M

20,0

CALL DA 10,5 10 S

LD LD

IR2·R, R,.IM 10,S

LD

R2·IR,

Lower Nibble (Hex) 7

lOS 6.5

ADD LD

IR,.IM f1 R2 1O.S

ADC

IR"IM lO.S

SUB

IR"IM la,S

SBC

IR"IM 1O,S

OR

IR"IM 1O,S

AND

IR"IM 1O,S

TCM

IR"IM 10,5

TM

IR"IM

lOS

CP

IR"IM 10,5

XOR

IR"IM 10,5

f,

LD 'r2,x.R,

1O,S

LD

IR"IM

A B C o E F

---_.-_._-- -_.- -- 121100-

6S 12110 S 12110 Q 65 6S

LD DJNZ JR LD JP INC

f;?,R 1 f1 RA cc RA fllM cc DA r1

c---

f----~

r---

I I

H

f - - - -

I--- r---

r---s;--

01

r---

6.1

'EI

r---

14

°

RET

~I

r---

6.5

RCF

~ SCF

r---

65

CCF

~ NOP '-... - - - -.... v ... ----""~ ... - - - -.... v ...

----"".1 ... - - - - -...

EXECUTION CYCLES UPPER OPCODE_A

NIBBLE FIRST OPERAND

LOWER OPCODE NllLE

• 2-byte instruction, letch cycle appears as a 3-byte instruction

3

PIPELINE CYCLES

MNEMONIC

SECOND OPERAND

Bytes per Instruction

Legend:

R = 8-bit address r = 4,blt address Rl or f1 = 05t address R2 or f2 = Src address Sequence:

Opcode, First Operand, Second Operand NOTE' The blank areas are not defined

9

REGISTERS

R241 TMR TIMER MODE REGISTER

(F1 H; Read/Write)

T,", MODES

~ llS~o

NOT USED = 00 ~ 1 :: LOAD To

i~ g~i ~ ~~ 0:: DISABLE To COUNT INTERNAL CLO. CK OUT:: 11 1 '" ENABLE To COUNT

T MODES 0 :: NO FUNCTION

EXTERNAL CLOCK tNplOr :: 00 , 1 '" LOAD 11

GATE INPUT:: 01 0 = DISABLE t, COUNT

(NON.R1~~~g~:~::~~) = 10 1 = ENABLE T, COUNT

TRIGGER INPUT = ¹¹ (RETRIGGERABLE)

R242 T1 COUNTER TIMER 1 REGISTER

(F2H; Read/Write)

1\ T, INITIAL VALUE (WHEN WRITTEN) '-'----(RANGE 1 256 DECIMAL 01 00 HEX) T, CURRENT VALUE (WHEN READ)

R243 PRE1 PRESCALER 1 REGISTER

(F3H; Write Only)

~L

1 :::: T, INTERNAL . 0 = .T1 EXTERNAL TIMING INPUT

(TIN) MODE PRESCALER MOOULO (RANGE: 1~64 DECIMAL 01-00 HEX)

R244 TO

COUNTER/TIMER 0 REGISTER (F4H; Read/Write)

To INITIAL VALUE (WHEN WRITTEN) ' - - - ( R A N G E : 1 256 DECIMAL 01 00 HEX) To CURRENT VALUE (WHEN READ)

R245PREO PRESCALER 0 REGISTER

(Ft/H; Write Only)

~L ^COUNTMODE

RESERVED

PRESCALE'R MODULO (RANGE: 1-64 DECIMAL 01-00 HEX)

R246P2M PORT 2 MODE REGISTER

(F6H; Write Only)

R247P3M PORT 3 MODE REGISTER

(F7H;Write Only)

~~ ^I L ^L

RESERVED RESERVED

o P31 '" INPUT (TIN) P36 '" OUTPUT (TOUT) RESERVED

L -_ _ _ _ _ _ _ _ RESERVED

Figure 8. Control Registers

AC CHARACTERISTICS

Timing Table

Number Symbol TpC

? ^TrC.TIC

3 TwC

4 TwTinL 5 TwTinH 6 TpTin 7 TrTin,TfTin B TwlL 9 TwlH NOTES:

Figure 9. Timing

Parameter Input Clock Period

Clock Input Rise and Fall Times Input Clock Width

Timer I nput Low Width Timer Input High Width Timer InputPeriod

Timer Input Rise and Fall Times Interrupt Request Input Low Time Interrupt Request Input High Time 1. Clock timing references use3.8Vfor a logic "1" and 0.8Vfor a logic "0':

2. Timing references use 2.0Vfor a logic "1" and 0.8V for a logic "0':

3. Interrupt request via Port 3 (P31·P33)'

• Units in nanoseconds (ns).

Z8600 Min Max 125 1000 25 37 100 3TpC BTpC

100 100 3TpC

Notes'

1 2 2 2 2 2,3 2.3

ABSOLUTE MAXIMUM RATINGS

Voltages On all pins with respect

toGND . . . -O.3Vto +7.0V Operating Ambient

Temperature ...

Storage Temperature ..

. .. See Ordering Information ... -65°C to + 150°C

STANDARD TEST CONDITIONS

The DC characte\risticslisted below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin.

Standard conditions are:

• +4.75V~ Vee~ +5.25V

• GND =OV

DC CHARACTERISTICS

Symbol Parameter Min

VeH Clock Input HighVoltage 3.8

Vel Clock Input Low Voltage -0.3

VIH Input High Voltage 2.0

Vil Input low Voltage -0.3

VRH Reset Input High Voltage 3.8

VRl Reset I nput Low Voltage -0.3

VOH Output High Voltage . 2.4

VOL Output Low Voltage

III Input Leakage -10

'OH Output Drive Current

IOl Output Leakage -10

IIR Reset Input Current lee Vee Supply Current

Stresses greater than those listed-under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extendep periods may affect device reliability.

+5V 2.1K

Figure 10. Test Load 1

Max Unit Condition

Vee V Driven by External Clock Generator 0.8 V Driven by External Clock Generator

Vee V

0.8 V

Vee V

0.8 V

V IOH = -250,..A 0.4 V IOl = +2.0 mA 10 ,..A OV <> VIN <>+ 5.25V

1.5 rnA _VOH

=

=

150 mA

~ ZiIill Product Specification

Features

General Description

Z860VZ8603 Z861VZ8613 Z8®

• Complete microcomputer, 2K (8601) or 4K (8611) bytes of ROM, 128 bytes of RAM, 32 I/O lines, and up to 62K (8601) or 60K (8611) bytes addressable external space each for program and data memory.

• 144-byte register file, including 124 general- purpose registers, four I/O port registers, and 16 status and control registers.

• Average instruction execution time of 1.5 /LS, maximum of 1 /LS.

• Vectored, priority interrupts for I/O, counter/timers, and UART.

The 28 microcomputer introduces a new level of sophistication to single-chip architecture.

Compared to earlier single-chip micro- computers, the 28 offers faster execution; more efficient use of memory;' more sophisticated interrupt, input/output and bit-manipulation capabilities; and easier system expansion.

Under program control, the 28 can be tailored to the needs of its user. It can be configured as a

PORTO (NIBBLE PROGRAMMABLE) 1/0 OR Ae-A15

PORT 1 (BYTE PROGRAMMABLE) 1/0 OR ADo-AD7

PORT 2 (BIT PRO·

GRAMMABLE) , 110

PORT 3 SERIAL AND PARALLEL 110 AND CONTROL

2'8601 Single-Chip MCU with 2K ROM

28603 Prototyping Device with 2K EPROM Interface Z8611 Single-Chip MCU with 4K ROM

Z86l3 Prototyping Device with 4K EPROM Interface

• Full-duplex UART and two programmabla 8-bit counter/timers, each with a 6-bit programmable prescaler.

• Register Pointer so that short, fast instruc- tions can access any of nine working register groups in I /LS.

• On-chip oscillator which accepts crystal or external clock drive.

• Single + 5 V power supply-all pins TTL compatible.

• 12.5 MHz.

stand-alone microcomputer with 2K or 4K bytes of internal ROM, a traditional microprocessor that manages up to 124K bytes of external memory, or a parallel-processing element in a system with other processors and peripheral controllers linked by the 2-BUS® bus. In all configurations, a large number of pins remain available for I/O.

+5V P3,

XTAL2 P3,

XTAL1 P2,

P'37 P2,

P30 P2,

FIESE'f P2,

R/W P2,

os P2,

AS P2,

P3, P20

GND P3,

P3, P3,

po, P1,

po, P1,

-:'02 P1,

po, P1,

po, P1,

PO, P1,

po, P1,

po, P1,

Figure 2a. 40-pin Dual-In-Line Package (DIP).

Pin ASSignments

Pin Description

AS. Address Strobe (output, active Low).

Address Strobe is pulsed once at the begin- ningofeach machine cycle. Addresses output via Port 1 for all external program or data memory transfers are valid at the trailing edge of AS. Under program control, AS can be placed in the r.igh-impedance state along with Ports 0 and 1, Data Strobe and Read/Write.

OS. Data Strobe (output, active Low). Data Strobe is activated once for each external memory transfer.

POO-P07' Plo-PI7. P2o-P27' P30-P37' I/O Port Lines (input/outputs, TTL-compatible). These 32 lines are divided into four 8-bit I/O ports that can be configured under program control for I/ 0 or external memory interface.

RESET. Reset (input, active Low). RESET ini- tializes the 28. When RESET is deactivated,

program execution begins from internal program location OOOCH. '

ROMless. (input, active LOW). This pin is only available on the 44 pin version of the Z8611, When connected to GND disables the internal ROM and forces the part to function as a Z8681 ROM less Z8. When left unconnected or pulled high to V cc the part will function normally as a Z8611.

R/W. Read/Write (output). R/W is Low when the Z8 is writing to external program or data ' memory.

XTALl. XTAL2. Crystall, Crystal 2 (time-base input and output). These pins connect a parallel resonant 12.5 MHz crystal or an external single- phase 12.5 MHz clock to the on-chip clock oscillator and buffer.

'Y .... '::v~

~(j <1,,,. <I,,,,.¢,,, .¢'"

."4.

~ 7

RIW 8 DS 9 AS 10 P3. 11 GND 12 P3, 13 PO. 1.

PO,

,.

PO, 16 ROMless 17

6 5 4 3 2 1 « ~ ~ 41 ~

Z8611 MCU

18 19 20 21 22 23 24 25 26 27 28 qO~ qt::J~ qt::>~ <I.~'o q~'\ q"~ <l ... q,1-q ... "bq .... ~ ~CJ

39 NC 38 P2, 37 P2.

36 P2, 3. P2, 3' P2.

33 P3.

32 P3, 31 P17 30 P1.

29 P1.

Figure 2b. 44-pin Chip Carrier. Pin Assignments

2037-002

Architecture Z8 architecture is characteri:;::ed by a flexible Three basic address spaces are available to support this wide range of configurations:

program memory (internal and external), data memory (external) and the register file (inter- nal). The 144-byte random-access register file is composed of 124 general-purpose regist~rs,

four I/O port registers, and 16 control and status registers.

2037-003

I/O scheme, an efficient register and address space structure and a number of ancillary features that are helpful in many applications.

. Microcomputer applications demand power- ful I/O capabilities. The Z8 fulfills this with 32 pins dedicated to input and output. These lines are grouped into four ports of eight lines each and are configurable under software control to provide timing, status Signals, serial or parallel I/O with or without handshake, and an address/

data bus for interfacing external memory.

Because the multiplexed address/data bus is merged with the I/O-oriented ports, the Z8 can assume many different memory and I/O con- figUrations. These configurations range from a self-contained microcomputer to a micropro- cessor that can address 124K (Z8OOl) or 120K (Z86U) bytes of external memory.

OUTPUT

, To unburden the program from coping with real-time problems such as serial data com- munidation and counting/timing, an asynchro- nous receiver/transmitter (UART) and two counter/timers with a large number of userse- lectable modes are offered on-chip. Hardware support for the UART is minimi:;::ed because one of the on-chip timers supplies the bit rate.

XTAL Ai

'} 2O.:S:O':'BIT ZlB11 L. _ _ ~_.J 4098. a·BIT

(BIT PROGRAMMABLE) uo ADDRESS OR UD

(NIBBLE PROGRAMMABLE) ADDRESS/DATA OR UO (BYTE PROGRAMMABLE)

~I~ .. 3. Functional Block Diagram

Address Spaces

Program Memory. The 16-bit program counter addresses 64K bytes of program memory space, Program memory can be located in two areas:

one internal and the other external (Figure 4).

The first 2048 (28601) or 4096 (28611) bytes consist of on-chip mask-programmed ROM. At.

addresses ;2048 (28601) or 4096 (Z8611):and greater, the Z8 executes external program memory fetches.

The first 12 bytes of prograin memory are' reserved for the interrupt vectors. These loca- tions contain six 16-bit vectors that correspond to the six available interrupts.

Data Memory. The Z8 can address 62K (28601) 9r 60K (Z8611) bytes of external data memory beginning at location 2048 (28601) or 4096 (28611) (Figure 5). External data memory may

... ^, .

2048 2047

location 01 ftlllt~of instruction

...-

aftarraeet

Intenupt

-

(Lower Byte)

i2

11

,.

•

7

• •

EXTERNAL ROM OR RAM

ON·CHIP ROM

~---

IRQ5 IRQ5 IRQ<

IRQ4 IRQ3 IRQ3 IRQ2 Intenupt

-

(Upper Byte)

• 1>0"_ ^IRQ2

....

,

•

•

:Z8811

Figure 4. Pr"gram Memory Map

LOCATION

... ...

... ...

...

... ...

...

'43 .42

...

STACK POINTER BITS 7-0) STACK pOINTER (BITS 15-8) REGISTER POINTER PROGRAM CONTROL FLAGS INTERRUPT MASK REGISTER INTERRUPT REQUEST REGISTER INTERRUPT PRIORITY REGISTER

PORTS 0-1 MODE PORTa MODE PORT 2 MODE TO PRESCALER TIMERICOUNTER 0

T1 PRESCALER TtMERICOUNTER 1

nMER MODE SERIAL UO

NOT IMPLEMENTED

GENERAL·PURPOSE REGISTERS

PORT 3 PORT 2 PORT 1 PORTO

Fig .... 6. The Reglater FUe

IDENTIFIERS SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P3M PR ..

TO PRE1 Tl TMR SIO

PO

.,

be included with or separated from the external program memory space. DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space.

Register File. The 144-byte register file includes four I/O port registers (RO-R3), 124 general-purpose registers (R4-RI27) and 16 control and status registers (R240":R255). These registers are assigned the address loca1tions shown in Figure 6. '

Z8 instructions can access registers directly or indirectly with an 8-bit address field. The 28 also allows short 4-bit register addressing using the Register Pointer (one of the control regis- ters). In the 4-bit mode, the register file is

EXTERNAL DATA MEMORY

zaem=I---I:Z8611

NOT ADDRESSABLE

, Figure 5. Data Memory Map

--{

^... ...

The upper nibble of the register tile addl'8S8

>---provided by the register pointer specllies the active wortdng.reglster woup.

-- -- -- --

,.7

The lower nibble of

r--'

REGISTER BROUP - I -

the register 1118_

provided by the.lns1rUcllon points to the specllied register.

-- -- ,.

--

2037·004, 005, 006, 007

Serial Input/

Output

Counter/

Timers

20~7-009

,divided into nine working-register groups, each occupying 16 continguous locations (Figure 6).

The Register Pointer addresses the starting location of the active working-register group.

Stacks. Either the internal register file or the external data memory can be used for the stack.

Port 3 lines P30 and P3z can be programmed as serial I/O lines for full-duplex serial asynchro- nous receiver/transmitter operation. The bit rate is controlled by CounterlTimer 0, at 12 MHz.

The Z8 automatically adds a start bit and .two stop bits t6 transmitted data (Figure 8). Odd parity is also available as an option. Eight data bits are always transmitted, regardless of parity

Trcmsmltted Data (No Parity)

LSTAATBIT ' - - - E l G H T DATA BITS

TWO STOP BITS

T1'CID8DIltted Data (With Parity)

Isplspl p 1 .. 1.,1 •• 1 D,I .,I.,! D,I STI

T

LST"RTBIT

' - - - S E V E N DATA BITS L -_ _ _ _ _ _ _ ODDPARITY

TWO STOP BITS

A 16-bit Stack Pointer (R254 and R255) is used for the external stack, which can reside anywhere in data memory between locations 2048 (8601) or 4096 (8611) and 65535. An 8-bit Stack Pointer (R255) is used for the internal stack that resides within the 124 general-purpose'registers (R4-R127).

selection. If parity is enabled, the eighth bit is the odd parity bit. An interrupt request (IRQ4) is generated on all transmitted characters.

Received data must have a start bit, eight data bits and at least one stop b\t. If parity is on, bit 7 of the received data is replaced-by a Piirity error flag. Received characters generate the IRQ3 interrupt request.

Received Data (No Parity) I~I~I

.. I .. I .. I .. I .. I .. I .. ISTI

LSTARTBIT ' - - - e I G H T DATA BITS l - - - O N E S T O P BIT

Received Data (With Parity) 1~lpl

.. I .. I .. I .. I .. I .. I .. ISTI

,\1<---_ ^L--~

^LSTARTBIT

Figure 8. Serial Data Formate The Z8 contains two 8-bit programmable

counter/timers (To and Tl), each driven by its own 6-bit programmable prescaler. The T 1

prescaler can be driven by internal or external clock sources; however, the To prescaler is driven by the internal clock only.

The 6-bit prescalers can divide the input fre- quency of the clock source by any number from 1 to 64. Each prescaler drives its counter, which decrements the value (l to 256) that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request-IRQ4 (to) or IRQ5 (Tl)-is generated.

The counters can be started, stopped, restarted to continue, or restarted from the - initial value. The counters can also be pro- grammed to stop upon reaching zero (single-

pass mode) or to automatically reload the initial value and continue counting (modulo-n contin- uous mode). The counters, but not the presca- lers, can be read any time without disturbing their value or count mode.

The clock source for T 1 is user-definable and can be the internal microprocessor clock divided by four, or an external signal input via Port 3. The Timer Mode register configures the external timer input as an external clock, a trigger input that can be retriggerable or non- retriggerable, or as a gate input for the internal clock. The counter/timers can be programmably cascaded by connecting the To output to the input of T 1. Port 3 line P36 also serves as a timer

outp~t (TOUT) through which To, Tl or the inter- nal clock can be output.

17

110 Ports

18

The Z8 has 32 lines dedicated to input and output. These lines are grouped into four ports of, eight lines each and are configurable as input, output or address/data. Under software control, the ports can be programmed to provide address

Port 1 can be programmed as a byte 1/0 port or as an addre~s/data port for interfacing external memory: When used as an 1/0 port, Port 1 may be placed under handshake con-

tro!. In this configuration, Port 3 lines P33 and P34 are used as the handshake controls RDY I and DAV I (Ready and Data Available).

Memory.1ocations greater than 2048 (28601) or 4096 (Z86ll) are referenced through Port 1. To interface external memory, Port 1 must be programmed for the multiplexed AddresslData . mode. If more than 256 external locations are

required, Port 0 must output the additional lines.

Port 1 can be placed in the high-impedance state along with Port 0, AS, DS and RIW,

Port 0 can be programmed as a nibble 1/0 port, or as an address port for interfacing external memory .. When used as an 1/0 port, Port

o

For external memory references, Port 0 can provide address bits As-All (lm'!er nibble) or As-AIS (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently ps 1/0 while

Port 2 bits can be programmed independently as input or output. The port is always available for 1/0 operations. In addition, Port 2 can be configured to provide open-drain outputs.

Like Ports 0 and L Port 2 may also be placed under. handshake control. In this, con- figuration, Port 3 lines P31 and P36 are used as the handshake controls lines DAV 2 and RDY 2.

The handshake signal assignment for Port 3 lines P3j and P36 is dictated by the direction (input or output) assigned to bit 7 of Port 2.

Port 3 lines can be configured as 1/0 or control lines. In either case, the direction of the eight lines is fixed as four input (P30-P33) and' four output (P34-P37)' For serial 1/0, lines P30 and P~ are programmed as serial in and serial out respectively.

Port 3 can also provide the follOWing con- trol functions: handshake for Ports 0, 1 and 2 (DAVand RDY); four e~ternal interrupt request signals (IRQo-IRQ3); ti,mer input and output signals (T~nd Tour) and Data Memoty Select (DM):

outputs, timi.ng, status sig;nals, serial 1/0, and parallel VO with or without handshake. All ports have active pull-ups and pull-downs compatible with TTL loads.

allowing the Z8 to share common resources in multiprocessor and DMA applications. Data transfers can be controlled by assigning P33 as a Bus Acknowledge input and P34 as a Bus Request output.

Z8 MCU

PORT.

(I/O OR ADo-AIl,)

Figure

sa.

the lower nibble is used for addressing. When Port 0 nibbles are defined as address bits, they can be set to the highimpedance state along with Port 1 and the control signals AS, DS and RIW.

Z8 MCU

ZB MCU

Figure 9b. Port 0

PORT 2(110)

} HWa~=~~ED~~NTROLS (pa, AND P3e)

Figure Sc. Port 2

PORTa

I Z8 (110 OR CONTROL)

MCU

Figure 9d. Port 3

2037·008

Interrupts

Clock

The 28 allows six different interrupts from eight sources: the four Port 3 lines P30-P33, Serial In, Serial Out. and the two counter/timers.

These interrupts are both maskable and prioritized. The Interrupt Mask register globally or individually enables or disables the six inter- rupt requests. When more than one interrupt i~

pending, priorities are resolved by a pro- ' grammable priority encoder that is controlled by the InterruptPriority register.

All 28 interrupts are vectored: When an inter- rupt request is granted, an interrupt machine

The on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal or to any suitable external clock source (XTALl :, Input, XTAL2 = Output).

The crystal source is connected across XTALl and XTAL2, using the recommended capacitors

cycle is entered. This disables all subsequent interrupts, saves the Program Counter and status flags, and branches. to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request.

Polled interrupt systems are also supported. To accommodate a polled structure, any or all of the interrupt inputs can be masked and the Interrupt Request register polled to determine which of the interrupt requests needs service.

(Cj :$ 15 pF) from each pin to ground. The specifications for the crystal are as follows:

• AT cut, parallel resonant

• Fundamental type, 12.5 MHz maximum

• Series resistance, Rs :$ 100

n