MOS INVERTERS
Prof. Philippe LORENZINI
Polytech-Nice Sophia
Pr. Ph.Lorenzini 2
Outline
• Metal Oxyde Semiconductor Structure
• MOS Transistor
• MOS Inverters
• NMOS
• CMOS
From MOS Capacitor to CMOS inverter
• Two definitions (only 2!)
• Work Function (Travail de sortie) : this is the energy we have to give to an electron to extract it of metal without kinetic
energy. It reaches the "vacuum level". Work function is the energy difference between the vacuum level and the highest occupied energy level, ie the Fermi level.
• Electron Affinity (Affinité électronique ) : it’s the difference between the vacuum level and the bottom of the conduction band.
It’s only defined for SC and not for Metal.
• Unity for both of them: eV (electron volt)
e M
e SC
Pr. Ph.Lorenzini 4
Metal Oxyde Semiconductor Structure
MOS capacitor Energy band diagram of the three components of a MOS system
fi g
SC
SC e
E
2 fi
g SC
SC e
E
2
From MOS Capacitor to CMOS inverter
• The field effect is the variation of the conductance of a
channel in a semiconductor by the application of an
electric field
Pr. Ph.Lorenzini 6
Equilibrium of MOS structure
eM
e
SCe
SCE F E F
Metal SC(n)
E V E C
SC SC
M bi
x dx
V d dx
E dV
V
, 2 ( )
2
,
Independant system
eM
eSC
e
SCE F E F
Metal SC(n)
E V E C
eVbi
Equilibrium state
dx
From MOS Capacitor to CMOS inverter
(a) Accumulation (b) Flat band
(c) Desertion / depletion (d) Weak inversion
(e) Strong inversion
Pr. Ph.Lorenzini 8
Energy band diagram for ideal n and p type MOS capacitors under different bias conditions
From MOS Capacitor to CMOS inverter
Pr. Ph.Lorenzini 10
We suppose we deal with a p type semiconductor:
0
F Fi
Fi E E
e
Vg Vs
x V
x
V ( ) 0 , ( 0 ) ,
warning: in few books, absolute value is not present!!!!
Field, potential and charges in Silicon
From MOS Capacitor to CMOS inverter
Poisson’s Equation :
Charge density
( ) ( ) ( ) ( )
)
( x e p x n x N D x N A x
n N
AN
Dp
0 00 exp( )
kT n e
n i Fi
0exp( )
kT n e
p
i
Fi ) )
) ( exp( (
) ) exp( (
)
(
0kT x V n e
kT x n eV
x
n
i
Fi
kT
x p eV
kT x V n e
x
p
i Fi( )
exp ) )
) ( exp( (
)
(
0SC
x dx
V d
( )
2
2
Pr. Ph.Lorenzini 12
kTx eV kT
x eV
e n e
p p
n e x
) ( 0 )
( 0
0
)
0 (
(
1 ) (
1 )
)
(
( )0 )
( 2 0
2
kT x eV kT
x eV
SC
e n e
e p dx
x V d
dx x dV dx
x dV dV
d dx
x dV dx
d dx
x V
d ( ) ( ) ( ) ( )
2 2
) ( )
1 (
) 1 ) (
( )
(
( )0 )
(
0
e n e dV x
e p dx
x d dV
dx x
dV
eVkTx eVkTxSC
From MOS Capacitor to CMOS inverter
Field, potential and charges in Silicon
• We compute the integral from bulk to a point x in SC
( ) 0
) ( 0
) ( 0
) (
0
( ) ( )
V x(
eVkTx1 ) (
eVkTx1 ) ( )
SC x dx
dV
x dV e
n e
e p dx
x d dV
dx x dV
V(x=« bulk »)=0 et ( ) 0
dx
bulkx dV
dx x x dV
E ( )
)
( And the Electric Field is given by :
( ) 1
) 1 2 (
) ) (
(
) (
0 ) 0
0 ( 2
2
kT x e eV
p n kT
x e eV
kTp dx
x x dV
E
eV x kT eV x kT
SCMO S
V g
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 14
( ) 1
) 1 ( 2
) ) (
(
) (
0 ) 0
( 2
2 2
2
kT x e eV
p n kT
x e eV
L e
kT dx
x x dV
E
eV x kT eV x kTD
With the Debye length:
o SC
D e p
L 2 kT
If we use the Gauss’s theorem:
SC SC S
E Q x
E ( 0 ) Field, potential and charges in Silicon
metal kT S
V S e
eV kT D
SC
SC
Q
kT eV p
e n kT
e eV L
e
Q kT
S S FI
21
0 0 )
2 (
1
2 1
metal kT S
V S e
eV kT D
SC
SC
Q
kT eV p
e n kT
e eV L
e
Q kT
S S FI
21
0 0 )
2 (
1
2 1
metal kT S
V S e
eV kT D
SC
SC
Q
kT eV p
e n kT
e eV L
e
Q kT
S S FI
21
0 0 )
2 (
1
2 1
metal kT S
V S e
eV kT D
SC
SC
Q
kT eV p
e n kT
e eV L
e
Q kT
S S FI
21
0 0 )
2 (
1
2 1
For V s (and so V g ) negative (accumulation)
For V s (and V g ) positive but less than 2 fi
(depletion – weak inversion)
For V s (and Vg) > 2 fi
(strong inversion)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 16
Weak / Strong Inversion
n s =p 0 =N A
i A Fi
S
n
N e
V 2 kT ln
2
i A Fi
S
n
N e
V 2 kT ln
2
This condition will define a very important parameter of the
struture: the threshold voltage or the required gate voltage to put the transistor in strong inversion regime
eFI
The C-V curve is usually measured with a CV meter:
• We apply a DC bias voltage Vg + small sinusoidal signal (100 Hz to 10 MHz)
• We measure the capacitive current with an AC meter (90 degree phase shift)
=> i
cap/v
ac=C
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 18
When a voltage Vg is applied to the MOS Gate, part of it appears as a potential drop across oxide and the rest of it appears as a band bending Vs in silicon:
S ox
SC SC
ox
g V
C V Q
V
V
S
ox SC SC
ox
g V
C V Q
V
V
M O S V g
V ox V SC
Oxide and Silicon have capacitor behavior
Measurement of capacitance in Ideal MOS Structure
V
GV
OXV
SX V(X)
-t
OX0
SC is grounded,
so V
SC=VS
• Oxide capacitance : as a parallel‐plate capacitor
• We can also write :
F/cm 2
ox ox ox
C d
) (
)
( G S
M S
G M OX
ox M
V V
d
dQ V
V Q V
C Q
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 20
• Semiconductor (silicon) capacitance
S M S
SC SC
dV Q d
dV Q d
oltage
C ( ) ( )
SC) across
v (
SC) in
(charge
S M S
SC SC
dV Q d
dV Q d
oltage
C ( ) ( )
SC) across
v (
SC) in
(charge
Measurement of capacitance in Ideal MOS Structure
• Global capacitance of the structure :
• If we combine the 3 relations above :
G SC G
MOS M
dV dQ dV
C dQ
G SC G
MOS M
dV dQ dV
C dQ
series in
connected es
capacitanc 2
1 1
1
SC ox
MOS C C
C 1 1 1 2 capacitanc es connected in series
SC ox
MOS C C
C
M O S V g
V ox V SC
Pr. Ph.Lorenzini 22
• Total charge in SC depends on different regimes
2 types of charges, fixed and mobile/free:
dep S
SC Q Q
Q SC free carriers charges fixed charges Q S Q dep Q free carriers charges fixed charges
S dep S
S S
dep S
S sc
SC dV
dQ dV
dQ dV
dQ dQ
dV
C dQ
( )
S dep S
S S
dep S
S sc
SC dV
dQ dV
dQ dV
dQ dQ
dV
C dQ
( )
Semiconductor capacitance can be written as :
Measurement of capacitance in Ideal MOS Structure
From MOS Capacitor to CMOS inverter
dep S
SC Q Q
Q SC free carriers charges fixed charges Q S Q dep Q free carriers charges fixed charges
dep S
S sc
SC C C
dV
C dQ S dep
S sc
SC C C
dV
C dQ
Semiconductor capacitance can be written as :
• Total charge in SC depends on different regimes
2 types of charges, fixed and mobile/free:
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 24
• Summary: MOS capacitor is equivalent :
- of 2 capacitors series connected, C
OXand C
SC- C
SCis equivalent of two capacitors
- the two are variable and be view as 2 capacitors in //
C ox C sc
C ox
C s C dep
Measurement of capacitance in Ideal MOS Structure
Conclusion: the whole capacitance of MOS structure is
function of bias conditions or operating regime through
C SC
metal kT S
V S e
eV kT D
SC SC
Q
kT eV p
e n kT
e eV L
e
Q kT
S S FI
21
0 0 )
2 (
1
2 1
metal kT S
V S e
eV kT D
SC SC
Q
kT eV p
e n kT
e eV L
e
Q kT
S S FI
21
0 0 )
2 (
1
2 1
• Accumulation Regime: V S <0 ie V G <0
2 2 0
eV kT
D SC
SC
e
SeL Q kT
2 2 0
eV kT
D SC
SC
e
SeL Q kT
S g
ox SC
s
SC SC C V V
kT Q e
kT e dV
C dQ
2 2
Pr. Ph.Lorenzini 26
Capacitance of MOS structure
• Accumulation Regime: V S <0 ie V G <0
S ox g
MOS
S ox g
SC ox
MOS
V V
kT e C
C
V V
kT e C
C C
C
2 1 1
1
1 2 1
1 1
From MOS Capacitor to CMOS inverter
metal kT S
S eV eV kT
D SC
SC
Q
kT e eV
p n kT
e eV L
e
Q kT
S S
21
0
0
1
2 1
C ox
C sc
• Accumulation Regime: V S <0 ie V G <0
kT=26 meV, in accumulation regime V S is around ‐0,3 V to
‐0,4 V, as soon as V G <‐1 to ‐2 V, so we can simplify to:
S ox ox g
MOS
V V C
kT e C
C
2 1 1 1
1
S ox ox g
MOS
V V C
kT e C
C
2 1 1 1
1
metal kT S
S eV eV kT
D SC
SC
Q
kT e eV
p n kT
e eV L
e
Q kT
S S
21
0
0
1
2 1
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 28
Capacitance of MOS structure
• Flat Band: V S =0 V ie V G =0 V (warning : ideal structure!!!!!)
Analytical computing :
D SC
SC fb L
C
) (
D SC
SC fb L
C
) (
A SC SC
ox ox
ox
D SC ox ox
MOS ox
N e
d kT L
d fb
C
) (
A SC SC
ox ox
ox
D SC ox ox
MOS ox
N e
d kT L
d fb
C
)
(
• Depletion regime and weak inversion
Fi
V S 2 0 V S 2 Fi 0
2 0
2 2
2 1 1
S A SC S dep
D SC
SC eN V Q
kT eV eL
Q 2 kT 2 2 1 2 0
1
S A SC S dep
D SC
SC eN V Q
kT eV eL
Q kT
dep SC S
SC A
S SC
SC V W
eN dV
C dQ
2
1
2 dep
SC S
SC A
S SC
SC V W
eN dV
C dQ
2
1
2
W
depInsulator
Pr. Ph.Lorenzini 30
Capacitance of MOS structure
• Depletion regime and weak inversion
Fi
V S 2 0 V S 2 Fi 0
dep SC S
SC A
S SC
SC V W
eN dV
C dQ
2
1
2 dep
SC S
SC A
S SC
SC V W
eN dV
C dQ
2
1
2
) /
2 ( 1 )
( 2
A SC
g ox
ox
dep SC
ox ox
ox
MOS C V eN
C W
d depletion
C
) /
2 ( 1 )
( 2
A SC
g ox
ox
dep SC
ox ox
ox
MOS C V eN
C W
d depletion
C
From MOS Capacitor to CMOS inverter
• Strong inversion V V S S 2 2 Fi Fi
metal kT S
V S e
eV kT D
SC SC
Q
kT eV p
e n kT
e eV L
e
Q kT
S S FI
21
0 0 )
2 (
1
2 1
metal kT S
V S e
eV kT D
SC SC
Q
kT eV p
e n kT
e eV L
e
Q kT
S S FI
21
0 0 )
2 (
1
2 1
2 ( 2 2 ) 0
kT V e
D SC
SC
FI S
eL e Q kT
2 ( 2 2 ) 0
kT V e
D SC
SC
FI S
eL e Q kT
kT V e
s D SC SC
FI s
L e dV
C dQ 2
) 2 (
2
ox SC
ox
MOS C C C
C
1 1 1
1
p type SC
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 32
Capacitance of MOS structure accumulation dep
???
p type SC
Strong inversion
D SC ox ox
ox MOS
L d
fb C
) (
D SC ox ox
ox MOS
L d
fb C
) (
S ox g
MOS
V V
kT e C
C
2 1 1
1
dep SC ox ox
ox MOS
W d
depletion C
) (
dep SC ox ox
ox MOS
W d
depletion C
)
(
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 34
Capacitance of MOS structure
• Strong inversion:
Which mechanism governs the onset of strong inversion layer?
P type SC : we must create electrons at oxide/SC interface. Where they come from?
From Metal : NO because oxide barrier
From SC (neutral region) : NO minority carriers (e‐)
Only one solution: thermal (or optical) generation
• Strong inversion:
• Thermal generation?
• N°1 :In the space charge + dissipation of charge by electric field
• N°2 : In the neutral region
First mechanism dominates but it’s a slow one.
recombination +
+ + +
+ p++
EF
space charge
zone diffusion zone
0 W
n
p+ SiO2
n+
metal contact semitransparent
metal
(a)
(b)
(c)
Pr. Ph.Lorenzini 36
• Strong inversion
• Which Delay time to create strong inversion layer ?
m i th
g n
2
m i th
g n
2
A S
th N
g th S N A
g m
i A
S n
N
2 m
i A
S n
N
2
Strong inversion limit: n S = N A
More realistics
mi A
S
n
N
1 - 10
mi A
S
n
N
1 - 10
From MOS Capacitor to CMOS inverter
Capacitance of MOS structure
Shockley-Read equation
Si:
n
i=10
10cm
-3N
A=10
15cm
-3
s=1s !!
m=10
-5s
• When we measure C(V) , results depend on YES or NO, we give enough time to create this layer
• YES: we measure capacitance du to inversion layer
• NO : Depletion layer preserves the neutrality of the system with an increase of its width . The limit is the breakdown of the
semiconductor
Results are frequency dependant
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 38
3 cases :
Low frequency +
Slow ramp Vg
x Q
x Q
High frequency +
Slow ramp Vg
x Q
High frequency +
High ramp Vg
Capacitance of MOS structure: strong inversion
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 40
• minimum capacitance (HF):
A sc
i A
ox
e N
n N
kT C
C
min 2) / ln(
4 1
1
) / 4 ln(
2 2
max 2 A i
A sc Fi
A
sc
N n
N e
kT W eN
BF
HF
Capacitance of MOS structure: strong inversion
• 2 factors modify « ideal » structure of MOS capacitor.
• The Charges in oxide and/or Charges at interface Oxide – SC.
• The Difference between the work function of the Metal and the SC
Influence on the threshold voltage V T of
the structure.
Pr. Ph.Lorenzini 42
• Distribution of charges in the oxide :
• Mobile ionic charge
• Oxide traped charge
• Fixed oxide charge
• Traped charge at Si-SiO
2interface
K
+Na
+Ionic mobiles
- - - - -
+ + + +
traped
+ + + + +
x x x x
SiO 2
SiO x Si
Depending on their position in the oxide, the charges will influence more or less on the electron population below the gate.
From MOS Capacitor to CMOS inverter
MOS capacitor :oxide charge
• Effect of a sheet charge of areal density Q within the oxide layer of an MOS capacitor:
Oxyde
x
(x)
V g =0V
Si Metal
0 x 1 Q
x
(x)
V g =V fb
d ox -Q
Q
Oxide charges are
compensated with charges in Metal AND SC.
If Vg=Vfb, charges in SC must be zero. Only Metal
« DO the job »
ox ox ox
ox ox
g
C
Q d
xQ x
V
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 44
• The effect is maximum when the charges are located at the interface oxide - SC, ie Q
ox=Q
SS(and no effect if Q
oxclose to Metal)
d ox
x
ox ss
g C
V Q
FB ox
S ox
S
g V
C V V Q
V
( )
)
( FB
ox S ox
S
g V
C V V Q
V
( )
) (
It is a common practice to define an equivalent oxide charge per unit area Q ox located at the oxide – silicon interface (ie Q SS ):
MOS capacitor :oxide charge
• Work function difference non zero oxide field.
• Even when V g = 0 V, structure show a band bending
e
Depletion zone
A gate voltage must be applied to restore the flat band
condition V FB = M – S = MS : this voltage is called Flat
Band voltage V FB
Pr. Ph.Lorenzini 46
• Work function difference.
• Example: polysilicon n + gate on p-MOS
silicium
poly e
n
poly
e silicium
n
fi g
Silicium
SC
e
E
2
fig Silicium
SC
e
E
2
) ln(
56 .
2 0
ia fi
poly g
MS
n
N e
kT e
E
0 . 56 ln( )
2
ia fi
poly g
MS
n
N e
kT e
E
From MOS Capacitor to CMOS inverter
Work function difference
• Taking into account both Oxide charges and work-
function difference, the global flat band voltage can be written as:
ox ox MS
FB C
V Q
ox ox MS
FB C
V Q
Warning: this is the voltage we have to apply
on the gate to restore de flat band condition .
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 48
Threshold voltage
• Key parameter for behavior understanding of transistor
• Many definitions (same results!):
• n
S= N
A• V
s= 2
fi• …
V T is simply the applied gate voltage when the surface potential or band bending reaches 2 FI and the silicon charge is equal to the bulk depletion charge for that potential
FB Fi
OX
Fi A
SC Fi
S g
T V
C V eN
V
V
4 2
) 2
(
FB Fi
OX
Fi A
SC Fi
S g
T V
C V eN
V
V
4 2
) 2
(
(we suppose here that no bias of bulk is present no
body effect) V
T
V
OXV
S=2
FIX V(X)
-t
OX0
) 0 ( V
FB
(from slide 16)
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 50
• Substrate sensitivity - Body Effect
• In general the MOS devices have a common silicon substrate
substrate voltage is equal for all transistor.
• BUT when multiple NFETs (or PFETs) are connected in series in a circuit, they share a common body (the silicon substrate) but their sources do not have the same voltage. We must
introduce a coefficient that accounts for this effect :
Threshold voltage
=0
>0 +++++++
<0
>0 +++++++
+ + + - - -
++
One part of Gate voltage is no more used to create inversion layer but just to compensate the extra depletion width V
Twill increase
+
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 52
• The new threshold voltage taking account the body effect can be written as:
• The substrate sensitivity as:
• Of course substrate bias have to be reverse to prevent current flow
ox T
ox
SB Fi
a sc SB
ox SB
T
C V Q
C
V eN
dV dQ C
dV
dV
1 / 2 ( 2 ) et
ox T
ox
SB Fi
a sc SB
ox SB
T
C V Q
C
V eN
dV dQ C
dV
dV
1 / 2 ( 2 ) et
Fi SB Fi
T
T
V V
V
T V
T0 2
Fi V
SB 2
Fi
V
0 2 2
ox SC A
C eN
2
ox SC A
C eN
2
Threshold voltage
The effect of (reverse) substrate bias is to widen the bulk depletion region and raise the threshold voltage:
• The back contact acts as a back Gate
• We can tune V T !
V V d
FB ox
0 A 200
0 2 4 6 8 10
0,8 1,0 1,2 1,4 1,6
1,8 Na = 1E16 cm-3 Na = 3E15 cm-3
T
Substrate bias voltage V
SB(V)
Thr eshold volt ag e (V)
MOS-FET
TRANSISTOR
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 56
Graphical summary of the major processing steps in the formation of a MOSFET Transistor
http://www.youtube.com/watch?v=dR-Qtv-7uWI
Stockage time ?
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 58
Linear regime
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 60
Saturation regime
Effective length of canal decreases from L to L’
• L, canal length( y oriented)
• W, canal width(z oriented)
• V, voltage in the canal (f(y))
• V(y=0) = V(source) = V
s= 0 V
• V(y=L) = V (drain) = Vds
• Vg, gate voltage
• -V BS , body voltage
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 62
Schematic MOSFET cross section (Taur)
• Analytical solution we simplify the model:
• Charge sheet approximation (x
i=0):
• We assume all the inversion charges are located at the silicon interface without any thickness
• No potentiel drop across this layer
• No band bending across this layer
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 64
First step: calculation of inversion layer charge function of Vg
) ) ( 2
( 2
) (
2 eN V y eN V y
W eN
Q
dep
A M
A
SC S
A
SC
Fi
)) ( 2
( ))
( (
) ( )
( y Q y C V V V y C V V V y
Q
sc
métal
ox g
FB
S
ox g
FB
Fi
) ) ( 2
( 2
)) ( 2
( V V V y eN V y
C Q
Q
Q
inv
sc
dep
ox g
FB
Fi
A
SC
Fi
2 1
)) ( 2
( )) 2
( 2
) (
(
e
y V N
e
y V V
V C e
Q e
Q e
y Q
n
S inv sc dep ox g FB Fi A
SC FiCharge sheet approximation
• Current density in the channel can be caused by diffusion and drift components
• Current is simply given (integration over channel section)
dy dn q
qµ kT dy
y qnμ dV
=
J
n 0( )
0
i i
i i
x x
DS
x W
x W
DS
dy dx dn q
qµ kT W
dy dx qn dV
W I
dy dx dn q
qµ kT dz
dy dx qn dV
dz
= I
0 0
0 0
0 0
0
0 0
0
There is a sign change because we want I
DS>0 in –y direction
• The previous relation can be rewritten
• If we remember that:
• Current expression can be found
• And so, by integrationg from y=0 to y=L and as current is independant of y:
Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 66
xi xiDS
qndx
dy d q Wµ kT dy qndx
=W dV
I
0 0
0 0
xiinv
q n x y dx
Q
0( , )
dy V dQ q Wµ kT dy
V dV Q
Wμ
=
I
DS inv n( )
)
(
00
Charge sheet approximation
((0))) (
) 0 0 (
0
L Q
Q inv
L V
V inv
L DS
inv inv
q dQ dV kT
Q
=W dy
I
