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GIMIX 64K BYTE CMOS STATIC RAM BOARD W/BATTERY BACK-UP for the SS-50/SS-50C bus

Using the latest in memory technology, the GIMIX 64K BYTE CMOS STATIC RAM BOARD combines the best features of previous memory boards on one board.

FULLY STATIC MEMORY with its inherent low soft error rate and freedom from alpha-particle induced errors. No complicated refresh timing or clocks required for data retention. Fully compatible with any of the 6800/6809 DMA techniques.

HIGH SPEED 20Oos. memorys for guaranteed operation at 2MHz. with no wait states or clock stretching required.

ULTRA-LOW POWER CMOS RAM requires less than 1/4 AMP (250 Ma.) at 8V. for a fully populated 64K BYTE board. 'Less power supply loading and heat generation for cool, efficient operation.

NON-VOLATILE using an on-board nickel-cadmium battery. The board retains data even with system power removed. With the battery fully charged, the contents of the memory remain intact for a minimum of 21 days.

HIGH DENSITY permits greater memory expansion to meet the needs of todays sophisticated, multi-user/multi-tasking operating systems.

ADDRESSABLE in two 32K sections that have their own decoding for both the regular and extended (SS-50C) address lines. Each section can be addressed to any 32K boundary in the address range (1M BYTE with extended addressing). The 32K sections are divided into four 8K blocks that can be individually enabled or disabled. Disabled sections do not occupy any address space.

RELIABLE like all GIMIX products, the 64K BYTE CMOS STATIC RAM is designed with reliability in mind. Series damping resistors, a fully gridded power and ground layout, and generous power supply decoupling, all contribute to reliability and data integrity. An unsafe voltage detect circuit inhibits writes to the board, when the 8V. supply falls below a preset level, to prevent loss of data during the transition between system and battery power.

The GIMIX 64K BYTE STATIC RAM BOARD is ideally suited to a wide variety of applications.

Its h~gh density and ultra-low power consumption make it possible to greatly expand systems with a few available bus slots and limited power supply capabilities.

The battery back-up feature is useful where data loss due to power failure cannot be tolerated, or as a replacement for disk or tape storage where conditions such as environment prohibit their use. Since the entire board can be hardware write protected by a switch located at the top of the board, it can also be used to emulate PROM or ROM memory. This is especially useful during firmware developement where frequent software changes must be made.

When the board is used in conjunction with a device such as the GIMIX MISSING CYCLE DETECTOR BOARD, which monitors the A.C. line and generates an interrupt when a power failure occurs. critical data can be stored and system integrity maintained during either expected or unexpected power outages.

ADDRESSING

The board is addressed as two separate 32K blocks. DIP-switches are used to select the base address of each block, the extended address (55-SOC) for each block if required, and to enable or disable 8K sections within each block.

BASE ADDRESS SELECT (53)

The base address of each 32K block can be set to either $0000 (lower 32K) or $8000 (upper 32K). DIP-switch 53 sections 1 and 6, see figure 1, select the base address for blocks 1 and 2 respectively. A switch set ON (CLOSED) selects the lower 32K and a switch set OFF

(OPEN) selects the upper 32K.

8K SECTION ENABLES (53)

Each 32K block is divided, on even 8K boundaries, into four 8K sections. Each 8K section can be individually enabled or disabled as required. DIP-switch 53 sections 2, 3~ 4, S, 7, 8, 9, and 10, see figure 1, enable and disable 8K sections as shown in the following table.

SECTION ADDRESS

BLOCK SWITCH UPPER 32K LOWER 32K

1 53-2 $EOOO-$FFFF $6000-$7FFF

1 53-3 $COOO-$DFFF $4000-$SFFF

1 53-4 $AOOO-$BFFF $2000-$3FFF

1 S3-S $8000-$9FFF $OOOO-$lFFF

2 53-7 $EOOO-$FFFF $6000-$7FFF

2 53-8 $COOO-$DFFF $4000-$SFFF

2 53-9 $AOOO-$BFFF $2000-$3FFF

2 53-10 $8000-$9FFF $OOOO-$lFFF

A switch set ON (CLOSED) enables the associated 8K section.

A switch set OFF (OPEN) disables the associated 8K section.

When an 8K section is disabled, the address space that it would normally occupy is available for other boards or devices in the system. This makes it possible to leave gaps in the address space for I/O devices, disk controllers, PROM/ROM, etc. On boards that are not fully populated, S6K versions for example, the switch corresponding to the unpopulated section of the board should be OFF (OPEN).

Unpopulated sections of the board will occupy .address space and cause possible buffer conflicts unless they are disabled.

S3

BLOCK I

I

UPPER/LOWER 32K SELECT

I

ON (CLOSED)=LDWER

BK ENABLES ON (CLOSED)= ENABLE

UL I ⁴

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-

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2

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8K ENABLES ON (CLOSED) = ENABLE

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-

- ^-

6 7 8 9 10

BASE ADDRESS SELECT

FIG. I

EXTENDED ADDRESSING (52)

Separate extended address decoding is provided for each of the two 32K blocks. The blocks can be set to the same extended address (bank), different" extended addresses, or extended addressing can be disabled for one or both blocks. DIP-switch 52 sections I and 6, see figure 2, enable or disable extended address decoding for blocks 1 and 2 respectively. A switch set ON (CLOSED) enables extended address decoding for the associated block. A switch set OFF (OPEN) disables

extended address decoding for the associated block.

DIP-switch 52 sections 2, 3, 4, and 5 correspond to extended address lines A16, A17, A18, and A19. If textended address decoding for block 1 is enabled (52-1

=

ON), these switches must be set to the binary equivalent of the desired bank address ($0 through $F). A switch set ON (CLOSED) corresponds to a "1" in that bit position. A switch set OFF (OPEN) corresponds to a "0". If extended address decoding for block 2 is enabled (S2-6 = ON), DIP-switch 52 sections 7,

8, 9, and 10 which also correspond to extended address lines Al7 through Al9 respectively, must be set to the desired bank address for

block 2. •

52

EXTENDED ADDRESS ENABLE

[ ]

ON (CLOSED)= ENABLE XON

B

AI6 [ ]

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EXTENDED ADDRESS C

SELECT

AI7

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AI9 [ ]

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EXTENDED ADDRESS SELECT

ADDRESSING EXAMPLES Figures 3 configurations.

and 4

FJG.2

show illustrate two possible address

Figure 3 shows the proper switch settings for 56K of contiguous memory from $0000 to $DFFF, with extended addressing disabled. Note that switch S3 section 7, which disables the upper 8K section of block 2, must be OFF (OPEN), even if no memory chips are installed This is the normal configuration for a 56K system using FLEX~ or OS-9~ level 1.

Figure 4 shows the proper switch settings for addressing the board as two 32K blocks, both addressed from $0000 to $7FFF, on two separate banks, 0 and 1.

ADDRESSING EXAMPLES

52 53

XON

_OFF ^{BLOCK I BLOCK 2}

AI6

X 2 50000- S 7FFF S8000- SDFFF

EXTENDED

AI7

X 3 (SEOOO-SFFFF

ADDRESS

AlB

X

4

DISABLED)

DISABLED

AI9 X 5

XON

_OFF

6 UL 4

3 2

I UL 4

3 2 I

AI6

X

7

AI7 X B

^{0 0}

o

^{0 0}

o

^{0 0 0 0}

N N N N N F F N N N

AlB

X

9

_{F F}

AlB X

10

I

^{2 3 4}

5 S 7 a 9

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DONT CARE

AG. 3:56K CONTIGUOUS MEMORY SOOOO-SDFFF NO EXT. ADD.

S2 S3

XON

ON

BLOCK I BLOCK 2

BLOCK I

AI6

OFF 2

BANK:t$O

AI7

OFF 3

SOOOO-S7FFF SOOOO-S7FFF

AlB

_OFF 4

AI9

^OFF 5

UL 4

3 2

I UL 4

3 2

I

XON

ON

S

BLOCK· 2

AIS

^ON

7 0

0

o 0 0 0

0

o 0 0

BANK~I

AI7

_OFF

,a

_{N N N N N}

N

^N

N N

^N

Ala

OFF

9

AI9

^OFF .10

I

2 3 4 5

6 7 8 9

10

FIG. 4: TWO SEPARATE 32K BANKS SOOOO-$7FFF BANKS 0 a ^I

WRITE PROTECT WRITE PROTECT SWITCH (Sl)

The write protect switch (Sl), located at the upper right corner of the board, disables the write circuitry and prevents the system from writing data to the memory. When the switch is moved to the left position (toward the memory array) the board is write enabled and data can be written to as well as read from the memory. When Sl is moved to the the right, the board is write protected and data cannot be written to the memory.

BATTERY BACK-UP

The on-board Nickel-cadmium battery provides the power required to retain data in the CMOS memorys when system power is removed. Data remains intact for a minimum of 21 days with a fully charged battery.

The battery is trickle charged whenever system power is applied to the board and the battery ON/OFF jumper is in the ON position. The transition between system and battery power is automatic. An adjustable unsafe voltage circuit monitors the +8V bus and inhibits memory accesses whenever the bus voltage falls below a preset safe level. This prevents false writes to the memory when the system bus is in an undefined state during power-up and down.

BATTERY ON/OFF JUMPER (JA-2)

JA-2 provides a means for disconnecting the battery when battery operation is not desired or when parts are removed from or installed in the board. Figure 5 shows the proper positions of the jumpers for battery ON and OFF.

CAUTION: When the battery ON/OFF jumper (JA~2) is in the ON position, power is applied to the memory array and the CMOS decoders at all times, even when the board is removed from the system. Before removing or installing parts at these locations the battery ON/OFF jumper must be placed in the OFF position to prevent possible damage to the parts. Use caution wh~n handling the board to prevent shorting the battery terminals together or to other parts of the circuit or damage to the battery or the board may occur.

VOLTAGE THRESHOLD ADJUSTMENT (R2)

The voltage at which the unsafe voltage detector activates is determined by the setting of trimmer resistor R2. This adjustment is factory set at a voltage just above the point where the on-board voltage regulator falls out of regulation, approximately 7 volts, and should not need readjustment under normal circumstances.

NOTE: In certain 55-50 systems with marginal power supplies, the bus voltage may be too low to allow proper operation of the board. These systems will require modifications to their power supplies to provide sufficient voltage. The nominal +8V bus voltage should be somewhat above the setting of the unsafe voltage threshold to provide for normal voltage fluctuations.

(0 0) (00)

BATTERY ON

JA-2

FIG. 5

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⁰⁴ GIMIX INC .

R7 <C-_J\AR31v-_ _ _ _ _ _ -®f-lQ~2r---d-AI--:-G~+7---1L-'y_~: ^2-1-81 LOGIC DIAGRAM 1~----""

64K STATIC RAM PROPRIETARY MAT'L,ALL RIGHlS

RESERVED 0 1982 GIMIX INC I L2400530

COMPONENT LAYOUT

IF S3-1 IS OFF, USE ADDRESSES LABLED I U IF S3-6 IS OFF, USE ADDRESSES LABLED 2U

IF S3-1 IS ON, USE ADDRESSES LABLED I L IF S3-6 IS ON,USE ADDRESSES LAB LED 2 L