MOS-DEGRADATION IN INPUT AND OUTPUT STAGES OF VLSI-CMOS-CIRCUITS DUE TO ELECTROSTATIC DISCHARGE

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MOS-DEGRADATION IN INPUT AND OUTPUT STAGES OF VLSI-CMOS-CIRCUITS DUE TO

ELECTROSTATIC DISCHARGE

X. Guggenmos

To cite this version:

X. Guggenmos. MOS-DEGRADATION IN INPUT AND OUTPUT STAGES OF VLSI-CMOS-

CIRCUITS DUE TO ELECTROSTATIC DISCHARGE. Journal de Physique Colloques, 1988, 49

(C4), pp.C4-303-C4-306. �10.1051/jphyscol:1988463�. �jpa-00227961�

MOS-DEGRADATION IN INPUT AND OUTPUT STAGES OF VLSI-CMOS-CIRCUITS DUE TO ELECTROSTATIC DISCHARGE

X. GUGGENMOS

Siemens AG, Corporate Research and Development, Microelectronics, Otto-Hahn-Ring 6, 0-8000 Miinchen 83, F.R.G.

Abstract

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MOS transistors have been used as sensors to study non- catastrophic effects of electrostatic discharges in input stages with protection circuits as well as output stages of VLSI circuits. Stress voltages far below the destructive level were found to cause both, severe threshold voltage shifts and transconductance degradation. As a result a reduction in circuit reliability is observed. To prevent degradation, selected and improved ESD protection circuits have to be used. It will be shown that the standard criterium for ESD-hardness needs to be extended in order to account for these requirements.

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INTRODUCTION

Micron and sub-micron CMOS-Devices are known to show an increased suscepti- bility to excessive voltages and currents caused by electrostatic discharge (ESD) or similar electrical overstress /I/. Consequently the ESD-hardness of the input and output stages has to be improved. The accepted characterization criterium for the ESD-hardness is given by the critical voltage V,,L= of the ESD test model (e.g. Human Body Model

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HBM, Machine Model

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^{MM) at which}

significant leakage current or maifunction occurs /2/. This test will only consider catastrophic failures caused by single discharge pulses. Soft damage, such as threshold voltage and transconductance degradation in the CMOS devices will remain undetected /3/-/5/.. However, this unrevealed ESD damage may be a serious limitation of device reliability. This issue is expected to become even more relevant in scaled down MOS devices with reduced gate oxide thick- nesses and increased hot-carrier stress during operation.

In this work we have studied to which extent non-catastrophic effects of ESD- stress will cause degradation of the MOS devices of input and output stages.

In CMOS input stages ESD protection circuits are integrated to limit the vol- tage at the susceptible MOS-gates. Their efficiency to prevent degradation has been investigated. To account for ESD effects on output stages, the driver performance of output transistors has been studied.

We will provide experimental evidence that ESD stress will cause significant device degradation and reduce device reliability. Protection circuits selected with a high ESD-hardness according to the standard tests were found to be insufficient in some cases.

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TEST STRUCTURES AND MEASUREMENT SETUP

For the electrical characterization of input stages special test structures consisting of an input protection circuit combined with a typical CMOS input inverter were used. The effects on output stages were studied at single driver transistors without additional protection circuits.

An especially developed ESD-tester enables a combination of a two pin ESD- stress and a full DC-characterization of the test inverter. In addition to the

Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988463

JOURNAL DE PHYSIQUE

standard characterization (leakage current, malfunction, etc.), MOS parameters of the individual transistors of the input inverter such as threshold voltage

(Vth) and transconductance (g,) are determined after each ESD-stress.

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RESULTS AND DIlSCUSSION

3.1

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MOS DEGRADATION DUE TO ELECTROSTATIC DISCHARGE

To determin the ESD-hardness of an input stage according to the standard test the voltage of the ESD-model is stepwise increased. Fig. 1 illustrates the Vth shift and the g, degradation of the NMOS-transistor of the input inverter during a step strtsss test with the HBM. Note that only for stress voltages exceeding the critical voltage (V,,a=) of -4600 V a significant leakage current occurs. However, much below this value starting at a voltage of about -2000 V, the MOS c:haracteristics are largely degraded. Since the observed Vth shifts are negative in all cases, it is concluded that positive charge trapping in the SiOz has occured. The observed Vth shift and the changes in the transconductance indicate that voltage spikes pass the protection circuit and reach the gate which are not high enough to cause gate oxide rupture but will cause a current injection into the gate oxide.

Fig. 1 Threshold voltage shift (a) and degradation of the transconductance (b) of the NMOS-transistor of an input inverter with protection circuit (PC) vs. stress voltage (Human Body Model 100 pF, 1.5 kohm)

Protection circuits with different elements and layout variations have been compared. The protection circuit b) of Fig. 2 has a higher critical voltage V,,rt of -3900 V compared to -2600 V of structure a), but already at a voltage of about -400 V a significant shift of the threshold voltage of the PMOS- transistor takes place. Up to a voltage of about -2300 V structure a) shows no significant degradation. Accordingly, structure a) would be the better choice.

This result demonstrates that the standard ESD specification according V,,ir can be misleading with respect to device degradation.

Fig. 2 Threshold voltage shift of the PMOS-transistor of an input inverter for two different protection circuits vs. stress voltage (Human Body Model 100 pF, 1.5 k0hm)

output transitor. In this case the ESD stress voltage is applied between the drain and the source of the NMOS-transistor (gate floating). Compared to the degradation of input transistors, a similar degradation behaviour is observed. For this type of stress there are two possible mechanisms for the degradation: The high vertical electrical field between drain and gate may induce a transient gate oxide current (loading the floating gate) and/or the high lateral electrical field at the drain edge may generate hot-carriers. /3/

Fig. 3 Threshold voltage shift (a) and degradation of the transconductance (b) of the NMOS-transistor of an output inverter without protection circuit vs. stress voltage (Human Body Model 100 pF, 1.5 kOhm,VD/Vs)

3.2

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EFFECTS ON CIRCUIT RELIABILITY

Now we will concentrate on ESD induced longterm effects. At first the influ- ence of single ESD-events on the hot-carrier degradation behaviour of input transistors is studied. Fig. 6 shows the Vth shift and the g, degradation of an NMOS-transistor due to hot-carrier stress (Lerrrl pmr VD=7 VI Vo=3.7 V).

After 128 seconds a single ESD-stress (Machine Model, 50 pF/O Ohm/-500 V) is performed. In this case, the hot carrier stress causes a negative Vth shift and the negative shift due to ESD stress accumulates. After a brief delay, the g, degradation is shiftet to a higher level. In any case the additional ESD- stress reduces the device lifetime because a specified degradation level is exceeded earlier. These findings are paralleled by results reported recently in the case of output transistors /3/.

t i m e ( s e e )

lo0 10' 10'

t i m e I s e c )

Fig. 4 Threshold voltage shift (a) and transconductance degradation (b) of an NMOS-transistor due to hot carrier stress (VD=7 V, Vc=3.7 V) with an additional ESD-stress after 128 sec.

Next the effect of a multiple ESD-stress is discussed. Fig. 5 shows the Vth shift caused by an increasing number of discharges with an amplitude far below the critical voltage (compare Fig. 1). The degradation caused by each single ESD event accumulates resulting In a large total Vth shift. The number of discharges resulting in a functional failure can be estimated from this curve.

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Both experiments show that the degradation caused by ESD-stress reduces the lifetime of the MOS devices due to cumulative effects. Even low level ESD events have to be avoided in order to maintain circuit reliability.

number oY ESD p u l s e s

Fig. 5 Threshold voltage shift of the NMOS-transistor of an input inverter with protection circuit vs.

number of discharges with a constant amplitude (Human Body Model 100 pF

,

-1500V, VIN/VSS)

a f t e r 3 5 0 h

I

t i m e a f t e r E S D - s t r e s s l h l

Fig. 6 Annealing behaviour of the threshold voltage shift vs. time after the initial ESD-stress at a elevated temperature of 140 OC

Further evidence of the importance of the results mentioned above with respect to longterm effects was found in the annealing behaviour of ESD induced degra- dations. Fig. 6 sbows the annealing behaviour of the threshold voltage shift of an NMOS-transistor which was caused by a single ESD-event. Even after 350 hours at an elevated temperature of 140 OC about 81% of the initial shift of 430 mV remains. It this therefore reasonable to assume that the relaxation of ESD damage is not fast enough to relief from degradation effects under normal operating temperatures.

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CONCLUSIONS

It was shown that MOS devices of input/output stages degrade significantly at stress voltages far below the destructive level when unsuitable protection circuits are used. Since the observed Vth shifts and g, degradation alter trigger voltages and switching times of the input/output stages, the performance is reduced. Multiple ESD events as well as single ESD events in combination with hot-carrier stress during operation was found to accumulate.

As a result of this enhanced degradation, a reduction of circuit lifetime will occur.

As a consequence protection circuits have also to be selected and improved according to degradation effects. Standard characterization methods were found to be insufficient and in some cases, misleading. An extended characterization method has been developed. In test structures the MOS-transistors of input as well as output stages can be used efficiently as sensors for dangerous transient overvoltages. This method enables a proper selection and systematic improvement of protection circuits.

ACKNOLEDGEMENTS

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The author wish to thank Dr. Neppl and Prof. Dr. Ruge for supporting this work, and Dr. Schwalke, Dr. Kerber and Dr. Mazure for he1,pfull discussions.

REFERENCES:

/1/ Duwury, C., et al., Int. Reliability Physics Symp., Proc., 24 (1986)199 /2/ MIL-STD 883, Method 3015

/ 3 / Aur, C., et al., Int. Rel. Physics Symp., 24 (1986)199

/4/ Holmes, G.C., Electr. Overstress Electrostatic Discharge Symp., (1985)27 /5/ Amerasekera, E.A., Cambell, D.S., Quality and Rel. Eng. Int., 2 (1986)107