FPGA PROTOTYPING OF AN ASIP LDPC DECODER FOR THE DVB-T2 STANDARD Bertrand LE GAL and Christophe JEGO
IPB / ENSEIRB-MATMECA, CNRS IMS, UMR 5218 351 Cours de la Libération, 33405 Talence
Université de Bordeaux, France [email protected]
ABSTRACT
Forward Error Correction (FEC) consists in the addition of redundancy to the binary information sequence before the transmission. This redundancy allows the FEC decoder to detect and/or to correct the effects of noise and interference encounte- red during the transmission. An ASIP LDPC decoder compliant with DVB-T2 standard is presented in this paper.
1. INTRODUCTION
Application Specific Instruction set Processor (ASIP) is a promising approach to design an LDPC decoder that have to be compliant with multi-standards. Indeed, channel decoding is mainly dominated by dedicated hardware implementations that cannot easily support a large variety of digital communication standards and their evolutions. In this paper, an LDPC decoder architecture based on a publicly available MIPS processor core associated with a homogeneous matrix of processing units is introduced. The proposed architecture corresponds to an inter- mediate approach between the creation of an new application specific instruction-set processor and a fully dedicated decoder.
Rapid prototyping is an important step in the development and verification of complex digital communication systems. The goal is to replace time-consuming simulations based on abs- tract models of the system with real-time experiments under real-world conditions. New ASIP architectures corresponding to LDPC decoding algorithms have thus been implemented in a real-time platform using FPGA. The experimental setup is com- posed of onto a Xilinx Virtex-6 LX240T FPGA. The board is hosted on a 64- bit, 66MHz PCI bus that enables communication at full PCI bandwidth with a computer. A first implementation is dedicated to the decoding of the smallest WiMAX standard LDPC code : LDPC (567, 288). Another implementation has been done to demonstrate the potential of our ASIP architec- ture model to design a flexible efficient decoder that supports all the LDPC code configurations of the DVB-T2 standard [1].
The FPGA prototyping of the second implementation is descri- bed in the rest of the paper.
2. ASIP ARCHITECTURE FOR LDPC CODES
In order to address a large variety of LDPC codes specified in existing communication standards, we have designed a deco- ding architecture from an existing flexible softcore processor.
In order to achieve this, we have evaluated several publicly- available MIPS processor implementations and selected the Plasma processor. This processor is a public domain 32-bit soft
processor designed by Steve Rhoads which implements most of the MIPS-I (TM) instruction set [2]. As it has the same ins- truction set as a MIPS processor, it can be programmed from the same GNU tool chain. The designed architecture is com- posed of a Plasma microprocessor controller associated with a homogeneous Single-Instruction Multiple-Data (SIMD) matrix as detailed in Fig. 1. The SIMD matrix is a specialized form of parallel computing, whereP Processing Units (PUs) andP block memories compute and store independent data, respec- tively. All PUs are dedicated to a same specific function. As a horizontal layered decoding strategy has been adopted, a PU is defined in order to process the calculations for one parity check node of the bipartite graph. Moreover, a register file is dedicated to each PU to store local data. A duplication of the PUs pro- vides high computation rates and the SIMD matrix ensures the homogeneous property. The LLR transfers between PUs and block memories are done thanks to an interconnection network that performs the interleaveΠand deinterleaveΠ−1functions.
The communication between the microprocessor core and the SIMD matrix is provided by a system interface that manage data exchanges. The Plasma processor is a static scheduler for the iterative decoding process. It has to be programmed to exe- cute the corresponding firmware C-code. Note that eleven new instructions have been added to the Plasma CPU instruction set to increase its efficiency in terms of execution cycles.
The proposed LDPC decoder architecture enables to answer to two challenges :
– genericity : the computation capacity can be adapted in function of frame size, code rate and throughput, – programmability : the architecture can process LDPC
codes of different standards (WiFi, WiMAX and DVB).
More details about the ASIP decoder architecture can be found in [3].
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Fig. 1: ASIP LDPC decoder
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 10−11
10−10 10−9 10−8 10−7 10−6 10−5 10−4 10−3 10−2 10−1 100
Eb/N0
BER
2/5 1/2 3/5 2/3 3/4 4/5 5/6 8/9 9/10
Fig. 2: BER performance for 64K DVB-T2 LDPC codes measured on an ASIP architecture that contains64PUs
3. FPGA PROTOTYPING OF THE ASIP LDPC DECODER
Designing ASIP architectures for LDPC decoding is a chal- lenging issue. A good trade-off between hardware complexity and decoding performance can be achieved with a 5 bits quan- tization scheme for LLR values. Let us consider the following notation(x, y, z)wherex,y andzrefer to bit quantizations of LLRTn, messageTnmand messageEmn, respectively. An uniform quantized with 1 sign bit, 2 magnitude bits and 2 frac- tional bits has been selected for LLR values in all our investi- gations. It means that the fixed-version of the LDPC decoding algorithm and the decoder architectures have been implemen- ted with the(5, 7, 5)quantization scheme.The SIMD matrix of the ASIP decoder is made of 64 PUs and 64 blocks memory to exploit the long frame (64,800 LLRs) mode. Computational resources of the decoder take up 12,807 slice Flip-Flops and 41,094 slice LUTs. It means that the occupation rates are about 4% and 28% of a XC6VLX240T FPGA for slice registers and slice LUTs, respectively. It is well-known that the major bot- telneck of a LDPC decoder that has to support the long frame mode of DVB-T2 standard is the memory usage. It our design 336 BlockRAMs of 36kbits are necessary to support both the two frame modes and all the code rates. The clock frequency has been fixed at 80 MHz and 20 iterations have been chosen for the decoding process. It results in a throughput of 65 Mbps for the DVB-T2 (64,800 ; 32,400) LDPC decoder .
In order to validate the designed ASIP LDPC decoders, BER performance measures have to be carried out. For this reason, we have successively integrated the LDPC decoder into an experimental setup composed of a computer associated with the Virtex-6 FPGA ML605 evaluation kit. The LDPC encoder and an AWGN channel emulator are a software running on the computer. The intrinsic information generated by the channel emulator is truncated and rounded, and is sent to the FPGA board thanks to a PCI express interface. Frame by frame com-
munication is operated into our experimental setup. For the decoding process, the offset Min-Sum algorithm is employed.
20 iterations has been fixed for all the investigations. Measured BER performance obtained by our experimental setup for 9 code rates of the DVB-T2 standards over a Gaussian Channel using a BPSK mapping are plotted in Fig. 2. The ASIP decoder prototype shows quasi-identical performance when compared to fixed-point simulation. The error floor produced by the code rate 2/5 can only be solved by implementing a more robust simplified version of the BP algorithm. Fortunately, all other results are compliant with the DVB-T2 standard requirements.
4. CONCLUSION
In this paper, an LDPC decoder architecture based on a Plasma CPU associated with a homogeneous SIMD matrix of processing units has been introduced. Implementation results and BER performance measured demonstrate the potential of an ASIP approach based on an existing softcore processor. Note that our design approach also enables to implement an LDPC decoder that supports all the LDPC codes of one or more digital communication standards. During the DASIP demo night, an architecture framework for the generation of ASIP and different FPGA prototypes of the LDPC decoder will be presented.
5. REFERENCES
[1] DVB-T2, “Implementation guidelines for a second genera- tion digital terrestrial television broadcasting system (DVB- T2),” indraft ETSI TR 102 831 3 V0.10.00, Nov. 2009.
[2] S. Rhoads, “Plasma 32-bit softcore,” www.plasmacpu.no- ip.org, Tech. Rep., 2011.
[3] B. Le Gal and C. Jego, “Design of an ASIP LDPC decoder compliant with digital communication standards,” in EEE Workshop on Signal Processing Systems, SiPS 2012, Oct.
2012.
