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Self-optimisation using runtime code generation for Wireless Sensor Networks Internet-of-Things

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HAL Id: cea-01240865

https://hal-cea.archives-ouvertes.fr/cea-01240865

Submitted on 9 Dec 2015

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Self-optimisation using runtime code generation for

Wireless Sensor Networks Internet-of-Things

Caroline Quéva, Damien Couroussé, Henri-Pierre Charles

To cite this version:

Caroline Quéva, Damien Couroussé, Henri-Pierre Charles. Self-optimisation using runtime code gen-eration for Wireless Sensor Networks Internet-of-Things. Internet-of-Things Symposium at ESWeek, Marilyn Wolf (Georgia Tech) Jason Xue (City University of Hong Kong), Oct 2015, Amsterdam, Netherlands. �cea-01240865�

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www.cea.fr

Self-optimisation using runtime

code generation for Wireless

Sensor Networks

Internet-of-Things Symposium

ESWeek Amsterdam

Caroline Quéva Damien Couroussé Henri-Pierre Charles

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Intro Compilers

Classical Compiler architecture : GCC, LLVM, Java JIT

Driven by performance only Mono architecture

Not energy aware Not data dependent

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Intro Compilers

Future Compilers Architecture

Multi objective (execution time, power, thermal constraints) Multi-target (Heterogeneous multi SoC)

Data driven (dynamically)

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Definitions

Definitions

Static compilation “classical” binary code generation (gcc, icc, clang, ...)

Dynamic Compilation binary code generated at run-time (DBT)

JIT run-time dynamic compilation based on complex

Intermediate representation (Java, LLVM)

Innovations

Compilette : small binary code generator embedded into application able to optimize code depending on data sets

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Supported architectures

Architecture Stat. Features

ARM Cortex-A & M, [T2, VFP, NEON] SIMD, [IO/OoO]

STxP70 (STHORM / P2012) SIMD, VLIW (2-way)

K1 (Kalray MPPA) SIMD, VLIW (5-way)

PTX (CUDA Asm language) ARM32

MIPS 32 bits

MPS430 (TI) Up to < 1kB ram

Cross code generation supported (generate code for STxP70 from ARM Cortex-A)

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Intro Architectures examples

Example MSP430 LaunchPad Development Kit TI Micro controller 16-bit Ultra-Low-Power Microcontroller, 1KB Flash Example STM32 ST Micro microcontroller ARM Cortex-M 32 processor

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Code specialisation for arithmetic

Micro-controllers lack dedicated HW support for arithmetic computing

No FP unit

Sometimes, even no integer multiplier !

Illustration on floating-point multiplication, But applicable to many other operations !

Example : simple float multiplication, compiled for TI’s MSP430

1 f l o a t f m u l (f l o a t a , f l o a t b ) { 2 r e t u r n ( a * b ); 3 } 1 c 6 3 0 : mov r8 , r12 2 c 6 3 2 : mov r9 , r13 3 c 6 3 4 : mov r6 , r14 4 c 6 3 6 : mov r7 , r15 5 c 6 3 8 : c a l l #0 x c 9 d 6 ; < _ _ m u l s f 3 > 6 c 6 3 c : mov r14 , r12 7 c 6 3 e : mov r15 , r13 8 c 6 4 0 : mov r10 , r14

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Experiment

Reference

gcc’s generic version of the float multiplication routine Precision p = 24 1 /* t g c c */ 2 f l o a t f m u l ( f l o a t M , f l o a t X ) { 3 r e t u r n ( M * X ); 4 } Our approach

Runtime specialization of the float multiplication routine Precision p ≤ 24 1 /* t g e n : c o d e g e n e r a t i o n */ 2 f l o a t (*) ( f l o a t ) f m u l M; 3 f m u l M = g e n e r a t e _ f m u l _ c o d e ( M , p ); 4 5 /* t d y n : run the g e n e r a t e d r o u t i n e */ 6 f l o a t f m u l ( f l o a t X ) { 7 r e t u r n f m u l M( X ); 8 }

tgcc : execution time of gcc’s multiplication routine

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Performance indicators

tgcc : execution time of gcc’s multiplication routine

tgen : execution time of code generation

tdyn : execution time of the generated fmulM function

Speedup : s = tdyn tgcc (1) Overhead recovering : n = tgen tgcc− tdyn

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LibMul GeneralAlgo

FP Multiplication algorithm (X, Y)

Special case handling (denormal, zero, NaN) Unpack X, Y Mantissa multiplication Renormalize Repacking Rounding Optimization potential

Skip unecessary steps Value specialization

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Optimization principle

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Results

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Conclusion for multiplication

Demonstration that runtime code generation is a realistic goal

on a 16-bit micro-controller with only 512 bytes of RAM

Efficiency : 10× faster floating-point multiplication (when one of the two operands is a runtime constant) Greater genericity : extra flexibility on precision

50% increase performance on an IIR application (7 coeff.)

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Future works

In IoT

Generalize the arithmetic library

Other operators (trigonometry, . . . ) Network stacks

Other domains

High Performance Computing Power Consumption driven Code polymorphism

Online optimization Cryptography

Références

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