Generating a timing information (1-PPS) from a software deﬁned radio decoding of GPS signals

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Generating a timing information (1-PPS) from a software defined radio decoding of GPS signals

D. Rabus¹, G. Goavec-Merou¹, G. Cabodevila¹, F. Meyer³, J.-M Friedt¹

1FEMTO-ST Institute, Time and Frequency Department, Besan¸con, France

2OSU THETA, Besan¸con, France

e-mail: [email protected] https://github.com/oscimp/gnss-sdr-1pps

https://github.com/topics/gnss- sdr

May 28, 2021

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Software Defined Radio (SDR) implementation of a GNSS receiver

I SDR: minimize hardware to RF frontend (antenna, amplifier and frequency transposition) I Process all radiofrequency signal as software on complex values I+jQ

I Gain access to the raw IQ stream for incoming plane wave physical characteristics I Implement anti-jamming/anti-spoofing processing¹ in the SDR frontend (null-steering) I Full control of the complete signal processing chain

I Steer local oscillator to match incoming timing information

How to materialize timing information is 1-Pulse Per Second (1-PPS)?

1W. Feng, J.-M Friedt, G. Goavec-Merou, F. Meyer,Software Defined Radio Implemented GPS Spoofing and Its Computationally Efficient Detection and Suppression, IEEE Aerospace and Electronic Systems Magazine36(3), March

2021 andhttps://github.com/oscimp/gnss-sdr ^{2 / 11}

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Problem statement: SDR reception

ADC I ADC Q

FPGA GP-CPU position,velocity timesolution(PVT) interference

gnss-sdr GNU Radio

90^◦ 90^◦

I Two-channel Ettus Research B210/

AD9361 coherent radiofrequency frontend I Complex frequency transposition

I =s(t)·cos(ωLOt) ;Q=s(t)·sin(ωLOt) I ADC samples atf_s ≥1.023 MS/s both

channels (B≥2.046 MHz)

I FPGA pre-processing and continuous datastream transfer to general purpose central processing unit (GP-CPU) running free, opensource implementation of Global Navigation Satellite System (GNSS) decoder gnss-sdr

I compatibility with embedded applications, e.g. Raspberry Pi4 single board computer², 1.5 GHz quad-core inperformancemode I output: Position, Velocity, Timing (PVT)

solution

2G. Goavec-Merou, J.-M Friedt,Porting GNU Radio to Buildroot: application to an embedded digital network

analyzer, FOSDEM 2021, andgnss-sdrathttps://github.com/oscimp/oscimp_br2_external 3 / 11

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Problem statement: sample timing

time interval counterHP53132A U−Blox

receiver

hydrogen maser (inaccuracy

< 1e−12)

ADC

FPGA

gnss−sdr

AD9361 Raspberry Pi4

GbE USB3

ADC CK I, Q

Ettus Research B210

or

CPU CK top value

B210 external 10 MHz input

PLL ext 10 MHz steering

R&S SMA100A

1−PPS

1575.42 MHz 40 MHz

ref clock genuine GPS constellation

( )

40 MHz is 4-times multiplication of reference 10 MHz input of B210 HM always clocks the HP53132A counter and might clock the B210

I All communication between FPGA and GP-CPU hardware asynchronous

I Only ADC sampling time is knownassumingcontinuous datastream atfs

I Control the clock timing the AD9361 frontend ADC, which also clocks the FPGA

I Counter in the FPGA from 0 to fs−1

I Characterization: HP53132A time- interval counter clocked by Hydrogen Maser (HM) and reference 1-PPS from U-Blox NEO-M8P hardware receiver

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1-PPS output: open loop

-600 -400 -200 0 200 400 600 800

0 50000 100000 150000

UBlox-gnss 1-PPS (s)

time (s) I 50 hour long measurement

I time difference between a U-Blox NEO-M8P and the 1-PPS counter implemented in the FPGA I GP-CPU runninggnss-sdrand logging the time-difference

I B210 clocked by afree runningRohde & Schwarz SMA100A synthesizer set to nominal 10 MHz, I +11.1 ns/s=ppb drift removed, only the residue is displayed.

⇒objective: steer reference clock to keep 1-PPS within±100 ns boundary

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1-PPS output: closed loop

I Control SMA100A frequency with time-offset information fromgnss-sdrPVT solution I comparison between the “single solution” and the PPP solution

I sampling period is 1-chip or 20 ms, control loop every 500 ms

I select a sampling ratefs fractional integer of the 40 MHz clock (1.25 MHz=integer division by 32, 2 MHz=integer division by 20, 1.125 MHz=fractional division by 320/9) to avoid drifting 1-PPS

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1-PPS output: closed loop issue

1-PPS offset (us)

time (s)

500 ns=1/2 MS/s

I Source→Conditioner→ Acquisition/Tracking/Telemetry

→Observables→PVT

I Uselessresamplerfromf_s tof_s: misses one sample every 2³² I Make sure toPass Throughto

avoid 1/fs jumps every 2³²/f_s = 2147.5 s at 2 MS/s I (sampling rate 1.125 MS/s

⇒2³²/(1.125·10⁶) = 3817 s shift by 1/1.125 = 0.888µs)

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1-PPS output: closed loop result

-600 -400 -200 0 200 400 600

0 20000 40000 60000 80000 100000 120000 140000

1-PPS offset (ns)

time (s)

free running gnss-sdr v.s UBlox

10^-14 10^-13 10^-12 10^-11 10^-10 10^-09 10^-08 10^-07

10⁰ 10¹ 10² 10³ 10⁴ 10⁵

Allan deviation (no unit)

integration time (s)

gnss-sdr v.s UBlox UBlox v.s HM counter gnss-sdr v.s HM counter UBlox v.s HM counter

gnss-sdr v.s HM counter

I Long term stability assessment I Drift of the HM with respect to

1-PPS GNSS visible at≥X·10⁴ s I Convert time intervalx phase-time fluctuation to³ fractional-frequency fluctuationy= ˙x

SigmaTheta-4.1/1col2col file SigmaTheta-4.1/X2Y file_2col

I Allan Time Deviation (MDEV⁴) from 10⁻⁸at 1 s (10 ns @ 1 s)

&1/τ

SigmaTheta-4.1/MDev file_2col.ykt

I Control loop time constant visible τ∈[10−100] s

4E. Rubiola,Phase Noise and Frequency Stability in Oscillators, Cambridge Univ. Press (2009), p.8

4F. Vernotte& al., SigmaTheta athttps://theta.obs-besancon.fr/spip.php?article103&lang=en

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1-PPS output: OCXO→TCXO

I Replace SMA100A OCXO clocked synthesizer with TCXO clocked AD9959 Direct Digital Synthesizer (DDS)

I Short term performance degraded by drift

I 32-bit resolution→18.6 mHz DDS frequency resolution when clocked by a 20 MHz TCXO internally multiplied by 4 I close to SMA100A 10 mHz

frequency resolution

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1-PPS output: control loop initialization

0 100 200 300 400 500

-120 -100 -80 -60 -40 -20 0 20

time (s) 0.5

0

-0.5

-1100 200 300 400

time (s)

1 PPS v.s HM (us)

free running

lock on GNSS: define setpoint

I Excessive frequency offset between TCXO frequency and nominal frequency ...

I ... prevents initial fast convergence and leads to excessive oscillations.

I Initial coarse estimate of the frequency offset byobservingthe frequency drift once the first PVT solutions are found before closing the control loop

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Conclusion

I Bridge the virtual output of SDR & application to GNSS decoding with hardware 1-PPS output I Only the ADC timestamp provides accurate timing propagated to the asynchronous processing

chain

I →need to steer the clock controlling the ADC ...

I ... which also happens to control the FPGA in which the counter is implemented.

I Demonstrated 1-PPS frequency control to 10⁻⁸@1 s &

&1/τ consistent with hardware receiver performance I Sample loss will hardly affectfrequency control Perspective: 1-PPS phase (time-offset) control even when ADC samples are lost

Fork ofgnss-sdrwith 1-PPS support (SMA100A) available athttps://github.com/oscimp/gnss-sdr-1pps

Acknowledgement: the free, opensource software/gatewaredevelopment community:

I gnss-sdratgithub.com/gnss-sdr/by the Centre Tecnol`ogic Telecomunicacions Catalunya (CTTC, Spain): C.

Fern´andez-Prades and J. Arribas are acknowledged for fruitful discussions I GNU Radio atgithub.com/gnuradio/

I Ettus Research FPGA

github.com/ettusresearch/fpgaand USRP Hardware Driver (UHD) Software atgithub.com/ettusresearch/uhd I Buildroot athttps://buildroot.org/

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