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An algorithm to efficiently and accurately compute the effective capacitances of interconnects driven by logic gates

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Academic year: 2021

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Figure

Fig.  1  A Distributed  Interconnect  Model
Fig. 3.  A  -I model replaced  by  an  effective  capacitance  model.
Fig.  4. A  Thevenin  equivalent  for a gate  driven by  a  step input  loaded  with  a H  model.
Fig.  5.  A  Thevenin  equivalent  for a gate  driven  by  a ramp input loaded  with  a HI  model.
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