Functions and Functional Blocks

ELEN0040 - Electronique num´erique

Patricia ROUSSEAUX

Ann´ee acad´emique 2014-2015

CHAPITRE 3

Combinational Logic Circuits

ELEN0040 3 - 96

1 Combinational Functional Blocks 1.1 Rudimentary Functions

1.2 Functions and Functional Blocks 1.3 Decoders

1.4 Encoders 1.5 Multiplexers

1.6 Implementing Combinational Functions with Multiplexers

2 Arithmetic Functions 2.1 Binary Adders

2.2 Binary Arithmetic

2.3 Binary Adders-Subtractors 2.4 Overflow

2.5 Other Arithmetic Functions

Functions and Functional Blocks

◮ Introduction of fundamental components performing basic combinational functions

◮ The basic functions considered are those found to be very useful in design : decoding, encoding, selecting

◮ Corresponding to each of the functions is a combinational circuit implementation called a functional block : decoder, encoder and multiplexer

◮ In the past, functional blocks were packaged as

small-scale-integrated (SSI), medium-scale integrated (MSI), and large-scale-integrated (LSI) circuits.

◮ Today, they are often simply implemented within a very-large-scale-integrated (VLSI) circuit.

ELEN0040 3 - 98

Multiple-bit Rudimentary Functions

Multi-bit Examples:

A wide line is used to represent a bus which is a vector signal

In (b) of the example, F = (F₃, F₂, F₁, F₀) is a bus.

The bus can be split into individual bits as shown in (b)

Sets of bits can be split from the bus : (c) bits 2 and 1 of F.

The sets of bits need not be continuous : (d) bits 3, 1, and 0 of F.

F (d) 0

F₃

1 F₂

F₁

A F₀

(a)

0 1 A

1 2 3

4 F

0

(b)

4 2:1 ² F(2:1) F

(c)

4 3,1:0 ³ F(3), F(1:0)

A A

Enabling Function

Enabling permits an input signal to pass through to an output

Disabling blocks an input signal from passing through to an output, replacing it with a fixed value !

The value on the output when it is disable can be 0 , or 1

• When disabled, 0 output

• When disabled, 1 output

100

X F

EN

(a)

EN

X F

(b)

Decoding ( n → m ; n < m )

Decoding - the conversion of an n-bit input code to an m-bit output code with

n ≤ m ≤ 2

such that each valid input code word produces a unique output code

Circuits that perform decoding are called decoders Here, functional blocks for decoding are

• called : n-to-m line decoders, where m ≤ 2

, and

• generate 2

(or fewer) minterms for the n input

variables

Decoder Examples

1-to-2-Line Decoder

2-to-4-Line Decoder

102

The 2-4-line decoder is made up of 2 1-to-2-line decoders and 4 AND gates.

A D₀ D₁

0 1 0

1 0 1

(a) (b)

D₁5 A A

D₀5 A

A₁

0 0 1 1

A₀

0 1 0 1

D₀

1 0 0 0

D₁

0 1 0 0

D₂

0 0 1 0

D₃

0 0 0 1 (a)

(b)

D₀ 5 A₁A₀

D₁ 5 A₁A₀

D₂ 5 A₁A₀

D₃ 5 A₁A₀ A₁

A₀

Decoder Expansion

For a larger decoder with n inputs and 2ⁿ outputs, use hierarchical design

Split the decoder into smaller dimensions ones At each stage, divide by 2 the number of inputs The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by 1.

These decoders are then designed using the same procedure until 2-to-1-line decoders are reached.

The procedure can be modified to apply to decoders with the number of outputs ≠ 2ⁿ

Decoder Expansion - Example 1

3-to-8-line decoder

• Number of inputs n=3

• Number of output ANDs m=2³=8

• First split : 3 = 1*2 + 1

One 2-to-4-line decoder One 1-to-2-line decoder

• Second split : split the 2-to-4-line decoder, 2=2*1

Two 1-to-2-line decoders

• At each stage, each decoder with k (k>1) inputs provides its 2^k outputs through 2^k 2-AND gates

104

Decoder Expansion - Example 1

Circuit

1-to-2-Line decoders

4 2-input ANDs 8 2-input ANDs

2-to-4-Line decoder

D₀ A₀

A₁

A₂

D₁

D₂

D₃

D₄

D₅

D₆

D₇

Decoder Expansion - Example 2

7-to-128-line decoder

• Number of output ANDs m=2⁷= 128

• Number of inputs n= 7

• First split : 7=1*4+1*3

One 4-to-16-line decoder One 3-to-8-line decoder

• Second split :

4-to-16-line decoder : 4=2*2 → Two 2-to-4-line decoders 3-to-8-line decoder : 3=1*2+1 → One 2-to-4-line decoder + one 1-to-2-line decoder

• Third split :

2-to-4-line decoders : 2=2*1 → Two 1-to-2-line decoders

106

7-to-128-line decoder : hierarchical structure

128 2-ANDs 16 2-ANDs

8 2-ANDs 4 2-ANDs

4 2-ANDs

4 2-ANDs DEC 1-2

DEC 1-2

DEC 1-2

DEC 1-2

DEC 1-2

DEC 1-2

DEC 1-2 DEC 2-4

DEC 2-4

DEC 2-4

DEC 3-8 DEC 4-16

7 inputs

Decoder with Enable

In general, attach m-enabling circuits to the outputs See truth table below for function

• Note the use of X’s to denote both 0 and 1 in the inputs

• Combination containing two X’s represent four binary combinations

Demultiplexer : distribute value of signal EN to 1 of 4 outputs

In this case,

• input data =EN

• Selection inputs = A₁, A₀

108

EN A₁

A₀

D₀

D₁

D₂

D₃

(b) EN A₁ A₀ D₀ D₁ D₂ D₃

0 1 1 1 1

X 0 0 1 1

X 0 1 0 1

0 1 0 0 0

0 0 1 0 0

0 0 0 1 0

0 0 0 0 1 (a)

Combinational Logic Implementation

Decoder and OR Gates A decoder provides 2

minterms

Any function can be represented by its SOM expression

A decoder can be used to implement m functions of n variables :

• Find the sum-of-minterms expressions

• Use one n-to-2ⁿ-line decoder

• Use m OR gates, one for each output

Not always the best solution !

Decoder and OR Gates Example

Implement the following set of odd parity functions of (A₇, A₆, A₅, A₃)

P₁ = A₇ A₅ A₃ P₂ = A₇ A₆ A₃ P₄ = A₇ A₆ A₅

Finding sum of

minterms expressions

P₁ = Σ_m(1,2,5,6,8,11,12,15) P₂ = Σ_m(1,3,4,6,8,10,13,15) P₄ = Σ_m(2,3,4,5,8,9,14,15)

Find circuit

Best solution ? Better to resort to XOR gates

110

+ + +

+ + +

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A₇ A₆ A₅ A₃

P

P

P

DEC 4-16

Encoding

Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with

n ≤ m ≤ 2

such that each valid code word produces a unique output code

Circuits that perform encoding are called encoders

An encoder has 2

(or fewer) input lines and n output lines which generate the binary code corresponding to the input values

Typically, an encoder converts a code containing

exactly one bit that is 1 to a binary code corresponding

to the position in which the 1 appears.

Encoder Example

A decimal-to-BCD encoder

• Inputs: 10 bits corresponding to decimal digits 0 through 9, (D₀, …, D₉)

• Outputs: 4 bits with BCD codes

• Function: If input bit D_i is a 1, then the output (A₃, A₂, A₁, A₀) is the BCD code for i

The truth table could be formed, but alternatively, the equations for each of the four outputs can be obtained directly.

112

Encoder Example (continued)

Encoder Example (continued)

Input D

is a term in equation A

if bit A

is 1 in the binary coded value of i.

Equations:

A

= D

+ D

A

= D

+ D

+ D

+ D

A

= D

+ D

+ D

+ D

A

= D

+ D

+ D

+ D

+ D

114

Priority Encoder

If more than one input value is 1, then the encoder just designed does not work.

One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder.

It implements a priority function, one 1 value is given the priority above others

For example, among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position.

Priority Encoder Example

Priority encoder with 5 inputs (D₄, D₃, D₂, D₁, D₀) - highest priority to most significant 1 present –

Code outputs A2, A1, A0 and V where V indicates at least one 1 present.

In the Table, X in input variable represent 0 or 1 so that row 6 of the table represents 16 rows of the truth table

116

No. of Min- terms/Row

Inputs ^Outputs

D4 D3 D2 D1 D0 A2 A1 A0 V

1 0 0 0 0 0 X X X 0

1 0 0 0 0 1 0 0 0 1

2 0 0 0 1 X 0 0 1 1

4 0 0 1 X X 0 1 0 1

8 0 1 X X X 0 1 1 1

16 1 X X X X 1 0 0 1

Priority Encoder Example (continued)

Equations (after simplification) :

A

= D

A

= D

+ D

= F

, F

= (D

+ D

) A

= D

+ D

= (D

+ D

)

V = D

+ F

+ D

+ D

D

D

D

D

D

D

D

D

D

D

Selecting

Selecting data or information is a critical function in digital systems and computers

Circuits that perform selecting have:

• A set of information inputs from which the selection is made

• A single output

• A set of control lines for making the selection

Logic circuits that perform selecting are called multiplexers

118

Multiplexers

A multiplexer selects information from an input line and directs the information to the output line A typical multiplexer has n control inputs

(S

, … S

) called selection inputs, 2

information inputs (I

, … I

), and one output Y A multiplexer can be designed to have m

information inputs with m < 2

as well as n

selection inputs

Multiplexers (2)

120

Input Selection

Inputs Output

2-to-1-Line Multiplexer

Two information inputs I

, I

, so n=1 A single selection input S:

• S = 0 selects input I₀

• S = 1 selects input I₁

Truth table : The equation:

Y = I S

+ SI

2-to-1-Line Multiplexer

The circuit:

We recognize :

• 1-to-2-line Decoder

• 2 Enabling circuits

• 2-input OR gate

122

S

I₀

I₁

Decoder Enabling

Circuits

Y

2

-to-1-Line Multiplexer

For n>1 selecting inputs

An 2

-to-1-line multiplexer can be built from :

• one n-to-2ⁿ-line decoder generating the m_i

• one 2ⁿ × 2 AND-OR circuit combining the enabling circuits and the OR gate

Example : n=2 Equation

+

+ +

Example: 4-to-1-line Multiplexer

one 2-to-2²-line decoder one 2² × 2 AND-OR

124

S1

Decoder

S0

Y S1

Decoder

S0

Y

S₁ Decoder

4 3 2 AND-OR S₀

Y I₂

I₃ I₁ I₀

Inputs !

4×2 AND-OR m_i

Multiplexer with m outputs

Select “vectors of bits” instead of “bits”

Use multiple copies of 2

× 2 AND-OR in parallel Example: m=4

4-to-1-line quad multi- plexer

4 3 2 AND-OR

2-to-4-Line decoder

4 3 2 AND-OR

4 3 2 AND-OR

4 3 2 AND-OR I_0,0

I_3,0

I_0,1

I_3,1

I_0,2

I_3,2

I_0,3

I_3,3

Y₀

D₀

D₃ A₀

A₁

Y₁

Y₂

Y₃ ..

.

.. .

.. .

.. .

.. . 4×2 AND-OR

4×2 AND-OR

4×2 AND-OR

4×2 AND-OR

Combinational Logic Implementation - Multiplexer Approach 1

Multiplexing is a universal function

Any combinational n-variable function can be implemented with a

• A sum-of-minterms expression

• An 2ⁿ-to-1-line multiplexer

Design :

• Apply the function input variables to the multiplexer selection inputs S_{n - 1}, … , S₀

• Find the SOM expression from the truth table

• Put values to multiplexer inputs :

If minterm m_j is present in SOM, put I_j=1

If minterm m_j is not present in SOM, put I_j=0

126

Example : F(X,Y) = Ʃm(0, 3)

S₁ Decoder

S₀

Y

S₁ Decoder

S₀

Y

S₁ Decoder

4 3 2 AND-OR S₀

Y I₂

I₃ I₁ I₀

Y X

m₀

m₁

m₂

m₃

1

1 0 0

4×2 AND-OR

Example: Gray to Binary Code

Design a circuit to convert a 3-bit Gray code to a binary code The formulation gives the truth table on the right

It is obvious from this table that X = C and the Y and Z are more complex

128

Gray A B C

Binary x y z 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1

Gray to Binary (continued)

Rearrange the table so

that the input combinations are in counting order

Functions y and z can be implemented using a dual 8-to-1-line

multiplexer by:

• connecting A, B, and C to the multiplexer select inputs

• placing y and z on the two multiplexer outputs

• connecting their respective truth table values to the inputs

Gray A B C

Binary x y z 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 0 1

Gray to Binary (continued)

, , , , , ,

130

D04 D05 D06 D07 S1 S0 A

B

S2 D03 D02 D01 D00

Out

C

D14 D15 D16 D17 S1 S0 A

B

S2 D13 D12 D11 D10

Out

C 1

1

1 1 1

1

1 1

0 0 0

0

0

0 0

0

Y Z

8-to-1 MUX

8-to-1 MUX

Gray A B C

Binary x y z 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 0 1

Combinational Logic Implementation

- Multiplexer Approach 2

A simpler implementation is obtained by using :

• A 2^n-1-to-1-line multiplexer

• A single inverter

Design:

• Apply the first n-1 function input variables to the multiplexer selection inputs S_{n - 2}, … , S₀

• Find the SOM expression from the truth table

• Define the multiplexer inputs to get the minterms of the function :

let be the n-th function input variable each multiplexer input is either : 1, 0, or

Gray to Binary (continued)

132

Gray A B C

Binary x y z

Rudimentary Functions of

C for y

Rudimentary Functions of

C for z

0 0 0 0 0 0

0 0 1 1 1 1

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 0 0 1

1 0 1 1 1 0

1 1 0 0 1 0

1 1 1 1 0 1

F = C F = C

F = C F = C F = C

F = C F = C

F = C

Gray to Binary (continued)

Assign the variables and functions to the multiplexer inputs:

Note that this approach (Approach 2) reduces the cost by almost half compared to Approach 1.

S1 S0 A

B

D03 D02 D01 D00

Out Y

8-to-1 MUX C

C C

C D13

D12 D11 D10

Out Z

8-to-1 S1 MUX

S0 A

B C

C C

C C C

Y m 1,2,5,6 Z m 1,2,4,7

Summary

Decoder :

◮ n inputs

◮ m outputs, n ≤ m ≤ 2ⁿ

◮ generate minterms : output D_i = m_i

Encoder :

◮ 2ⁿ inputs = 2ⁿ minterms, only one equal to 1

◮ n outputs

◮ generate the binary

representation of the input values : n-bit representation

ELEN0040 3 - 134

Summary (continued)

Multiplexer :

◮ n selecting inputs

◮ 2ⁿ information inputs

◮ one output

◮ select binary information from one input

F = ¯S₁S¯₀D₀ + ¯S₁S₀D₁ + S₁S¯₀D₂ + S₁S₀D₃

1 Combinational Functional Blocks 1.1 Rudimentary Functions

1.2 Functions and Functional Blocks 1.3 Decoders

1.4 Encoders 1.5 Multiplexers

1.6 Implementing Combinational Functions with Multiplexers

2 Arithmetic Functions 2.1 Binary Adders

2.2 Binary Arithmetic

2.3 Binary Adders-Subtractors 2.4 Overflow

2.5 Other Arithmetic Functions

ELEN0040 3 - 136

Arithmetic circuits

◮ An arithmetic circuit is a combinational circuit that performs arithmetic operations :

◮ addition

◮ subtraction

◮ multiplication

◮ division

◮ The operations are performed with binary numbers or decimal numbers in a binary code

◮ Apply the rules of arithmetic with binary numbers

◮ rules for numbers representation

◮ resort to 1 or 2’s complements

◮ An arithmetic circuit :

◮ operates on binary vectors

◮ uses the same subfunction for each bit position

◮ is made of the iterative interconnection of basic functional blocks, one for each bit position = iterative array

Adders

Functional blocks :

◮ Half-Adder : a 2-input, 2-output functional block that performs the addition of the two input bits

◮ Full-Adder : a 3-input, 2-output functional block that performs the addition of the three input bits, including a third carry input bit obtained from a previous adder

Multiple bit adders :

◮ Ripple Carry Adder : an iterative array to perform binary addition

◮ Carry Look Ahead Adder : an improved structure with higher performance

ELEN0040 3 - 138

Half-Adder

A Half-Adder performs the following computations:

It adds two bits to produce a two-bit sum

The sum is expressed as a Sum bit, S and a Carry bit, C

X 0 0 1 1

+ Y + 0 + 1 + 0 + 1

C S 0 0 0 1 0 1 1 0

Half-Adder : Truth table

From the truth table, we get the equations :

For S

And for C :

140

X Y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

) Y X

( ) Y X

( S

Y X

Y X

Y X

S

++++

⋅⋅⋅⋅

++++

====

⊕

⊕ ⊕

⊕

====

⋅⋅⋅⋅

++++

⋅⋅⋅⋅

====

) (

C

Y X

C

) Y X ( ⋅⋅⋅⋅

====

⋅⋅⋅⋅

====

Y

Half-Adder : Five Implementations

We can derive the 5 following sets of equations for a half-adder:

(a), (b), and (e) are SOP, POS, and XOR implementations for S.

In (c), the C function is used as a term in the AND- NOR implementation of S, and in (d), the function is used in a POS term for

S.

Y X

C

) (

S ) c (

Y X

C

) Y X

( ) Y X

( S

) b (

Y X

C

Y X

Y X

S ) a (

Y C X

⋅⋅⋅⋅

==== ==== ==== ==== ==== ==== ⋅⋅⋅⋅ ⋅⋅⋅⋅ ⋅⋅⋅⋅ ++++ ++++ ⋅⋅⋅⋅ ⋅⋅⋅⋅ ++++

⋅⋅⋅⋅

++++

Y X

C

Y X

S ) e (

) Y X

( C

C )

Y X

( S

) d (

⋅⋅⋅⋅

==== ⊕ ⊕ ⊕ ⊕

==== ==== ==== ++++ ++++ ⋅⋅⋅⋅

C

142

Half-Adder : Implementations

The most common half

adder implementation is: (e)

A NAND only implementation is: (d)

Y X

C

Y X

S ==== ==== ⊕ ⊕ ⊕ ⊕ ⋅⋅⋅⋅

) (

C

C )

Y X

( S

) Y X ( ⋅⋅⋅⋅

==== ++++ ⋅⋅⋅⋅

====

X Y

C S

X

Y

C

C S

XOR

Full-Adder

A full adder is similar to a half adder, but includes a carry-in bit from previous stages.

Like the half-adder, it computes a sum bit, S and a carry bit, C.

It performs the following computations For a carry-in Z=0

it is the same as the half-adder

For a carry- in Z=1

Z 0 0 0 0

X 0 0 1 1

+ Y + 0 + 1 + 0 + 1 C S 0 0 0 1 0 1 1 0

Z 1 1 1 1

X 0 0 1 1

+ Y + 0 + 1 + 0 + 1 C S 0 1 1 0 1 0 1 1

Full-Adder : Truth table

From the truth table, we get the equations :

After simplification :

Odd function

144

X Y Z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Z X Y C

Z Y X Z

Y X Z

Y X Z

Y X S

++++ ++++

====

++++

++++

++++

====

Z

X Y X Y Z ++++ X Y Z

Z Y

X

S ==== ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕

Z ) Y (

Y X

C ==== ++++ ⊕ ⊕ ⊕ ⊕ Z G P

C ==== ++++

X X

Y

Z

Full-Adder : Implementation

Z Y

X

S ==== ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ C ==== G ++++ P Z

The term G=X·Y is carry generate.

The term P= X⊕Y is carry propagate P

G

R´ef´erences

◮ Logic and Computer Design Fundamentals, 4/E, M. Morris Mano Charles Kime , Course material

http ://writphotec.com/mano4/

◮ Cours d’´electronique num´erique, Aur´elie Gensbittel, Bertrand Granado, Universit´e Pierre et Marie Curie

http ://bertrand.granado.free.fr/Licence/ue201/

coursbeameranime.pdf

ELEN0040 3 - 146