FLOPPY DISK

STANDARD MICROSYSTEMS--- CORPORATION

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!II!!!

TECHNICAL NOTE TN6-1

FDC9216

FLOPPY DISK

DATA SEPARATOR

2

1. INTRODUCTION

Data written to a floppy disk drive is typically a self-clock- ing encoded serial data stream. ~wo metho~s of enco~ing

are in widespread use today: Single-density recordrng, also known as FM (Frequency Modulation) and Double- density recording, also known as MFM (Modified Fre- quency Modulation).

The function of a data separator is to derive a clock signal from the combined clock/data waveform available from the output of most disk drives. This clock signal should be one suitable for input to one of the popular disk controllers such as the SMC FDC 179X family or the NEC 765 controller.

A typical FM encoded signal is shown in Figure 1 A and a typical MFM encoded waveform is shown in Figure 1 B. The clock signals or windows required for the floppy con!rolle~s

are also shown in the figures. Note that the clock signal IS really a signal which is used to delineate the half-bit slots in the disk data separator waveform to allow the controller to separate clock slots from data slots.

One scheme for data separation is shown in Figure 2A. The disk data is presented directly to the controller and the data separator provides a derived clock to define the half-bit slots.

Most analog phase-locked loop data separators are con- nected in this way. Figure 2B shows another scheme for data separation. The disk data is remembered by the data separator and regenerated for presentation to the di.sk controller. The derived clock is also regenerated to main- tain proper synchronization with the regenerated data. The FDC9216/B is a floppy disk data separator of this type.

Figure 3 shows the single and double density wa".efor~s

used to represent the eight-bit byte "D1" (hexadecimal) In floppy disk systems. Each of the eight bit times, bO through b7, is comprised of a clock half-bit slot foll0w.e~ by a data half-bit slot. Data is represented by a pulse wlthrn the data slot for a one, and by the absence of a pulse within the data slot for a zero.

The purpose of the clock slots is to provide positions for the insertion of non-data pulses in the waveform which help the data recovery hardware keep accurate count of bit times.

Without pulses in the clock slots, the representation of an all-zero data byte would be a featureless waveform eight bit times long. It would be difficult for the data recoyery hardware to know how many bits of zero had been received especially with variations in disk speed.

Rules for single-density encoding require a pulse to be inserted in each clock slot. This is shown in waveform B of Figure 3. Double density rules specify pulse insertion in clock slots only between consecutive zer.os as shown in wave,- form A. Since the controller determines whether a half-bit slot is a clock slot or a data slot, the data separator is able to treat clock slots and data slots identically. This is fortun- ate since radically different data patterns can have nearly identical double density representations, as shown in Fig- ure 4. It is the responsibility of the data separator to sepa- rate the data waveform into half-bit slots by providing an accompanying clock waveform, but it is the responsibility of the controller to differentiate clock slots from data slots.

(This is usually done by the use of special bytes which "break the rules" regarding clock slot pulse insertion, making them distinguishable from ordinary data bytes).

2. THEORY OF OPERATION

Figure 5 shows the relationship of the clock waveform to

the half-bit slots required by several currently available floppy disk controllers. The end of one half-bit slot and the begin- ning of the next is defined by a transition of the clock wave- form. Both positive-going and negative-going transitions are handled identically, and the fact that the clock waveform is high during one half-bit slot and low during the next is of no importance in differentiating clock slots from data slots.

Thus, clock waveforms A and B in Figure 5 are functionally identical.

The position of a pulse in the data waveform is taken to be its leading edge. Thus, as shown in the ideal data wave- form of Figure 5, the leading edge of each pulse should be centered in its half-bit slot, midway between clock wave- form transitions. If a pulse is widened so that the clock wave- form transitions during the pulse, the pulse is still associated with the half-bit slot containing the leading edge.

Figure 5 also shows a distorted data waveform, more real- istic than the ideal data waveform. Magnetic effects on the disk (mainly peak shift as shown in Figure 6) cause pulse positions to vary from ideal, as do variations in disk speed.

As a result, many pulses occur early or late withi~ their half- bit slots. It is therefore important that the denved clock delineate the half-bit slots as accurately as possible ·so that the position of a pulse may vary with the gre.atest ma:g~n

and still be associated with the correct half-bit slot. ThiS IS accomplished by adjusting the phase of the derived clo~k

so that the average position of the last several pulses IS centered in the half-bit slot.

The heart of the FDC9216/B Floppy Disk Data Separator is a synthetic oscillator phase-locked loop. One half-bit slot of the incoming data stream corresponds to one cycle of the synthetic oscillator. Each oscillator cycle consists nomi- nally of eight phase slices, identified in Figure 7 as phase memory values 1 through 8. The circuit therefore needs a phase slice clock with a frequency eight times the half- bit frequency.

Detection of an input pulse away from the center of its half- bit slot (in other than phases 4 or 5) causes a phase cor- rection to be applied to the synthetic oscillator, bringing the center of the half-bit slot closer to the pulse. Referring to Figure 7, input pulse 'A' in slot 1 is centered, so no corre?- tion is applied. Input pulse 'B' in slot 2 is early, so the slot IS shortened by skipping phase 3. Slot 3 contains no input pulse and is not corrected. Input pulse 'C' in slot 4 is late, so the slot is lengthened by repeating phase 8.

The end-of-cycle signal from the internal synthetic oscilla- tor phase-locked loop logic function array defines the derived clock waveform and the duration of each half-bit slot. The occurrence of an input detection during the half-bit slot is remembered and used to regenerate the data wave- form pulses immediately following end-of-cycie. The rela- tionship between detected and regenerated pulses 'A', 'B', and 'C' is shown in Figure 7. A delayed form of end-of- cycle is used to toggle the regenerated clock so that the regenerated data pu Ises are more nearly centered with respect to the regenerated clock (for compatibility with existing controllers).

The variation in the rotational speed of many floppy disk drives is as much as two percent. If data is recorded on a drive running two percent slow, and retrieved on a drive running two percent fast, the disk data waveform presente?

to the data separator will be four percent faster than nomi- nal. Similarly, the data separator may also be required to

DATA

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PATTERN

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FM ENCODED DATA

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TRANSITIONS (HEAD _CURRENT)

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(SE~~~~TED_) ^____ ~n~

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FIGURE 1A: FM ENCODING SCHEME

DATA PATTERN

MFM ENCODED

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FIGURE 1B: MFM ENCODING SCHEME

° ° ° °

C C C

3

4

handle incoming disk data as much as four percent slow. To compensate for these variations in average half-bit fre- quency, center-frequency correction is added as an improvement to the synthetic oscillator phase-locked loop algorithm. A short history is kept of input pulse detections which induce phase corrections. This history is used to allow subsequent phase corrections to request upward or down- ward changes in center frequency.

3. TYPICAL SYSTEM CONFIGURATION

Figure 8A shows a system configuration using the FDC179X Floppy Disk Formatter Controller and the FDC9216/B Floppy Disk Data Separator. Figure 8B

(A)

shows a system configuration using the NEC 765 Floppy Disk Controller and the FDC9216/B Floppy Disk Data Separator.

Note that a write precompensation circuit is also included.

Write precompensation is typically performed on the write data to reduce the amount of peak shift in the recovered data. Since peak shift is data pattern sensitive, its direction can be predicted by the Floppy Disk Controller/Formatter.

This information is used when writing the data on the disk to cause particular flux transitions (or pulses) to be written early or late from their nominal positions. This causes the recovered data to appear closer to its nominal bit position.

~ __ . -_________ D_IS_K __ D_AT._A ____________ ~DATA

(8)

FLOPPY DISK DRIVE

FLOPPY DISK DRIVE

DATA DISK

DATA SEPARATOR

CONTROLLER r -__ D_R_IV_E_C_L_O_C_K __ ~ CLOCK

~---REGENERATED DATA

DATA DATA

SEPARATOR t---~ CLOCK REGENERATED

DERIVED CLOCK

FIGURE 2

CONTROLLER

4. CHARACTERIZATION TEST RESULTS FOR

5V4" DRIVES

The FDC9216/B has been tested for error performance with a variety of 51/4" floppy disk drives. During the tests it was found that the performance of the FDC9216/B is enhanced by the selection of an optimum value of write pre- compensation for the particular type of drive being used.

The object of the tests were as follows:

1) To determine the optimum write precompensation for each manufacturer's drive type.

2) To determine the overall error rate of each drive type at nominal speed.

3) To determine the error rate of each type of drive over

a speed variation range of plus or minus 2% from nominal. This typifies the worst case for a disk that is written on one drive and read on another.

4) To determine the overall error rate of the FDC9216/B over all drives tested at nominal speed and at plus or minus 2% speed variation.

The following test configuration and drives were used:

Test Configuration:

Test System -North Star S100 System with SMC FDCS100 disk controller board oper- ating the drive under test.

Test Program -DISKSCAN test program, for use with the FDCS100 board.

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BIT TIMES HALF-BIT SLOTS DATA PATTERN "D1"

1 1 1 2 1 3 1 4 1 5 1 6

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FIGURE 3

FIGURE 4

DOUBLE DEN. WAVEFORM

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SINGLE DEN. WAVEFORM

®

DATA PATTERN "FF"

DATA PATTERN "00"

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ONE "HALF-BIT SLOT"

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FIGURE 5

6

Media

Orives:

- 1. Structured Systems Group, 5V4", single-sided.

2. Maxell, 5V4", single-sided, M01.

3. Maxell, 8", single-sided, F01.

4. Oysan, 5V4", 104/20.

- 1. Magnetic Peripherals, 51/4", Model

9408,Seri~Number001298

2. Shugart Assc., 51/4", Model 400, Serial Number B001160

3. Qume, 51/4", Model OT/5, Serial Number 19516

4. Tandon, 5114" Model TM100-1A, Serial Number 81380111

5. Qume, 5114", Model OT/5, Serial Number 60475

6. Shugart Assc., 51/4", Model 400, Serial Number L 12492

7. Shugart Assc., 5114", Model 410, Serial Number A13183

11. Micro Peripherals, 5%", Model 51 S, Serial Number 123487

The media used were standard off-the-shelf Maxell' Struc- tured-Systems, and Oysan single-sided flexible disks. The entire disk was written with a double-density MFM data pat- tern of 256 "60" (hex) bytes in each sector. This pattern was chosen because it contains the worst-case bit-shift patterns. Each individual test consisted of 1.0E9 bits read and was accomplished by repetitively reading the disk. (Note:

The notation "E9" should be read as "times 1

°

to the ninth power")

Figure 9 shows the results of the write precompensation tests for each drive. Each dot in each graph represents the actual error rate for 1 E9 bits formatted and read at the indicated precompensation value at nominal speed. For each test write precompensation was applied uniformly to all tracks. For all drives there was at least one value of precompensation, and in most cases several values, which produced zero errors in 1 E9 bits written and read back at nominal drive speed. Note that some drives have a much wider variation in write precompensation range than oth- ers.

Overall, these tests indicated that a write precompensation value in the range of 250 to 438ns is suitable for most 51/4"

drives. The speed variation tests are, of course, more strin- gent. For each driye this test consisted of reading in excess of 1.0E9 bits with the data written on the drive running 2%

slower than nominal, then read back on the drive set to run 2% faster than nominal. This had been determined to be

Speed Variation Drive # Soft Error Rate

1 <1 in 1.0E9 bits 2 1 in 2.0E8 bits 3 1 in 1 .OE9 bits 4 1 in 1 .OE9 bits 5 1 in 5.0E8 bits 6 <1 in 1.0E9 bits 7 1 in 1 .OE9 bits 11 1 in 1 .4E8 bits

Precom- pensation

@(ns) 250 375 438 250 438 375 312 438 TABLE 1

Remarks

the worst case speed test for the FOC9216/B. For each drive the results were as shown in Table 1.

All read errors were ''soft'' errors, that is the data was com- pletely recovered when the sector was read again on a sub- sequent pass. Based on the speed variation tests above, the overall worst case error rate was one error in 4.7E8 bits read. It should be noted that drives 1 and 6 had no errors at all at the time the test was terminated after 1.0E9 bits read.

5. CHARACTERIZATION TEST RESULTS FOR Sl/DRIVES

A number of tests were performed on 8" drives. The fol- lowing four drives were tested:

Orives- 8. Shugart Assc., 8", Model 800, SNK59696 9. Shugart Assc., 8", Model 800, SNB77977 12. Qume, 8", Model Qumetrak 842, SN114079 13. Tandon, 8", Model TM848, SN006293 Figure 10 shows the results of the write precompensation tests for these drives. For these drives a value of 187 to 312ns was optimal. For drives 8,9, and 13, write precompensation was applied only on track positions greater than 43. How- ever, drive 12 produced the lowest error rate when write precompensation was applied to track positions greater than 27. The speed variation tests consisted of writing the data at a 4% faster rate and reading it back at nominal speed.

All read errors were ''soft'' errors. The results are shown in Table 2.

Precom- Speed Variation pensation

Drive # Soft Error Rate @(ns) Remarks 8 <1 in 1.0E9 bits 312 Also <1 in

1.0E9 bits @ 4% recorded slow, played back nominal.

9 1 in 1.0E9 bits 250

12 1 in 5.0E8 bits 312 Precomp applied to tracks greater than 27.

13 1 in 1 .OE9 bits 187 TABLE 2

6. SUMMARY

These tests indicate that the FOC9216/B is an extremely effective data separator. The error rates are acceptable for virtually all systems. Further, all errors were soft errors which were subsequently re-read without error. Furthermore, the observed error rates were system error rates; that is, the entire system including disk drive, data separator, floppy disk controller, power supply etc. all contributed to the resultant error rate. The data separator does not stand isolated but is rather one of several elements in the data recovery proc- ess. Its low-cost, absence of finicky user adjustments (pots), and small-size make the 8-pin FOC9216/B ideal for most floppy disk system applications.

WRITE TRANSITION

SUPERIMPOSED READBACK PULSES

SUMMATION

READ DATA

PEAK-SHIFT EFFECTS

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FIGURE 7

+5V

FDC179X 8

RAW DATA FROM DRIVE

GND VDD

DSKD SEPD 7 27

RAW READ FDC9216

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INTERFACE

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FIGURE SA: TYPICAL 179X SYSTEM CONFIGURATION WITH WRITE PRECOMPENSATION

FIGURE 8B: TYPICAL 765 SYSTEM CONFIGURATION WITH WRITE PRECOMPENSATION AND

INPUT BUFFERING

RAW DATA

FROM DRIVE 6

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CPU INTERFACE

10

PRECOMP TEST

V SCALE = NO. OF BITS READ/1 ERROR.

H SCALE = AMOUNT OF PRECOMP USED TO FORMAT TRACK.

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DRIVE 1

• •

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FIGURE 9:

5114"

DRIVE WRITE PRECOMPENSATION

DRIVE 8

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STANDARD MICROSYSTEMS CORPORATION

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applica- tions; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes

at any time in order to improve design and supply the best product possible. ©6/82-5M