1982/83

1982/83

DafaBook

Zilog

Copyright 1981, 1982 by Zllog, Inc. All rIghts reserved. No part of thIs publIcatIon may be reproduced, stored In a retrIeval system I or transmItted, In any form or by any means, electronic, mechamcal, photocopymg, recordmg, or other~

WIse, wIthout the pnor written permISSIon of 2110g.

The mformatIon contamed herem IS subject to change wIthout nobce. 2110g assumes no responslblhty for the use of any CIrcuItry other than CIrCUItry embodIed In a Zilog pro·

duct. No other CircUlt patent heenses are ImplIed

Zilog offers mICrocomputers m every form: from components and development systems to board-level products and complete general- purpose mICrocomputer systems.

ThIs edItion of the Zi]og Data Book describes Zilog components, development systems, and micro- computer boards. You'll also fmd a section on the m-depth trainmg courses now offered about most Zilog products.

Zllog components, the basic building blocks for our other microcomputer products, include

Microcomputers in Every Form

the 8-blt Z80® MIcroprocessor and its famIly of mtelhgent peripherals, the Z8™ FamIly of Smgle-Chlp MICrocomputers, and the l6-blt Z8000™ MIcroprocessor and ItS family of mtelligent peripherals.

Zllog offers a wide variety of development envIronments, rang- mg from the mexpenslve Z8 and Z8000 Development Modules to the more elaborate PDS 8000 and ZDS-l Development Systems to the ultra-sophlShcated mulh-user Z-LAB 8000 Development System.

In addlhon, EMS 8000 and Z-SCAN

8000 both provIde in-cIrcuit emula- hon for the Z8001 and Z8002 MIcroprocessors.

Our Z80 MCB Board FamIly offers a complete soluhon for pro- totype and produchon desIgns in which you don't want to desIgn a mIcrocomputer from scratch. ThIs well-estabhshed famIly mcludes a Z80 CPU board, several types of . memory boards, and boards for all

types of dIgItal and analog 110. A complete set of card cages, enclosures, and other accessories makes thIs famIly easy to use.

Table of Contents

zao

Family .. . . 3

28400 CPU Central Processing Unit . . . 5

28300 CPU Central Processmg Unit. . . .. 27

28410 DMA Direct Memory Access . . . .. 49

28420 PIO Parallel Input/Output . . . .. 67

28430 CTC Counter/Timer CIrcuit . . . .. 81

28440/1/2 SIO Serial Input/Output Controller .. . . .. 93

28470 DART Dual Asynchronous Receiver/TransmItter ... 109

zaooo

Family ... 123

2800112 CPU Central Processmg Unit ... 125

28003/4 VMPU Virtual Memory Processmg Unit ... 153

28010 2-MMU Memory Management Unit ... 155

28015 PMMU Paged Memory Management Unit . . . .. 171

28016 DTC Direct Memory Access Transfer Controller ... 173

28030 2-SCC Serial Communications Controller ... 175

28031 2-ASCC Asynchronous Serial Communications Controller ... 197

28036 2-CIO Counter/Timer and Parallel I/O Umt ... 217

28038 2-FIO FIFO Input/Output Interface Unit ... 241

28060 FIFO Buffer Unit and 2-FIO Expander ... 273

28065 2-BEP Burst Error Processor ... 281

28068 2-DCP Data Ciphering Processor ... 295

28070 Floating Point Package ... 311

28090 2-UPC Universal Peripheral Controller ... 313

Universal Peripherals ... 335

28530 SCC Serial Communications Controller ... 337

28531 ASCC Asynchronous Serial Communications Controller ... 359

28536 CIO Counter/Timer and Parallel I/O Unit ... 379

28538 FlO-See 28038 2-FIO ... 241

28581 Clock Generator and Controller ... 403

28590 UPC Universal Peripheral Controller ... 407

za

Family ... ... 429

2860112/3 MCU Microcomputer ... 431

28611/2/3 MCU Microcomputer ... 449

28671 MCU Microcomputer with BASIC/Debug Interpreter ... 467

28681 MCU Microcomputer ... 469

Additional Information 2ilog 2-BUS Component Interconnect ... 475

2-BUS Backplane Interconnect ... 493

Advanced Architectural Features of the 28000 CPU ... 497

An Introduction to the 28010 MMU ... 511

High Reliability Microcircuits ... 531

Table of Conlenls

(Continued)

zaD Microcomputer Board Products ... 545

Z80 MCB Single Board Computer ... 547

280 RMB RAM Memory Board ... 551

Z80 Ala/AlB Analog InpuVOutput and Analog Input Boards ... 553

280 lOB Input/Output Board ... 557

280 SIB Serial Interface Board . . . 559

280 PPB PROM Programming Board ... 563

280 PMB PROM Memory Board ... 565

280 MDC Memory and Disk Controller Board . . . .. 567

28000 Dual Processor Upgrade Package ... 571

Zilog Development Products .. . . .. 575

System 8000 2-LAB ... 577

EMS 8000 Emulator Subsystem . . . 591

2-SCAN 8000 ... 593

Z8000 Development Module . . . .. 597

28000 Cross-Software Package ... 601

Z8000 Software Development Package ... 603

28000 PLZlSYS Compiler . . . 605

2RTS 2ilog Real-Time Software ... 607

PDS 8000 Development System . . . .. 611

2DS 1/40280 Development System ... 615

280 PL2 Compiler ... 619

RIO ElectrIC Blackboard ... 621

28 Development Module ... 623

28 Software Development Package ... 627

Zilog Technical Training . ... 631

VI

Funclionallndex

Single-Chip Microcomputers

Z8601 Z8 8-Bit with 2K ROM ... 431

Z8602 Z8 8-Bit with Memory Interface, 64-Pm, 2K External ROM ... 431

Z8603 Z8 Prototyping Device with EPROM Interface, Protopack, 2K External ROM ... 431

Z8611 Z8 8-Bit, with 4K ROM ... 449

Z8612 Z8 wIth Memory Interface, 64- Pin 4K External ROM ... 449

Z8613 Z8 Prototyping Device with EPROM Interface, Protopack, 4K External ROM ... 449

Z867 1 8-Bit BASIC/Debug Interpreter ... 467

Z8681 8-Blt with No On-Chip ROM ... 469

a-Bit Microprocessors Z8300 Z8400 Z8410 Z8420 Z8430 Z8440 Z8441 Z8442 Z8470 Z858 1 Z80L Low-Power Central Processmg Unit. . . .. 27

Z80 CPU Central Processing Umt . . . 5

Z80 DMA DIrect Memory Access Controller . . . .. 49

Z80 PIO Parallel Input/Output Controller . . . .. 67

Z80 CTC Counter/Timer Circuit. . . .. 81

Z80 SIO Dual Channel Serial Input/Output Controller . . . .. 93

Z80 SIO Dual Channel Serial Input/Output Controller . . . .. ... 93

Z80 SIO Dual Channel Serial Input/Output Controller . . . .. 93

Z80 DART Dual Asynchronotls Receiver/TransmItter ... 109

Clock Generator and Controller ... 403

IS-Bit Microprocessors Z8001/2 Z8003/4 Z8010 Z8015 Z8016 Z8030 Z8031 Z8036 Z8038 Z8060 Z8065 Z8068 Z8070 Z8090 Z8581 Advanced ArchItectural Features of the Z8000 CPU ... 497

Introduction to the Z8010 MMU ... 511

Zilog Z-BUS Component Interconnect ... 475

Z-BUS Backplane Interconnect ... 493

Z8000 CPU Central Processmg Unit ... 125

Z8000 VMPU Virtual Memory Processing Unit ... 153

Z8000 Z-MMU Memory Management Umt ... 155

Z8000 PMMU Paged Memory Management Umt ... 171

Z8000 DTC Direct Memory Access Transfer Controller ... 173

Z8000 Z-SCC Senal Commumcatlons Controller . . . .. 175

Z8000 Z-ASCC Asynchronous Senal Commumcatlons Controller ... 197

Z8000 Z-CIO Counter/TImer and Parallel I/O Unit ... 217

Z8000 Z-FIO FIFO Input/Output Interface Unit ... 241

Z8000 FIFO Buffer Unit and Z-FIO Expander ... 273

Z8000 Z-BEP Burst Error Processor ... 281

Z8000 Z-DCP Data Clphermg Processor ... 295

Z8000 Floatmg Point Package ... 311

Z8000 Z-UPC Umversal Peripheral Controller ... 313

Clock Generator and Controller . . . .. 403 Microprocessor Peripherals

Serial Communications Controllers

Functional Index

(Continued)

Microprocessor Peripherals (Continued) Parallel 1/0 and Counter/Timers

28036 28000 2-CIO Counter/Timer and Parallel I/O Unit ... 217

28038 28000 2-FIO FIFO Input/Output Interface Unit ... 241

28060 28000 FIFO Buffer Unit and 2-FIO Expander ... 273

28536 CIO Counter/Timer and Parallel I/O Unit ... 379

Universal Peripheral Controllers 28090 28000 2-UPC Universal Peripheral Controller ... 313

2809113 28000 2-UPC External ROM-Based Universal Peripheral Controller ... 313

28092/4 28000 2-UPC External RAM-Based Universal Peripheral Controller ... 313

28590 UPC Universal Peripheral Controller ... 407

2859113 UPC External ROM-Based Universal Peripheral Controller ... 407

28592/4 UPC External RAM-Based Umversal Peripheral Controller ... 407

Clock Products 28581 Clock Generator and Controller ... 403

Board Products Dual Processor Upgrade Package for Z80 Systems ... 571

280 AIO/ AIB Analog Input/Output and Analog Input Boards ... 553

280 lOB Input/Output Board ... 557

280 MCB Single Board Computer ... 547

280 MDC Memory and Disk Controller Board ... 567

280 PLZlSYS Complier for the 280 ... 619

280 PMB PROM Memory Board . . . .. 565

280 PPB PROM Programmer Board ... , 563

280 RMB RAM Memory Board . . . .. 551

280 SIB Serial Interface Board ... 559

Development Products EMS 8000 In-Circuit Emulator Subsystem ... 591

PDS 8000 Single-User Development System ... 611

RIO Electric Blackboard, CRT Editor for PDS and 2DS Systems ... 621

System 8000 2-LAB Multi-User Development System ... 577

2DS 1140280 In-Circuit Emulator and Development System ... 615

2RTS 2ilog Real- Time, Multitaskmg Software Tools ... 607

2-SCAN 8000 In-ClrcUlt Emulator ... 593

28 Development Module, Prototyping and Evaluahon Board ... 623

280 Software Development Package, Cross-Assembler for 280-Based Development Systems ... 627

280 PLZlSYS Compiler for the 280 ... 619

28000 Cross-Software Package, C Cross-Compiler and Assembler for the Z8001 and Z8002 ... 601

28000 Development Module, Prototyping and Evaluahon Board ... 597

28000 PLZ/SYS Compiler for the 28000 . . . .. 605

Z8000 Software Development Package, Cross-Assembler for Z80-Based Development Systems ... 603

VIIl

Pari Number Index

Part Number 05-0067-00 05-0069-00 05-0103-00 05-0122-00 05-6003-XX 05-6006-03 05-6007-01 05-6009-XX 05-6011-XX 05-6013-05 05-6015-01 05-6023-01 05-6075-01 05-6101-01 05-6102-01 05-6158-01 05-6168-01 05-6219-00 06-0086-01 07-3028-00 07-3029-00 07 -3301-01 07-3302-01 07-3306-02 07-3309-01 07-3310-01 07-3361-01 07-3362-01 Z8000 Z8001 Z8002 Z8010 Z8015 Z8016 Z8030 Z8031

Description

System 8000 Z-LAB Multi-User Development System, Model20, 50 Hz ... 577

System 8000 Z-LAB Multi-User Development System, Model 30, 50 Hz ... 577

Z-SCAN 8000 In-Circuit Emulator ... 593

EMS 8000 In-Circuit Emulator Subsystem ... 591

Z80 RMB RAM Memory Board ... 551

Z80 lOB Input/Output Board ... 557

Z80 SIB Serial Interface Board .. . . .. 559

Z80 MCB Single Board Computer " ... 547

Z80 MDC Memory and Disk Controller Board . . . .. 567

ZDS 1140 Z80 In-Circuit Emulator and Development System ... 615

Z80 PPB PROM Programmer Board . . . .. 563

Z80 PMB PROM Memory Board ... 565

Z80 AIO/AIB Analog Input/Output and Analog Input Boards ... 553

Z8002 Development Module ... 597

PDS 8000 Single-User Development System ... 611

Z8 Development Module ... 623

Z8001 Development Module . . . .. 597

Dual Processor Upgrade Package for Z80 Systems ... 571

Z8000 Cross-Software Package, C Cross-Compiler and Assembler for Z8001 and Z8002, DEC 11170 with UNIX' ... 601

RIO Electric Blackboard, CRT Editor for ZDS Systems ... 621

RIO Electric Blackboard, CRT Editor for PDS Systems ... 621

Z80 PLZlSYS Compiler for use with PDS 8000/05 and PDS 8000/15 ... 605

Z80 PLZ/SYS Compiler for use with ZDS-I Series . . . .. 605

Z8000 Software Development Package, Cross-Assembler for Z80-Based Hard Disk Systems with Optional Floppy Drives ... , 603

Z8000 Software Development Package, Cross-Assembler for PDS 800/5 ... 603

Z8000 Software Development Package, Cross-Assembler for ZDS-I Series ... 603

Z8 Software Development Package, Cross-Assembler for use with PDS 8000/5 and PDS 8000115 ., ... 627

Z8 Software Development Package for use with ZDS-l Series . . . .. 627

ZRTS Z8000 Real- Time, Multitasking Software Tools ... 607

16-Bit, Segmented Central Processing Unit ... 125

16-Bit, Non-Segmented Central Processing Unit ... 125

Z8001l3 Z-MMU Memory Management Unit ... , ... 155

Z8000 PMMU Paged Memory Management Unit ... 171

Z8000 DTC Direct Memory Access Transfer Controller ... 173

Z8000 Z-SCC Serial Communications Controller .. . . .. 175

Z8000 Z-ASCC Asynchronous Serial Communications Controller ... 197

Pari Number Index

(Continued) Part Number

28036 28038 28060 28065 28068 28070 28090 28091/3 28092/4 28300 28400 28410 28420 28430 28440 28441 28442 28470 28530' 28531 28536 28581 28590 28591 28592 28593 28594 28601 28602 28603 28611 28612 28613 28671 28681

Description

28000 2-CIO Counter/Timer and Parallel 1/0 Unit ... 217

28000 2-FIO FIFO Input/Output Interface Unit ... 241

28000 FIFO Buffer Unit and 2-FIO Expander ... 273

28000 2-BEP Burst Error Processor ... 281

28000 2-DCP Data Ciphering Processor ... 295

28000 Floatmg Point Umt ... 311

28000 2-UPC Universal Peripheral Controller ... 313

28000 2-UPC Universal Peripheral Controller, External ROM-Based ... 313

28000 2-UPC Universal Peripheral Controller, External RAM-Based ... 313

280L CPU Low-Power 280 Central Processing Unit ... " 27 280 CPU 280 Central Processing Unit. . . 5

280 DMA Dual Port, Direct Memory Access Controller .. . . .. 49

280 PIO Dual Port, Parallel InputlOutput Controller . . . .. 67

280 CTC Four Channel CounterlTimer Circuit. . . .. 81

280 SIOIO Dual Channel Synchronousl Asynchronous Serial I/O Controller ... " 93 280 SIOll Dual Channel Synchronousl Asynchronous Serial 1/0 Controller . . . .. 93

280 SIO/2 Dual Channel Synchronousl Asynchronous Serial I/O Controller .. . . .. 93

280 DART Dual Channel Asynchronous Serial 1/0 Controller ... 109

SCC Serial Communications Controller ... 337

ASCC Asynchronous Serial Communications Controller ... 359

CIO Counter/Timer and Parallel I/O Unit ... 379

Clock Generator and Controller ... 403

UPC Universal Peripheral Controller ... 407

UPC Universal Peripheral Controller with External ROM ... 407

UPC Universal Peripheral Controller with External RAM ... 407

UPC Umversal Peripheral Controller with External ROM, Protopack ... 407

UPC Universal Peripheral Controller with External RAM, Protopack ... 407

28 8-Bit, Single-Chip Microcomputer with 2K ROM ... 431

28 8-Blt Microcomputer with Memory Interface, 64-Pin, 2K External ROM ... 431

28 Prototyping Device with EPROM Interface, Protopack, 2K External ROM ... 431

28 8-Blt, Smgle-Chip Microcomputer with 4K ROM ... 449

28 8-Blt MICrocomputer with Memory Interface, 64-Pin, 4K External ROM ... " 449 28 Prototyping Device with EPROM Interface, Protopack, 4K External ROM ... 449

28 8-Blt, Single-Chip BASICIDebug Interpreter ... 467

28 8-Bit, Smgle-Chip Microcomputer with No On-Chip ROM ... 469

*Al! 85XX components are compatJble with processors other than Z110g's 28001,28002,28003, and Z8004 For further mformatlOn refer to the indIvidual product speClhcatlOns

x

~ Zilog

Zilog remams an industry leader, thanks to continumg innovation m mIcrocomputer concepts and inte- grated desIgn as exemphfied in the Z80 Family microcomputer products.

At Zilog, innovahon means usmg proven, sophisticated mamframe and minicomputer concepts and translating them into the latest LSI technologies. Integration means more than designmg an ever- greater number of functions onto a single chip. Zllog mtegrates technologies-LSI design enhanced by advances m computer-based system archI- tecture and system design technologies.

Zilog offers mIcroprocessor soluhons to computing problems:

from components and development systems to OEM board-level pro- ducts and general-purpose mIcrocomputer systems.

This gUIde to the Z80 Family of state-of-the-art microprocessors and mtelhgent peripheral con- trollers demonstrates Zllog's con- tinued support for the Z80 microprocessor and the other members of the Z80 product famlly-a family first introduced in 1976 that continues to enjoy grow- ing customer support while family chIps are upgraded to newer and ever-higher standards.

Zilog Z80® Family Sets the Industry Standard for 8 Bits

June 1982

funchons than ItS competitor.

In addItion to bemg source-code compatible wIth the 8080A microprocessor, the Z80 offers more mstruchons than the 8080A (158 vs. 78) and numerous other features that simplify hardware reqUIrements and reduce program- mmg effort whIle mcreasing throughput. The dual-register set of the Z80 CPU allows hIgh-speed context sWItching and more effi- cIent mterrupt processmg. Two index registers gIve addltlOnal memory-addressing flexlblhty and slmphfy the task of programmmg.

Interfacing to dynamiC memory IS simphfied by on-chip, program- mable refresh logic. Block moves plus string- and bit-manipulahon instruchons reduce programmmg effort, program SIze, and execution time.

Now the Z8300 Z80L CPU extends the range of Z80 apphcahons. This low-power version retains all Z80 CPU functions while providmg dramahc power savmgs and mcreased rehabihty.

The four tradItional functlOns of a microcomputer system (parallel I/O, serial I/O, counting/timmg, and direct memory access) are eaSIly implemented by the Z80 CPU and the followmg well-proven famIly of Z80 peripheral devIces:

Z80 PIO, Z80 SIO, Z80 DART,

logIc. Both I/O ports operate m either a byte or a bIt mode. In addition, this device can be pro- grammed to generate interrupts for various status condlhons.

All common data communica- tions protocols, asynchronous as well as synchronous, are remarkably well handled by the Z8440 Z80 SIO Serial Input/Out- put Controller. ThIs dual-channel receIver/transmitter devIce offers on-chIp parity and CRC genera- hon/checkmg. FIFO buffermg and flag- and frame-detechon generahon logic are also offered.

If asynchronous-only applica- tions are required, the cost- effective Z8470 Z80 DART Dual Asynchronous Receiver/Transmit- ter can be used in place of the Z80 SIO. The Z80 DART offers all Z80 SIO asynchronous features in two channels.

Timmg and event-counting func- hons are the forte of the Z8430 Z80 CTC Counter/Timer Controller.

The CTC proVides four counters, each wIth mdivldually program- mable prescalers. The CTC IS a convenient source of program- mable clock rates for the SIO.

With the Z8410 Z80 DMA Direct Memory Access Controller, data can be transferred directly between any two ports (typically, I/O and memory). The DMA trans-

~ Zilog

Features • The instruction set contains 158 instructions.

The 78 instructions of the 8080A are included as a subset; 8080A software com- patibility is maintained.

• Six MHz, 4 MHz and 2.5 MHz clocks for the Z80B, Z80A, and Z80 CPU result in rapid instruction execution with consequent high data throughput.

• The extensive instruction set includes string, bit, byte, and word operations. Block searches and block transfers together with indexed and relative addressing result in the most powerful data handling capabilities in the microcomputer industry.

• The 280 microprocessors and associated family of peripheral controllers are linked by a vectored interrupt system. This system

Mi As

A,

MREQ A,

.n~1

^{lORa A,}

CONTROL RD _w-

..

A, A,

RFSH A, ADDRESS

As ^BUS

HAL.T As

A"

A"

-1

^{Z 80 CPU A"}

CONTROL A"

A"

A"

CPU { BUS CONTROL

Z8400

Z80®CPU Central Processing Unit Product

Specification

June 1982

may be daisy-chained to allow implemen- tation of a priority interrupt scheme. Little, if any, additional logIc is required for daisy-chaimng.

• Duplicate sets of both general-purpose and flag registers are prOVided, easing the design and operation of system soft- ware through Single-context SWItching, background-foreground programming, and single-level interrupt processing. In addi- tion, two l6-bit index registers facilitate program processing of tables and arrays.

• There arl'l three modes of high speed inter- rupt processing: 8080 compatible, non-Z80 penpheral device, and Z80 Family peripheral with or without daisy chain.

• On-chip dynamic memory refresh counter.

A" A"

A" A,

A" A,

A" A,

A" A,

elK A,

0, A,

0, A,

0, A,

0, A,

+5V As

0, GNO

0, RFSH

Do Mi

0, RESET

iNT BUSREQ

General Description

6

The Z80, Z80A, and Z80B CPUs are third- generation single-chip microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and third-generation microprocessors. The internal registers contain 208 bits of read/write memory that are accessible to the programmer.

These registers include two sets of six general- purpose registers which may be used individually as either 8-bit registers or as l6-bit register pairs. In addition, there are two sets of accumulator and flag registers. A group of "Exchange" instructions makes either set of main or alternate registers accessible to the programmer. The alternate set allows operation in foreground-background mode or it may be

+5V ...

GND ...

CLOCK ....

reserved for very fast interrupt response.

The Z80 also contains a Stack POinter, Pro- gram Counter, two index registers, a Refresh register (counter), and an Interrupt register.

The CPU is easy to incorporate into a system since it requires only a single + 5 V power source. All output signals are fully decoded and timed to control standard memory or peripheral CIrcuits, and it is supported by an extensive family of peripheral controllers. The internal block diagram (Figure 3) shows the primary functions of the Z80 processors.

Subsequent text provides more detail on the Z80 I/O controller family, registers, instruction set, interrupts and daisy chaining, and CPU timing.

_ - _ I I ALU

Figure 3. Z8D CPU Block Diagram

2001-0212

zao

Micro- processor Family

zao

CPU Registers

The Zilog Z80 microprocessor is the central element of a comprehensive microprocessor product family. This family works together in most applica!Jons with minimum requirements for additional logic, facilitating the design of efficient and cost-effective microcomputer- based systems.

Zilog has designed five components to pro- vide extensive support for the Z80 micro- processor. These are:

• The PIO (Parallel Input/Output) operates in both data-byte I/O transfer mode (with handshaking) and in bit mode (without handshaking). The PIO may be configured to interface with standard parallel peripheral devices such as printers, tape punches, and keyboards.

• The CTC (Counter/Timer Circuit) features four programmable 8-bit counter/timers, Figure 4 shows three groups of registers within the Z80 CPU. The first group consists of duplicate sets of 8-bit registers: a prinCipal set and an alternate set (designated by , [prime], e.g., A'). Both sets consist of the Accumula- tor Register, the Flag Register, and six general-purpose registers. Transfer of data between these duplicate sets of registers is accomplished by use of "Exchange" instruc- tions. The result is faster response to interrupts and easy, efficient implementation of such ver- satile programming techniques as background-

MAIN REGISTER SET

A ACCUMULATOR F FLAG REGISTER

B GENERAL PURPOSE C GENERAL PURPOSE

D GENERAL PURPOSE E GENERAL PURPOSE

H GENERAL PURPOSE L GENERAL PURPOSE

4 - - -8 BITS - - . .

. . . _ - - - 1 6 8 I T 5 - - - _

IX INDEX REGISTER

IV INDEX REGISTER

5P STACK POINTER

PC PROGRAM COUNTER

A'

B'

D'

H'

each of which has an 8-bit prescaler. Each of the four channels may be configured to operate in either counter or timer mode.

• The DMA (Direct Memory Access) con- troller provides dual port data transfer operations and the ability to terminate data transfer as a result of a pattern match.

• The SIO (Serial Input/Output) controller offers two channels. It is capable of operating in a variety of programmable modes for both synchronous and asyn- chronous communication, including Bi-Sync and SDLC.

• The DART (Dual Asynchronous Receiver/

Transmitter) device prOVides low cost asynchronous serial communication. It has two channels and a full modem control interface.

foreground data processing. The second set of registers consists of six registers with assigned functjons. These are the I (Interrupt Register), the R (Refresh Register), the IX and IY (Index Registers), the SP (Stack Pointer), and the PC (Program Counter). The third group consists of two interrupt status flip-flops, plus an addi- tional pair of flip-flops which assists in identi- fying the interrupt mode at any particular time. Table I provides further information on these registers.

ALTERNATE REGISTER SET

ACCUMULATOR F' FLAG REGISTER

GENERAL PURPOSE C' GENERAL PURPOSE

GENERAL PURPOSE E' GENERAL PURPOSE

GENERAL PURPOSE L' GENERAL PURPOSE

INTERRUPT FLlp·FLOPS STATUS

G G

~

INTERRUPTS DISABLED STORES IFF1

4 ~ :

INTERRUPTS ENABLED DURING NMI SERVICE INTERRUPT MODE FLIP-FLOPS

IMFa IMFb

Z80 CPU Registers (Continued)

Interrupts:

General Operation

8

Register

A,A' Accumulator

F, F' Flags

B, B' General Purpose C, C' General Purpose

D,D' General Purpose

E, E' General Purpose

H,H' General Purpose

L, L' General Purpose

Interrupt RegIster

R Refresh RegIster

IX Index RegIster

IY Index RegIster

SP Stack POinter

PC Program Counter

IFF1-IFF2 Interrupt Enable IMFa-IMFb Interrupt Mode

Size (Bits) 8 8 8 8 8 8 8 8

8 8

16 16 16 16 Fhp-Flops Fhp-Flops

Remarks

Stores an operand or the results of an operation.

See Instruchon Set.

Can be used separately or as a 16-blt regIster wIth C.

See B, above.

Can be used separately or as a 16-blt regIster WIth E.

See D, above.

Can be used separately or as a 16-blt regIster wIth L.

See H, above.

Note: The (B,C), (D,E), and (H,L) sets are combined as follows:

B - HIgh byte C - Low byte D - HIgh byte E - Low byte H - HIgh byte L - Low byte

Stores upper eIght bIts of memory address for vectored interrupt processing.

ProvIdes user-transparent dynamIc memory refresh. AutomatIcally Incremented and placed on the address bus during each Instruchon fetch cycle.

Used for Indexed addressing.

Same as IX, above.

Holds address of the top of the stack. See Push or Pop In Instruc- han set.

Holds address of next instruchon.

Set or reset to Indicate Interrupt status (see FIgure 4).

Reflect Interrupt mode (see Figure 4).

Table I. ZaD CPU Registers

The CPU accepts two interrupt input signals: • Mode I - Peripheral Interrupt service, for use with non-8080/Z80 systems.

NMI and INT. The NMI is a non-maskable interrupt and has the highest priority. INT is a lower priority interrupt and it requires that interrupts be enabled in software in order to operate. INT can be connected to multiple peripheral devices in a wired-OR configura- tion.

The Z80 has a single response mode for interrupt service for the non-maskable inter- rupt. The maskable interrupt, INT, has three programmable response modes available.

These are:

• Mode 0 - compatible with the 8080 micro- processor.

• Mode 2 - a vectored interrupt scheme, usually daisy-chained, for use with Z80 Family and compatible peripheral devices.

The CPU services interrupts by sampling the NMI and INT signals at the rising edge of the last clock of an instruction. Further interrupt service processing depends upon the type of interrupt that was detected. Details on inter- rupt responses are shown in the CPU Timing Section.

Interrupts:

General Operation (Continued)

Non-Maskable Interrupt (NMI). The non- maskable interrupt cannot be dIsabled by pro- gram control and therefore will be accepted at all times by the CPU. NMI is usually

reserved for servICing only the highest priority type interrupts, such as that for orderly shut- down after power failure has been detected.

After recognition of the NMI signal (providing BUSREQ is not active), the CPU Jumps to restart location 0066H. Normally, software starting at this address contains the interrupt service routing.

Maskable Interrupt (lNT). Regardless of the interrupt mode set by the user, the 280 response to a maskable interrupt input follows a common timing cycle. After the interrupt has been detected by the CPU (provided that interrupts are enabled and BUSREQ is not active) a special interrupt processing cycle begins. This is a special fetch (MI) cycle in which IORQ becomes active rather than MREQ, as in normal MI cycle. In addition, this special MI cycle is automatically extended by two WAIT states, to allow for the time required to acknowledge the interrupt request.

Mode 0 Interrupt Operation. This mode IS compatible with the 8080 microprocessor inter- rupt service procedures. The interrupting device places an instruction on the data bus.

This is normally a Restart Instruction, which wIll initiate a call to the selected one of eight restart locations in page zero of memory.

Mode I Interrupt Operation. Mode I oper- ation is very similar to that for the NMI. The principal difference IS that the Mode I inter- rupt has a restart location of 0038H only.

Mode 2 Interrupt Operation. This interrupt mode has been designed to utilize most effec- tively the capabilities of the Z80 microproc- essor and its associated peripheral family. The interrupting peripheral device selects the starting address of the interrupt service routine. It does this by placing an 8-bit vector on the data bus during the interrupt acknowl- edge cycle. The CPU forms a pointer using this byte as the lower 8-bits and the contents of the I register as the upper 8-bits. This points to an entry in a table of addresses for interrupt service routines. The CPU then jumps to the routine at that address. This flexibility in selecting the interrupt service routine address allows the peripheral device to use several dif- ferent types of service routines. These routines

may be located at any available location in memory. Since the Interrupting device sup- plies the low-order byte of the 2-byte vector, bit 0 (Ao) must be a zero.

Interrupt Priority (Daisy Chaining and Nested Interrupts). The interrupt priority of each peripheral device is determined by its physical location within a daisy-chain config- uration. Each device in the chain has an inter- rupt enable Input line (lEI) and an interrupt enable output line (lEO), which is fed to the next lower priority device. The first deVIce in the daisy chain has its lEI input hardwired to a High level. The first device has highest priority, while each succeeding device has a corresponding lower priority. This arrange- ment permits the CPU to select the highest priority interrupt from several simultaneously interrupting peripherals.

The interrupting device disables its lEO line to the next lower priority peripheral until it has been serviced. After servicing, its lEO line is raIsed, allowing lower priority peripherals to demand interrupt servicing.

The Z80 CPU will nest (queue) any pending interrupts or interrupts received while a selected peripheral is being serviced.

Interrupt Enable/Disable Operation. Two flip-flops, IFF) and IFF2, referred to in the register description are used to signal the CPU interrupt status. Operation of the two flip-flops is described in Table 2. For more details, refer to the ZaD CPU Technical Manual and ZaD Assembly Language Manual.

Action IFFl IFFZ Comments

CPU Reset 0 0 Maskable interrupt INT disabled Dr instructlon 0 0 Maskable mterrupt

execuhon INT disabled

EI instruction Maskable mterrupt

executIon !NT enabled

LD A,I mstruchon IFF2 - Parity flag execuhon

LD A,R instruction IFF2 - Panty flag execuhon

Accept NMI 0 IFFl IFFl - IFF2 (Maskable mter- rupt INT disabled) RETN instruchon IFF2 IFF2 - IFFI at

execution completion of an

NMI servICe routine.

Table 2. State of Flip-Flops

Instruction Set

8-Bit Load Group

10

The Z80 microprocessor has one of the most powerful and versatile instruction sets available ^In any 8-bit microprocessor. It includes such unique operations as a block move for fast, efficient data transfers within memory or between memory and 1/0. It also allows operations on any bit in any location in memory.

The folloWing is a summary of the Z80 instruction set and shows the assembly language mnemonic, the operation, the flag status, and gives comments on each instruc- tion. The Z80 CPU Technical Manual (03-0029-01) and Assembly Language Programming Manual (03-0002-01) contain significantly more details for programming use.

The instructions are divided into the following categories:

o 8-bit loads

o

16-bit loads

o Exchanges, block transfers, and searches

o

8-bit arithmetic and logic operations

o

General-purpose arithmetic and CPU control

Symbolic Flags

Mnemonic Operation S H P/V

1D r, r' r - r'

·

^{X X}

^·

LD r, n X X

·

LD,. (HLI , - (HLI X X

LD r, (IX+d) r - (IX+d)

·

^X

·

^X

·

LD '. (IY +dl , - (IY+dl X X

LD (HLI.' (HLI - , x x

·

LD (IX+d). , (IX+dl - , x x

·

LD (IY +dl. , (IY+dl - , x x

·

LD (HL). n (HL) - n X X

·

LD (IX+d). n (IX+d) - n X X

LD (IY +d), n (IY+d)-n

·

^X

·

^X

LDA. (BCI A - (BC) X

·

^X

LDA. (DE) A - (DEI X X

LDA. (nn) A - (nn)

·

^X

·

^X

LD (BC). A (BC) - A

·

^{X X}

LD (DEI. A (DEI - A

·

^X

·

^X

LD (nnl. A (nn) - A X X

LDA. I A-I X X IFF

LDA. R A-R X 0 X IFF

LD I. A 1- A X X

LDR. A R-A

'.

^{X X}

·

NOTES r, r' means any of Ihe reglsters A, E, C, D, E, H, L IFF the content of the mterrupt enable flip-flop, (IFF) IS

copied mto the PIV flag

For an explanahon of flag notahon and symbols for mnemOniC tables, see Symbolic Notahon sechon followmg tables

N C

o

16-bit arithmetic operations o Rotates and shifts

o

Bit set, reset, and test operations

o

Jumps

o

Calls, returns, and restarts o Input and output operations

A variety of addressing modes are implemented to permit efficient and fast data transfer between various registers, memory locations, and input/output devices. These addressing modes include:

o Immediate

o

Immediate extended

o

Modified page zero

o

Relative

o

Extended o Indexed

o

Register

o

Register indirect o Implied

o

Bit

Opccd. No.of No.of M No.of T

76 543 210 Ho. By ... Cycl .. Stat .. Commentl

01 , , _~

00 , 110 000 B

- n - 001 C

01 , 110 7 010 D

II Oll 101 DD 19 Oll E

01 , 101 100 H

- d - 101 L

II III 101 FD 19 III A

01 , 110 - d -

01 110 , 7

II 011 101 DD 19

01 110 ,

- d -

II III 101 FD 19

01 110 ,

- d -

00 110 110 36 10

- n -

II Oll 101 DD 19

00 110 110 36 - d - - n -

11 III 101 FD 19

00 110 110 36 - d - - n -

00 001 010 OA 7

00 Oll 010 lA 7

00 III 010 3A 13

- n -

00 000 010 02 7

00 010 010 12 7

00 110 010 32 13

II 101 101 ED 01 010 III 57 II 101 101 ED 01 011 III SF 11 101 101 ED 01 000 III 47 11 101 101 ED 01 001 111 4F

2001·001

16-Bit Load Symbolic Flu", Opcodo No.of No.oI M No.oI T

Group ^{Mumomc OporatloD S Z H PIV N C} 78 543 210 Ho. Byt . . Cye'" StClt . . CommoDIa

LD dd. nn dd - nn

·

^X

·

^X

·

00 ddO 001 3 3 10 dd Pair

oo-BC

- n - 01 DE

LO IX, nn IX - nn

·

^X

·

^X

·

11 011 101 DD 14 10 HL

00 100 001 21 11 SP

- n -

LD IY, nn IY - nn

·

^X

·

^X

·

11 111 101 FD 14

00 100 001 21 - n -

LD HL, (nn) H-(nn+l)

·

^X

·

^X

^·

00 101 010 2A 16

L - (nn)

- n -

LD dd, (nn) ddH - (nn+ 1)

·

^X

·

^X

·

11 101 101 ED 20

ddL - (nn) 01 ddl 011

- n -

LD IX, (nn) !XH - (nn+ 1)

·

^X

·

^X

·

11 011 101 DD 20

IXL - (nn) 00 101 010 2A

LDIY, (nn) IYH - (nn+ 1)

·

^X

·

^X

·

11 111 101 FD 20

IYL - (nn) 00 101 010 2A

- n -

Il

LD (nn), HL (nn+1) - H

·

^X

·

^X

·

00 100 010 22 16

(nn) - L

- n - @J

LD(nn), dd (nn+ 1) - ddH

·

^X

·

^X 11 101 101 ED 20

(nn) - ddL 01 ddO 011

Q

- n -

a

LD (nn), IX (nn+l) - IXH

·

^X

·

^X

·

11 011 101 DD 20

(nn) - !XL 00 100 010 22

- n -

LD (nn), IY (nn+ 1) - IYH

·

^X

^·

^X

·

11 III 101 FD 20

(nn) - IYL 00 100 010 22

LD SP, HL SP - HL

·

^X

·

^X

·

11 III 001 F9 6

LD SP, IX SP - IX

·

^X

·

^X

·

11 011 101 DD 10

11 111 001 F9

LD SP, IY SP -IY

·

^X

·

^X

·

11 III 101 FD 10

11 III 001 F9 ~

PUSH qq (SP-2) - qqL

·

^X

·

^X

·

11 qqO 101 11 00 BC

(SP-l) - qqH 01 DE

SP-SP-2 10 HL

PUSH IX (SP-2) - IXL

·

^{X X}

·

!l 011 101 DD 15 11 AF

(SP-l) - IXH 11 100 101 E5

SP-SP-2

PUSH IY (SP-2) - IYL

·

^X

·

^X

·

11 III 101 FD 15

(SP-l) - IYH 11 100 101 E5

SP-SP-2

POPqq qqH - (SP+ 1)

·

^X

·

^X

·

11 qqO 001 10

qqL - (SP) SP-SP+2

POP IX IXH - (SP+ 1)

·

^X

·

^X

^·

11 011 101 DD 14

IXL - (SP) 11 100 001 El

SP - SP +2

POPIY IYH - (SP+l)

·

^X

·

^X

·

11 III 101 FD 14

IYL - (SP) 11 100 001 El

SP-SP+2

NOTES dd IS any of the reg:1sler pairs BC, DE, HL, SP.

qq LS any of the register pdlfS AF, BC, DE, HL

{PAIRlH. (PAIR}L refer to high order and low order 61ght bits of the register p<:1.1r respectively, e,g , BCL = C, AFH = A

Exchange. EX DE, HL DE - HL

·

^X

·

^X

·

11 101 011 EB

Block EXAF, AF' AF - AF'

·

^X

·

^X

·

00 001 000 08

EXX BC - BC'

·

^X

·

^X

·

11 011 001 D9 Regtster bank and

Transfer. DE - DE' auxiliary register

Block Search ^{HL - HL'} bank exchange

EX (SP), HL H - (SP+l)

·

^X

·

^X

·

11 100 011 E3 19

Groups ^{L - (SP)}

EX (SP), IX IXH - (SP+l)

·

^X

·

^X

·

11 011 101 DD 23

!XL - (SP) 11 100 011 E3

EX (SP), IY lYH - (SP+l)

·

^X

^·

^X

^·

11 III 101 FD 23

IYL - (SP)

CD 11 100 011 E3

LDI (DE) - (HL)

·

^{X X} 11 101 101 ED 16 Load (HL) Into

Exchanste. Symbolic Flags Opc:ede No.oI No.oI M No.oI T

Block

-

^{0peratI0D s Z H PlY N C} 78 54S 210 llex Byt . . Cycleo SIa ... c:omm... ..

Transfer. ^(j)

Block Search ^LDD (DE) - (HL)

.

^{x X I} II 101 101 ED 16

Groups DE - DE-l 10 101 000 A8

HL-HL-l

(Continued) BC - BC-l

LDDR (DE) - (HL)

.

^{x 0 x 0 0} II 101 101 ED 21 liBC" 0

DE -DE-l 10 III 000 B8 16 liBC = 0

HL-HL-l Be - BC-l Repeat untIl BC = 0

Gl ^(j)

CPl A - (HL) X X I II 101 101 ED 16

HL-HL+l 10 100 001 Al

BC - BC-l

Gl CD

cpm A - (HL) X X II 101 101 ED 21 liBC" o and

A" (HL)

HL-HL+l 10 llO 001 Bl 16 IfBC=Oor

BC - BC-l A = (HL)

Repeat until A = (HL) or BC = 0

@ CD

CPD A - (HL) X X II 101 101 ED 16

HL-HL-l 10 101 oof A9

BC-BC-l

@ CD

CPDR A - (HL) X X II 101 101 ED 21 lfBC"Oand

A" (HL)

HL -HL-l 10 III 001 B9 16 IfBC=Oor

BC-BC-l A = ^(HL)

Repeat until A = (HL) or BC = ⁰

NOTES <D ^{PIV £lao IS} 0 d the result of Be -1 '" 0, otherwllle PN = 1

<3> ^{Z flag IS 1 If} A :: (HL), othel'WlBe Z ::: 0

8-Bit ADDA,r A_A+r X X V W~ r ~

Arithmetic ADD A, n A-A+n X X V lll@llO 000 B

and Logical ^{001 C}

010 D

Group ADD A, (HL) A-A+(HL) X X V 10 (QQQ] llO 7 Oll E

ADD A, (IX+d) A - A + (IX+d) X X V II Oll 101 DD 19 100 H

10 IQQl!lllO 101 L

-

^d

-

^{III A}

ADD A, (IY +d) A - A + (IY +d) X X V 0 II III 101 FD 19

WI@110

-

^d

-

ADCA,' A ... A+s+CY X X V rnQl] ^{SIS any of r, n,}

SUBs A-A-, X X v IQiQI (HL). (IX + d).

(lY + d) as shown

SBCA, s A - A-s-CY X X V [Qj] for ADD 1nstruchon.

AND, A-AAs X X P [@ The Indicated bIts

OR, A-Avs X X P IIiQJ replace the EiQQlm

the ADD set above

XORs A - A . s X X P IlIDJ

CPs A-, X X V (iIi]

INCr r - r + 1 X X V 00 r l!QID

INC (HL) (HL) -(HL) + 1 X X V 00 llO IImI II

INC (lX+d) (IX+d) - X X V II 011 101 DD Zl

(IX+d)+l 00 llO I!]!lJ

-

^d

-

INC (IY +d) (IY+d) - X X V 0

.

II III 101 FD Zl

(IY+d)+l 00 llOm

d

DECm m-m-l X X V 1 1m! ^{m IS} any of r, (HL),

(IX+d). (lY +d) as shown for INC DEC SlIme format and states as INC Replace IiQQJ wdh

!im]m opcode

12 ^2001-001

General- Symbolic Flag. Opcod.e No.of No.of M No.of T

Purpose ^{Mnemonic OperaUon S H P!V N C} 76 5t3 ZID lie. ^Bytes Cycles Stat •• Comments

Arithmetic ^DAA Converts ace content X X 00 100 III 27 DeCimal adjust

mto packed BCD accumulator.

and following add or

CPU Control subtract With packed BCD operands

Groups CPL A-A

·

^{X X} 00 101 III 2F Complement

accumulator (one's complement) .

NEG A-O-A X X V II 101 101 ED Negate acc, (two's

01 000 100 44 complement) .

CCF CY - CY X X X 00 III III 3F Complement carry

flag,

SCF CY - 1 X X 00 110 III 37 Set carry flag

NOP No operahon X X

·

00 000 000 00

HALT CPU halted

·

^{X X}

·

01 110 110 76

DI * ^{IFF - 0}

·

^{X X}

·

II 1l001l F3

EI * ^{IFF - 1}

·

^{X X}

·

II 111 Oll FB

IMO Set mterrupt

·

^{X X}

·

II 101 101 ED

mode 0 01000 110 46

IMI Set Interrupt X

.

^X II 101 101 ED

mode 1 01 010 110 56

1M2 Set Interrupt

·

^{X X}

·

11 101 101 ED

mode 2 01 Oll 110 5E

NOTES IFF mdlccltes the mlerrupt enable fhp-flop

i

CY indicates the carry flip-flop.

* mdlcates mterrupts are not sampled at the end of EI or DI

@)

IS·Bit ADD HL, ss HL - HL+ss X X X

·

00 ssl 001 II _~

Arithmetic ADC HL, ss HL - HL+ss+CY X X X V II 101 101 ED 15 ^{00 BC} 01 DE

Q

c:I

Group 01 ssl OlD 10 HL

11 SP

SBC HL, 55 HL - HL-ss-CY X X X V II 101 101 ED 15

01 ssO 010

ADD IX, pp IX-IX+pp

·

^{X X X}

·

11 011 101 DD 15 pp Reg.

01 ppl 001 00 BC

01 DE 10 IX II SP

ADD IY, rr lY - IY + rr

·

^{X X X}

·

II III 101 FD 15 rr Reg.

00 rrl 001 00 BC

01 DE 10 IY II SP

INC ss ss - ss + 1 X X 00 ssO all 6

INC IX IX .... IX + 1 X X 11 Oil 101 DD 10

00 100 Oil 23

INC lY IY - IY + 1 X X

·

II III 101 FD 10

00 100 011 23

DECss ss - 55-1 X X

·

^{00 ssl all 6}

DEC IX IX - IX-l X X 11 011 101 DD 10

00 101 Oll 2B

DEC IY IY - IY-l

·

^X

^.

^X

^·

II III 101 FD 10

00 101 Oil 2B NOTES 5S IS any of the register pcllrs Be, DE, HL, SP

pp IS any of the regIster pairs Be, DE, IX, SF rr IS any of the register pcllrS BC, DE, IY SP

Rotate and

Shift Group ^{RLCA @J~J}

·

^{X 0 X} 00 000 III 07 Rotate left cIrcular accumulator RLA l@j~

·

^{X 0 X} 00 010 III 17 Rotate left

accumulator

RRCA L~@J X 0 X

·

00001 III OF Rotate nght circular

accumulator RRA ~@}l ^{X )(}

·

00011 III IF Rotate nght

accumulator

RLCr X 0 X 11 001 011 CB Rotate left Circular

00 IQQQJ ' register r

RLC (HL) X 0 X 11 001 011 CB 15 ~

00 I2QiiJ 110 000 B

001 C

@J~J X 0 X P II Oil 101 DD 23 010 D

RLC (lX+d) 011 E

dHL),(IX+d).(IY +d) 11 001 011 CB 100 H

-

_I§QQJ ^d

^-

^{101 L}