A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing

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A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing

Nicolas Mechouk, Dominique Dallet, Lilian Bossuet and Bertrand Le Gal University of Bordeaux, IPB, IMS CNRS UMR5218

IMS Bat A31, 351 crs Liberation, 33405 Talence - France Email: nicolas.mechouk@ims-bordeaux.fr

Abstract-This paper focused on a filter bank study used for ADC BIST. Filter selection to separate spectral components of an analog-to-digital converted signal are discussed. Regarding the BIST context, a method to realize the lowest cost filter bank is proposed. This task has been done taking into account the word

lenght of the input and clock frequencies and the filter coefficient values.

I. INTRODUCTION

Testing an analog-digital IC (ADC) has become a difficult task. Due to the constant increase of analog circuit density and speed, more and more complex test equipment is required to test its functionality, which is both expensive and time

consuming. One solution is the Built-In Self Test (BIST) approach, in which both stimuli generation and output analysis are performed on-chip. BIST permits to reduce the test cost per chip for high volume production.

Many research groups propose several techniques to achieve self-test of an ADC. Two techniques, the Hybrid Built-In Self Test (HBIST) [I], [2] and the Oscillation-based Built-In Self Test (OBIST) [3], [4] lead to classify the IC as functional or not by comparing a experimental signature to a theoretical one.

The Histogram-based Analog Built-in Self Test (HABIST) technique [5], [6] and the Polynomial fitting method (pEIST) [7] allows to determine some ADC parameters by comparing a measured code density histogram to the ideal one (HABIST) and from the coefficients of the third-order polynomial which best fits the transfer function of the ADC (PEIST). The Least Significant Bit (LSB) based EIST (LEIST) technique [8] monitors the LSB of a ADC to determine its linearities with a low-frequency signal as stimulus.

Lowpass 6:1:

F

Fig. I: The BIST scheme.

The last technique, the Mixed Analog-Digital EIST (MAD

BIST) [9] is based on a frequency analysis. A �L: oscillator is used for stimulus generation and some digital signal pro

cessing techniques analyze the converted signal. Nevertheless, both on-chip ADC and DAC, using large area, are needed

and intensive computation is not efficient. The proposed BIST scheme in this work [10], [II] which is inspired by the MADBIST technique is described in figure I. The required functional blocks are as follow :

• The LP �L: oscillator is a digital oscillator using a lowpass delta-sigma modulator to generate a single bit stream.

• The Lowpass analog filter converts the single bit stream in an analog signal.

• The Filter bank separates the different harmonics of the converted signal.

• The Decision block calculates the Signal-to-Noise Ratio (SN R) and checks if it matches the ADC specifications.

The SN R will be compute from the power of each spectral component (fundamental, harmonics and noise) to perform a Go/No-Go test with a 0.5 LSB tolerance. The lowest cost filter bank for our BIST scheme will be presented taking into account the fundamental frequency value. The targeted ADC is a

12

bit monolithic ADC [12] with a sample rate at

41

MSPS and its typical SN R is 68 dB.

In section II, the notch filter is presented with its structures and optimizations. In section III, the methodology to realize the lowest cost filter bank regardless the frequency are detailed with an example. Finally, conclusion is drawn in section IV.

II. FILTER BANK AND NOTCH FILTER

The aim of the filter bank is to separate the different harmonic, the fundamental and the noise from the converted signal. Several bandpass and notch filters are used. Each filter must include less noise than the ADC. Figure 2 describes the structure of the filter bank prresented in [10].

Fig. 2: Bank filter structure.

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Fundamental and harmonic components are isolated thanks to a triangular matrix organisation of the notch filter cells. In this work, we consider the first four harmonics in the converted signal. As shown in Figure 3, the notch filter is composed of a biquad resonator used to select the harmonic signal

Xbp

from the input

Xin

and a subtracter between the input

Xin

and the bandpass output

Xbp

to obtain the notch output

Xnt.

XiII +. XIII

Fig. 3: Notch filter structure.

A. Theoretical study of the resonator filter

A biquad resonator is an

2 nd

order bandpass filter. Although there are several options for zero placing, an interesting solution is to set

z

⁼

1

and

z

⁼

-1

for a complete elimination of spectral components localized at the normalized angular frequencies 0 ⁼ ° and 0 ⁼

7r.

The normalized angular frequency 0 is defined as

2 7r is

^where

^Fs

is the sampling frequency. The resulting transfer function is:

1 _{- r2} (1 _-Z-2)

Hb (z) - p - --

(1)

2 1 -(2 rcosB)z-l + r2z-2

where rand

B

are respectively the radius and the angle of the conjugate poles of

Hbp.

This transfer function has a unity gain at the normalized resonance angular frequency

Or

=

2 7r k

given by:

fr ( ^{2 r} )

Or

=

2 7r-F ;::::: arccos --- _{2 cos B}

s 1 _{+ r}

⁽²⁾

where

fr

is the resonance frequency. Note that the more

r

is close to

1,

the more 0 is close to

B.

An important feature of the resonator is the 3dB-bandwidth, which is approximately:

l - r

B-3dB

;::::: --

(3)

7r

when

r ;::::: 1.

In this case, only the radius of conjugate pole leads to the bandwidth. After the choice of the bandwidth, the angle of the conjugate poles is computed from the normalized resonance angular frequency:

B

⁼

arccos ( ¹ ; ^{rr2 cos} ^Or )

B. Theoretical study of notch filter

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The transfer function of notch filter

Hnt

⁼

1 _-Hbp(Z)

is:

2 2

1-i�r -(2 r cos B)z-l + l1{ z-2 Hnt(z)

⁼

1-(2 r cos B)Z-l + r2z-2

⁽⁵⁾ The normalized cutoff angular frequency and the bandwidth of the notch filter are respectively equal to the normalized res

onator angular frequency and the bandwidth of the resonator.

Figure 4 shows the normalized frequency response of a notch filter.

Fig. 4: Frequency response of the notch filter with

fr _{/ F}

s =

0,2 and two different bandwidths

( r

⁼^0,8,

r

⁼^0,95).

The operating principle of a notch filter (cutoff frequency and bandwidth) being given, we will present different archi

tectures for its implementation.

C. Discussion about architecture optimization

Several architectures are proposed to realize the transfer function of the resonator filter. In this work, two structures are studied: the first one is the classical transposed-form (TF) [13]

and the second one is based on the Lossless Discrete Integrator (LDI) [10] [14]. Their transfer functions, respectively

Ht

f and

Hld i,

are:

Ht (z)

_f ⁼

bo(1 _{+ Z-l} )(1 _-Z-l) 1 + alz-l + a2z-2

where

bo

=

(1 - r2)/2 , al

⁼

-2 r cos B , a2

⁼

r2

and

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-k2 (l+z-l)(I-z-l)

Hld i ( _Z )

=

-2 -

^x

1

_

(2

^_

k2

^_

knz-l + (1

_

k2)Z-2

(7) where

kl

⁼

VI + r2 -2 r cos

^Band

k2

⁼

l-r2. al

and

kl

are used to select the resonance frequency whereas

bo, _a2

and

k2

are use to set the bandwidth. Figure 5 describes respectively the TF structure on the left and the LDI structure on the right.

Fig. 5: TF (left) and LDI (right) structures of resonator filter.

Both structures have to be optimized by reducing the num

ber of multipliers. This can be done by replacing multipliers by shift registers. In our case, it was done by choosing

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r = V1 - 2 3, which is close to 1 and ensures a good filter selectivity. It leads to the following values:

bo

= 2-4,

a2

⁼1 - 2-4 and

k2

⁼2-3. So, the multiplication by

bo

and

k2

leads to a shifting of respectively 4 and 3 bits to the right.

The multiplication by

a2

is realized by a shifting of 4 bits to the right and a subtraction between the input signal and the shifted one. Unfortunatley, this procedure cannot be applied to

al and

k1,

which are used to select the resonance frequency. It means that these coefficients has to be study in term of coding and internal signals coding.

D. Coefficient precision

To determine the coefficient precision, the filter bank is simulated for each structure using a real converted signal as input. The first simulation is an IEEE Standard 754 floating

point [15] simulation and the S N R is computed. Each filter bank is then fixed-point simulated as function of the coefficient precision and the SNR is computing. Figure 6 shows the simulation results.

70 ;, . . .

... .

^• ^•

65

---

/: ^� ^� ^:

^;^:x

^;:-tt-o�::

^�---

�

/!

⁷¹²⁴

1

�

60

·_·_·_·4 !

^{71 22}

CI)

!

^{71 2}

55 _i

7118

/

^{12 13}

50 __ --�

1 ·· ··· · ··· · ··

� i � 0 � m

;1

� � D

I

Floating point SNR

��::i:�i��N(�

T )3 dB

4!i'\;-2 ----='''''3 ---='4':--�'5,---�'6,---7.17;---':-;1:�-F

�lXed�,9�po�m��

�

^N^�^R^�⁽

�

^�

�

^"=^I⁾^=!!^2·2

Size of the radix part of the coefficients

Fig. 6: Signal-to-Noise Rate as function of the size of the coefficient precision.

This figure can be used to determine the precision of the coefficients versus the precision of the measure as function of the constraints or to select the optimal case. Here, the floating

point SNR is 71.21 dB as the SNR computed from the IEEE Standard 1241 FFT [16] (70.45 dB) with a 1% bias [17].

As expected, the LDI structure is more quantification noise resilient than the TF structure, and the floating point S N R is matched for a coefficients with 20 radix bits versus 21 for the TF structure. The goal of this work is to propose an efficient architecture for go-no-go ADC testing with a bias of 3 dB for the SN R estimation. In this case, 14 radix bits are enough for the LDI structure versus 16 for the TF structure.

E. Coefficients and signals coding

1) TF structure: For this structure, the coefficient precision is 16 bits. As al < 2, its coding format is (18,1,16). ADC output is a signed integer 12-bit signal, so its coding is (12,11,0). In order to do not include additional quantization noises, maximum precision on internal signals will be kept

(29,12,16). This coding is also adopted for the input and the output of each filter.

2) LDI structure: The coefficient precision for this structure is 14 bits. By definition

k

^l < 2, so its coding is (16,1,14) and the internal signal coding is (17,12,14) as the input one.

In the next section, two methods to realize a lowest cost filter bank for the BIST scheme and a lowest cost filter bank for a given frequency are presented.

III. THE LOWEST COST FILTER BANK A. Best frequency research

Multiplications are the most expansive operations. But, in order to reduce the area used by the operator, a multiplication by a fixed-point constant can be done "multiplierless" using additions (or subtractions) and shifts [18]. A straightforward way of mUltiplying by a given constant c using add/subtracts and shifts can be obtained using specific bit representation of

c. For example, the Canonical Signed Digit (CSD) recoding increases the number of '0' in c representation and reduces the number of add/subtracts operators. The area used by Shift

and-Add multiplier depends on Hamming weight (PH) of the coefficient after CSD recoding. The Hamming weight of a binary number is the number of non-zero bits. Specifically, the bigger the Hamming weight is, the larger the multiplier is. So for each structure, we make a study of the evolution of the filter bank hamming weight (equation 8) depending on the input frequency of the filter bank for a fixed bandwidth.

This study corresponds to a study of the number of add/sub operator in the filter bank. The multiplication part of the filter bank weight corresponds of the sum of the Hamming weight of the coefficient after CSD recoding for each cell of the filter bank, ie. the number of '1' (or '-1') of the coefficients for each multiplication in the filter bank.

W ⁼

(2..:

_cells^PH

⁺ ⁽

^ncells

⁾

^x

⁽

^naddlsub

⁾ )

^x^size^c^o^e^f ⁽⁸⁾

where ncells is the number of cell in each filter bank, naddlsub

is the number of add/subtract in each cell and sizecoef is the number of bits of the coefficient. Figure 7 shows the filter bank weight for each filter structure depending of the fundamental frequency (the number of points shown in the graph has been reduced for easier reading).

For the TF structure based filter bank (named TF bank), the filter bank weight is minimal (1080) for

fa

= 4.006 MHz.

On the other side, for the LDI bank, the filter bank weight is minimal (1440) for 2 different frequencies:

fb

= 1.569 MHz and

fc

= 2.360 MHz.

B. Architectural synthesis

In order to make sure that the minimal filter bank weight is the filter bank using the smallest area, the architectural synthesis of the filter bank for two frequencies are made with Xilinx ISE 10.1 for a Xilinx Virtex IV FPGA. Table I shows the results.

720

(4)

32oo,---�--�--�--_____r��=;=;]

I x

^{TF bank}

3000 o LDI bank

o o

100%�-�0�.1�--70.72--�

x

0�.3�--0�.4�-�0.5

Normalized frequency at F s

Fig. 7: Weight of TF filter bank and LDI filter bank as function of the fundamental frequency value.

Fundamental Slice Slice FF 4-LUT Min.

frequency number number number frequency

TF fa ²⁸²⁹ ¹⁹⁹⁶ ⁵²⁰² ^{109 MHz}

LDI fe ³⁵⁸¹ ¹⁹³² ⁷²²⁶ ^{51 MHz}

TABLE I: Results of architectural synthesis of the filter bank.

The filter bank using the TF structure is smaller than the LDI filter bank as their respective weights. The smallest filter bank to test this ADC uses 2829 slices at 4.006 MHz.

C. Verification

A post-Place&Route simulation with MentorGraphics Mod

elSim is performed to verify the behavioral of the smallest filter bank using a real converted signal as input. Figure 8 shows the fundamental output spectrum of the filter bank. As expected, only the fundamental component is taken while the others harmonics are rejected. The SN R computed from the filter bank outputs (68.5dB) is 3 dB less than the floating point SNR as anticipated. This SNR estimation is a correct estimation of ADC SN R.

Frequency (MHz)

Fig. 8: Fundamental output spectrum.

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IV. CONCLUSION

In this paper, a low-area filter bank design study for on

chip ADC testing is presented. A metric is defined to select the lowest area filter structure. Then this metric is used on TF and LDI structure to study the lowest area filter bank. Comparing different works [14], [10] and unlike what one might think, we prove that the TF structure is better than the LDI one.

This filter bank is then post-Place&Route simulated in order to extract its performances. The SN R computed from this simulation is a correct estimation of the ADC SN R with an error less than 3 dB from the SNR computed from the IEEE Standard 1241 FFT. This design methodology can be used to realized the lowest area filter bank for a given frequency.

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A Low-Area Filter Bank Design Methodology for On-Chip ADC Testing