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RDATA 101

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IDEV

IENABLE

(2)

Notes on IWM interface:

The IWM Interface Is a PAL which has several functions. It monitors the write data Hnes of the IWH's of both the host and Nisha. It also monitors the state of the phase Hnes coming from the host IWH. It produces read data pulses based on the phase I ines· state and based on transitions seen on either of the write data lines. The PAL also produces controller reset and two handshaking lines: eMD and HOLOOFF.

In order to produce read data pulses, the PAL sees the transitions on the write data lines and outputs a high going pulse of a duration of two c lock periods. This pulse is output on the read data 1 ine. Read data is enabled when the signal IENABLE is asserted low. The read data Hne is held high unless the phase lines are in the following states:

93 ,,2 9 J ,,0 read data Jevel l O X X

o

^{1 0} ¹

o

^{read data}

In order to read data the phase 1 ines must be in the correct state (as indicated above-I OXX).

The PAL produces the signal IDEV when both IDS and IFaX are asserted. Thus IDEV fol1ows IDS when the correct address (FaX) is asserted on the address bus. Shown below is timing for a write to the IWM:

/FBX

\ ____________ 1

IDS ^\_\

Address Valid

Data ^\~_J~ Valid

IDEV \ I

r... .J

td tdh

Mv

td (IDS to IDEV delay time) =- IOns

tdh (/OEV to write data not vaHd de1ay) • 60 ns tdv (write data valid to IOEV) • 60 ns

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The signal IRESET 1s asserted low when the phase lines are 1100 and the stgnal IENABLE Is asserted low.

(3)

The s1gnal leMD Is asserted low when the phase 1 ines are lOX 1 and the signal IENABLE is asserted low.

The 51 gna 1 lHOLDOFF 1s asserted low when the phase I tnes are 1 0 1 X and

the signal IENABLE is asserted low.

Because IRESET, ICMD, and lHOLOOFF are s1gnals which are gated through flip-flops internally within the PAL, they are synchronized with the clock.

(4)

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