o VLSI TECHNOLOGY, INC

may be used as a pointer to the appro-priate interrupt service routine. When IIR(O) is high, no interrupt is pending.

IIR(1) and IIR(2) are used to identify the highest priority interrupt pending as indicated in Table 2.

IIR(3) - IIR(7): These five bits of the IIR are logic O.

The Interrupt Enable Register (IER) is a Write register used to independently enable the four serial channel interrupts which activate the interrupt (INTRPT) output. All interrupts are disabled by resetting IER(O) - IER(3) of the Interrupt Enable Register. Interrupts are enabled by setting the appropriate bits of the IER high. Disabling the interrupt system inhibits the Interrupt Identification Register and the active (high) INTRPT output. All other system functions operate in their normal manner, includ-ing the settinclud-ing of the Line Status and Modem Status Registers. The contents of the Interrupt Enable Register is de-scribed in Table 3 and below:

IER(O): When programmed high [IER(O} ... Logic 1], IER(O} enables Received Data Available interrupt.

IER(1}: When programmed high [IER(1)=Logic 1], IER(1) enables the Transmitter Holding Register Empty interrupt.

IER(2): When programmed high [IER(2}=Logic 1], IER(2) enables the Receiver line Status interrupt.

IER(3): When programmed high [IER(3) .. Logic 1], IER(3) enables the Modem Status Interrupt.

IER(4) - IER(7): These four bits of the IER are logic O.

TRANSMIITER

The serial transmitter section consists of a Transmitter Holding Register (THR), Transmitter Shift Register (TSR), and associated control logic. The Transmit-ter Holding RegisTransmit-ter Empty (THRE) and Transmitter Shift Register Empty (TEMT) are two bits in the Line Status Register which indicate the status of THR and TSR. To transmit a 5- to 8-bit word, the word is written through 00-07 to the THR. The microprocessor should perform a write operation only if TJiRE is high. The THRE is set high when the word is automatically transferred from

the THR to the TSR during the transmis-sion of the start bit.

When the transmitter is idle, THRE and TEMT are high. The first word written causes THRE to be reset to O. After the transfer, THRE returns high. TEMT remains low for at least the duration of the transmission of the data word. H a second character is transmitted to the THR, the THRE is reset low. Since the data word cannot be transferred from the THR to the TSR until the TSR is empty, THRE remains low until the TSR has completed sending the word. When the last word has been transmitted out of the TSR, TEMT is set high. THRE is set high one THR to TSR transfer time later.

RECEIVER

Serial asynchronous data is input into the SIN pin. The idle state of the line providing the input into SIN is high. A start bit detect circuit continually searches for a high to low transiticm from the idle state. When the transition is . detected, a counter is reset, and counts the 16X clock to 7 1/2, which is the center of the start bit. The start bit is valid if the SIN is still low at the mid-bit sample of the start bit. Verifying the start bit prevents the receiver from assembling a false data character due to a low going noise spike on the SIN input.

The Line Control Register determines the number of data bits in a character (LCR(O), LCR(1», number of stop bits LCR(2}, if parity is used LCR(3), and the polarity of parity LCR(4). Status for the receiver is provided in the Line Status Register to the Receiver Buffer Register, the Data Received indication in LSR(O) is set high. The CPU reads the Receiver Buffer Register through 00-07. This read resets LSR(O}. If 00-07 are not read prior to a new character transfer from the RSR to the RBR, the overrun error status indication is set in LSR(1).

The parity check tests for even or odd parity on the parity bit, which precedes the first stop bit. H there is a parity error, the parity error is set in LSR(2). There is circuitry which tests whether the stop bit is high. H it is not, a framing error indication is generated in LSR(3}.

The center of the start bit is defined as clock count 7112. If the data into SIN is symmetrical square wave, the center of the data cells will occur within

VL16C452

+/-3.125% of the actual center, providing an error margin of 46.875%.

The start bit can begin as much as one 16X clock cycle prior to being detected.

BAUD RATE GENERATOR (BRG) The BRG generates the clocking for the UART function, providing standard ANSI/CCITT bit rates. The oscillator driving the BRG is provided by an external clock into CLK.

The data rate is determined by the Divisor Latch registers DLL and DLM and the external frequency. The bit rate is selected by programming the two divisor latches, Divisor Latch Most Significant Byte and Divisor Latch Least Significant Byte. Setting DLL=1 and DLM .. O selects the divisor to divide by 1 (divide by 1 gives maximum baud rate for a given input frequency at the CLK input).

The BRG can use any of three different popular frequencies to provide standard baud rates. These frequencies are 1.8432 MHz, 2.4576 MHz, and 3.072 MHz. With these frequencies, standard bit rates from 50 to 38.5 kbps are available. Tables 7, 8, and 9 illustrate the divisors needed to obtain standard rates using these three crystal frequen-cies.

RESET

After power up, the VL 16C452 -RESET input should be held low for 500 ns to reset the VL 16C452 circuits to an idle mode until in~ialization. A low on -RESETcauses the following:

1. Initializes the transmitter and receiver internal clock counters.

2. Clears the Line Status Register (LSR), except for Transmitter Shift Register Empty (TEMT) and Transmit Holding Register Empty (THRE), which are set. The Modem Control Register (MCR) is also cleared. All of the discrete lines, memory elements and miscellane ous logic associated with these register bits are also cleared or turned off. The Line Control Register (LCR), Divisor Latches, Receiver Buffer Register, Transmit ter Buffer Register are not effected.

Following removal of the reset condition (Reset high), the VL 16C452 remains in the idle mode until programmed.

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A hardware reset of the VL 16C452 sets the THRE and TEMT status bit in the LSR. When interrupts are subsequently enabled, an interrupt occurs due to THRE.

A summary of the effect of a reset on the VL 16C452 is given in Table 10.

PROGRAMMING

Each serial channel of the VL 16C452 is programmed by the control registers LCR, IER, DLL and DLM, and MCR.

These control words define the charac-ter length, number of stop bits, parity, baud rate, and modem interface.

While the control register can be written in any order, the IER should be written to last because it controls the interrupt enables. Once a serial channel is programmed and operational, these registers can be updated any time the VL 16C452 serial channel is not transmitting or receiving data.

The control signals required to access each serial channel's internal registers are shown below.

SOFlW ARE RESET

A software reset of the serial channel is a useful method for returning to a

VL16C452

completely known state without a system reset. Such a reset consists of writing to the LCR, Divisor Latches, and MCR registers. The LSR and RBR registers should be read prior to enabling interrupts in order to clear out any residual data or status bits which

may

be invalid for subsequent operation.

CLOCK INPUT OPERATION The maximum input frequency of the external clock of the VL 16C452 is 3.1 MHz.

TABLE 7. BAUD RATES (1.8432 MHz CLOCK)

DesIred

TABLE 8. BAUD RATES (2.4576 MHz CLOCK)

TABLE 9. BAUD RATES (3.072 MHz CLOCK)

DesIred

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TABLE 10. RESET

Register/Signal Interrupt Enable Register Interrupt Identification Register

Line Control Register MODEM Control Register Line Status Register MODEM Status Register SOUT

Intrpt (RCVR Errs) Intrpt (RCVR Data Ready) Intrpt (THRE)

Intrpt (Modem Status Changes) -Out2

-RTS -DTR -Out1

DEVICE APPLICATION

DATA BUS

ADDR BUS

CTL BUS

Reset Control Reset

Reset Reset Reset Reset Reset Reset

Read LSRlReset Read RBRlReset Read IIRlWrite THRlReset Read MSRlReset Reset

Reset Reset Reset

VL16C452

DUAL UARTAND

PRINTER PORT

VL16C452

Reset

All Bits Low (0-3 forced and 4-7 permanent) Bit 0 is High, Bits 1 and 2 Low

Bits 3-7 are Permanently Low All Bits Low

All Bits Low

All Bits Low, Except Bits 5 and 6 are High Bits 0-3 Low

Bits 4-7 Input Signal High

Low Low Low Low High High High High

SERIAL CHANNEL 0

BUFFERS

SERIAL CHANNEL 1

BUFFERS

PARALLEL PORT RIC NET

9--PIN

"0"

CONN

9--PIN CONN

I

^25-PIN "D"

1----11. CONN

FUNCTIONAL DESCRIPTION

PARALLEL PORT REGISTERS The VL 16C4S2's parallel port interfaces the device to a Centronics-style printer.

When Chip Select 2 (-CS2) is low. the parallel port is selected. Table 11 shows the registers associated with this parallel port. The read or write function of the register is controlled by the state of the read (-lOR) and write

(-lOW) pin as shown. The Read Data Register allows the microprocessor to read the information on the parallel bus.

The Read Status Register allows the microprocessor to read the status of the printer in the five most significant bits.

The status bits are Printer Busy (-BUSY). Acknowledge (-ACK) which is a handshake function. Paper Empty (PE). Printer Selected (SLCT). and Error

(-ERROR). The Read Control Register allows the state of the control lines to be read. The Write Control Register sets the state of the control lines.

TABLE 11. PARALLEL PORT REGISTERS

Register Register Bits

Bit? Bit 6 BitS Bit 4

Read Data PD? PD6 PD5 PD4

Read Status -BUSY -ACK PE SLCT

Read Control 1 1 1 IRQENB

Write Data PD? PD6 PD5 PD4

Write Control 1 1 1 IRQENB

TABLE 12. PARALLEL PORT REGISTER SELECT

Control Pins Register Selected

-lOR -lOW -CS2 A1 AO

0 1 0 0 0 Read Data

0 1 0 0 1 Read Status

0 1 0 1 0 Read Control

0 1 0 1 1 Invalid

1 0 0 0 0 Write Data

1 0 0 0 1 Invalid

1 0 0 1 0 Write Control

1 0 0 1 1 Invalid

They are Interrupt Enable (IRQ ENB).

Select In (SLlN). Initialize the Printer (-INIT). Autofeed the Paper (AUTOFD).

Strobe (STROBE). which informs the printer of the presence of a valid byte on the parallel bus. The Write Data Register allows the microprocessor to write a byte to the parallel bus.

The parallel port is completely compat-ible with the parallel port implementa-tion used in the IBM SeriallParaliel Adaptor.

Bit3 B~ 2 Bit 1 Bit 0

PD3 PD2 PD1 PD~

-ERROR 1 1 1

SUN -INIT AUTOFD STROBE

PD3 PD2 PD1 PDO

SUN -INIT AUTOFD STROBE

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AC CHARACTERISTICS

TA= O°C to +70°C, VCC= 5 V ±50/0 (Notes 1,5)

Symbol Parameter Min Max Units

tOlW -lOR Strobe Width 125 ns

RC Read Cyle 360 ns

tODD Delay from -lOR to Data 125 ns

tHZ -lOR to Floating Data Delay 0 100 ns

tOow -lOW Strobe Width 100 ns

WC Write Cycle 360 ns

tOs Data Setup Time 40 ^ns

tOH Data Hold Time 40 ns

tRA Address Hold Time from -lOR 20 ns

tRCS Chip Select Hold Time from -lOR 20 ns

tAR -lOR Delay from Address 60 ns

tCSR -lOR Delay from Chip Select 50 ns

tWA Address Hold Time from-lOW 20 ns

tWCS Chip Select Hold Time from -lOW 20 ns

tAW -lOW Delay from Address 60 ns

tCSW -lOW Delay from Select 50 ns

tRW Reset Pulse Width 5 JlS

tXH Duration of Clock High Pulse 140 ns

tXL Duration of Clock Low Pulse 140 ns

Notes:

1. All timing specifications apply to pins on both serial channels (e.g. RI refers to both RIO and RI1).

2. The internal address strobe is always active.

3. RCLK

=

tXH and tXL.

4. Charge and discharge time is determined by VOL, VOH and the external loading.

5. All timings are referenced to valid 0 and valid 1.

(see AC TEST POINTS).

6. RCLK is internally derived from the internal-BAUDOUT signal.

VL16C452

Conditions

100 pF Load 100 pF Load, Note 4

Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2

External Clock External Clock

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VL16C452

AC CHARACTERISTICS

(Cant.) TA= O°C to +70°C, VCC= 5 V ±5% (Notes 1, 5)

Symbol Parameter Conditions

Transmitter

tHR1 Delay from Rising Edge of -lOW

175 ns 100 pF load

(WR THR) To Reset Interrupt

tlRS Delay from Initial INTR Reset to Transmit Start 16 ClK

Note 3 Cycles

ClK

tSI Delay from Initial Write to Interrupt 8 24 Cycles Note 3

tSTI Delay from Stop to Interrupt (THRE) 8 ^ClK Note 3

Cycles tJR Delay from -lOR (RD IIR)

250 ns 100 pF load

to Reset Interrupt (THRE) Modem Control

tMDO Delay from -lOW

250 ns 100 pF load

(WR MCR) to Output

tSIM Delay to Set Interrupt from MODEM Input 250 ns 100 pF load

tRIM Delay to Reset Interrupt from

250 ns 100 pF load

-lOR (RS MSR) Receiver

tSINT Delay from Stop to Set Interrupt 1 ClK Note 3

Cycles tRINT Delay from -lOR

1 Ils 100 pF load

(RD RBR/RDlSR) to Reset Interrupt Parallel Port

tOT Data Time 1 Ils

tSB Strobe Time 1 500 Ils

tAD Acknowledge Delay (Busy Start to Acknowledge) Ils Defined by Printer

tAKD Acknowledge Delay (Busy End to Acknowledge) JlS Defined by Printer

tAK Acknowledge Duration Time IlS Defined by Printer

tBSY Busy Duration Time IlS Defined by Printer

tBSD Busy Delay Time JlS Defined by Printer

Notes:

1. All timing specifications apply to pins on both serial channels (e.g. RI refers to both RIO and RI1).

2. The internal address strobe is always active.

3. RClK - tXH and tXL.

4. Charge and discharge time is determined by Val, VOH and the external loading.

5. All timings are referenced to valid 0 and valid 1 (see AC TEST POINTS).

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VL16C452

WRITE CYCLE TIMING

A2 A1 AD ---vA~L~ID~---:

-CS VALID

-lOW

tCSW • WC---~~

i

__________

tA_W_-_-_-_-_-_-_-:~---I~

^________

~)(~l..---

^ACTIVE

•

---t---{~---~ACTIVE

OR

-lOR

1\

tDS

I ^"tDH~

DATA - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~\ VALID DATA

)L _______________ _

00-07

READ CYCLE TIMING

A2 A1 AD VALID

tRA

-cs

^VALID

"tRCS

tCSR

•

iACT,VE

RC tAR

-lOR

)2

•

~

OR

VCTIVE -lOW

tODD

~~

_{• VALID} ^- _~\....

I-

_{_____} ^1HZ _{_}

DATA

---'""1

DATA

I

00-07

VL16C452

RECEIVER TIMING

SIN\ d

(RECEIVER START ~TA BITS (5-8) INPUT

DATA)

INTERRUPT

=t

RCVR ERR) tAINT

(DATA READY OR

t

-lOR - - - - \ ACTIVE

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