EFFECTIVE ADDRESS CALCULATION
3.6 USER/MONITOR MODE AND THE INTERNAL INTERRUPTS
3.6.1 User/Monitor Modes
Every 8400 is equipped with a feature to facilitate multi-programming and time sharing. 'rhe User/
Monitor mode feature prevents a user program from interfering with the continuous operation of the com-puter. In USer mode, any instruction that initiates input/output operations or modifies the state of cer-tain control register is not executed. In monitor mode all instructions are permitted.
The monitor mode flip-flop controls the mode of the computer. The machine is placed in monitor mode when any interrupt occurs, or by the INITIALIZE button from the console. The flip-flop can be reset and tested by the following instruction:
SFL = '65,,0 Reset Monitor Mode TSL = '65,,0 Test Monitor Mode
The Reset Monitor mode instructiop., in addition to placing the machine in :usermode, also enables the interrupt system. Once in user mode, the interrupts cannot be disabled. The interrupts can then be dis-abled only after an interrupt has occurred, and the machine has been returned to monitor mode.
Instructions that cannot be executed in user mode are called privileged instructions. They are:
1. LDT, LDM, LDE, LDC 2. SFL, TSL
3. LDOB, STm
4. LDCD, STCD, LDCC, STCC 5. HJ
When one of these instruction is attempted in user mode, the instruction is not executed, a privileged instruction flip-flop is set, and an interrupt is gen-erated. The privileged instruction flip-flop can be tested and reset with the following instructions:
SFL = '21,,0 Reset Privileged Instructions TSL = '21n 0 Test Privileged Instructions Other illegal instructions generate this interrupt as usual, but do not set the Privileged Instruction flip-flop.
Since the interrupt system cannot be disabled in user mode, instructions that refer to the E flag in the flag register are not allowed to change its state. Instruc-tions of this type are executed, but do not affect the E flag, as shown by the following:
Instruction JSE JSNE JRE
Acts Like JE JNE JE
lns true tion Acts Like
JRNE JNE
LRE LE
LRNE LNE
JTE JE
JTNE JNE
In user mode, the LDF instruction does not change the E bit, and the JT instruction has no affect on the interrupt system.
3. 6. 2 Internal Interrupts
Tne internal interrupts are summarized in Figure 3-4. The interrupt number represents the bit num-ber for the corresponding bit in the Mask Register.
The lowest number has the highest priority. Each interrupt is discussed in detail below.
(0) Interrupt Name: Power failure and memor:y parity error interrupt.
Interrupt Location: '40
o
2 3 4 5 MEM
PROT
6 TIMER 7 8 CHNO DATA 9 CHNI DATA 10 DATA CHN2
\I DATA CHN3 12 13 14 15
Interrupt Mask: Does not affect this interrupt.
If the voltage level varies beyond a safe limit, a power failure interrupt is generated. Memory parity is checked whenever the memory is accessed -either for normal program execution or for the auto-matic data channel operation. Both power failure and memory parity error are considered catastrophic.
Restart may be from the beginning of the present job or from the last SAVE point in the job. The follow-ing instructions are used to determine cause: TSL = '23" 0 for Test Memory Parity Failure, and SFL
=
'23,,0 for Reset Memory Parity Failure.
(1) Interrupt Name: Data Exec Interrupt Location: '41 Internal Mask: '40000
The Data Exec interrupt is set for any gathering of data in the monitor mode of a word with the left Exec
(POWER FAILURE)+(ANY READ)(MEMORY AIIRITY FAILURE) (DATA FETCHi(RIGHT EXEC)(USER MODE)HLEFT EXEC)
(MONITOR MODEl]
UNSTRUCTION FETCHi(PRIVILEGED INST)(USER MODE) +ULLEGAL INST)HLDCC+STCC)(NO ADCP~
(INSTRUCTION FETCH)(RIGHT EXEC)(USER MODE) EXPONENT OVERFLOW OR UNDERFLOW
(USER MODE)(ANY WRITE)(RIGHT EXEC)(MEMORY PROTECT ENABLE)HMEMORY ACCESS)(ADDRESS OUT OF MEMORY)
TIMER DECREMENTED TO ZERO CONsa.E INTERRUPT BUTTON DEPRESSED
DATA CHANNEL INTERRUPTS
(SEE CHAPTER 5 FOR DEFINITION OF INTERRUPT CONDITIONS)
bit set, or in user mode of a word with the right Exec bit set.
Exceptions: TEX, LDCC, LDCD, LDOB.
The cycle of instruction gathering lasts until the ef-fective address has been fully calculated, including indirect addressing and indexing. Instructions that have operands in a memory location given by the ef-fective address, have a data gathering cycle that fol-lows the instruction gathering cycle. Immediate instructions do not have a data gathering cycle.
(2) Interrupt Name: Illegal Instruction Interrupt Location: '42
Internal Mask: '20000
In general, any instruction that is undefined or would result in stopping machine operation will cause this interrupt. Immediately after gathering instruction the interrupt is generated and the instruction is not executed. The following specific instructions cause this interrupt:
1. Undefined OP codes
2. STCC or LDCC when no Automatic Data Channel Processor is present
3. Privileged instructions in user mode
(3) Interrupt Name: Instruction Exec Interrupt Location: '43
Internal Mask: ' 10000
This interrupt is generated following instruction gathering in user,. mode if the right Exec bit at the location of the obtained instruction is high. The instruction is not executed.
(4) Interrupt Name: ExPonent Fault Interrupt Location: ' 44
Internal Mask: '04000
This interrupt is generated by a floating-point expo-nent exceeding the proper range as the result of some floating-point operation. The proper range for expo-nents is -128 :s Exp:s 127. Exponent overflow does not inhibit a floating-point operation.
(5) Interrupt Name: Memory Protect Interrupt Location: '45
Internal Mask: '02000
This interrupt results when an instruction tries to modify any half-word, full-word, or Exec bit in a protected area of memory. Specifically, this inter-rupt occurs on a store instruction, in user mode, if and only if the right Exec bit is set at the location and the memory protect mode has been enabled for that memory bank. The memory protect mode can be en-abled and disen-abled individually for up to four memory banks. The instructions pertaining to the memory protect mode are the following:
Test Set Reset
Bank 1 TSL ='40,,0 SFL = '40, ,0 SFL='41,,0 Bank 2 TSL = '42,,0 SFL ='42,,0 SFL='43,,0 Bank 3 TSL = '44, ,0 SFL = '44,,0 SFL ='45,,0 Bank 4 TSL ='46,,0 SFL = '46, ,0 SFL ='47, ,0 The SFL instructions set the B flag if the specified mode control was set prior to the SFL action. The TSL instructions set the Z flag if the specified mode control was set, and reset the Z flag if the control was reset.
This interrupt will also occur if memory is refer-enced by an illegal address (for example, an address out of memory). If an instruction attempts to access
memory with an illegal address, the memory access is bypassed, the instruction cycle is completed, and the interrupt is generated.
(6) Interrupt Name: Timer Interrupt Location: ' 46 Internal Mask: '01000
The interval timer is an optional feature on the 8400, and this interrupt cannot occur on those machines without a timer. This interrupt occurs when the timer is decremented to zero.
The basic element of the timer is the 16-bit Timer Register. The following instructions pertain to the timer:
LDT m
STT m
Options Flags:
Load the Timer Register with a half-word from memory Store the Timer Register into a half-word in memory.
*,
X, /, =none
SFL = '62,,0 Start the timer TSL = '62,,0 Test the timer SFL = '63,,0 Stop the timer
The B flag is set following the SFL instructions if the timer was operating prior to the SFL; the Z flag is set follOWing the TSL if the timer was operating.
Once the timer is operating, the Timer Register is decremented every millisecond. Decrementing con-tinues until the timer is stopped with the appropriate SFL instruction. Note that the timer runs while the machine is in a manual halt condition. After zero is
value in the Timer Register, and decrementing pro-ceeds from there.
(7) Interrupt Name: Console Interrupt Location: '47 Internal Mask: '00400
The console interrupt is generated when anyone of the four console interrupt buttons (CI1-CI4) is de-pressed. Each button is buffered with a flip-flop as shown in Figure 3-5. Pushing the button sets a cor-responding flip-flop, and generates the interrupt.
An indicator in the button lights when the flip-flop is set. The flip-flops can be tested and reset by pro-gram to determine which of the buttons caused the interrupt. When the flip-flop is reset, the indicator light goes out. The instructions related to the con-sole interrupt are listed below:
TSL = '25" 0 Test Console - Interrupt 1 SFL ='25,,0 Reset Console - Interrupt 1 TSL '='27,,0 Test Console - Interrupt 2 SFL ~'27"O Reset Console - Interrupt 2 TSL ='31,,0 Test Console - Interrupt 3
Figure Console Interrupt Buttons
SFL
=
'31,,0 Reset Console - Interrupt 3 TSL = '33, , 0 Test Console - Interrupt 4 SFL = '33, , 0 Reset Console - Interrupt 4 The TSL instructions set the Z flag if the specified flip-flop was set. The SFL instructions set the B flag if the specified flip-flop was set.The JT instruction that resets the bit in the interrupt register has no affect on the flur flip-flops associated with the console interrupts. Following a console in-terrupt, both the interrupt bit and the console flip-flop must be reset before another console interrupt can be generated.
(8) - (15) Interrupt Name: Channel Interrupt Interrupt Location: '50 - '57
Internal Mask: '00377 Each data channel has. one interrupt. Channel 0 corresponds to location '50, channell to '51, and so forth. When a device is connected to a data channel, interrupts can result from the channel itself, or from the connected device. When no device is connected to a channel, interrupts can result from those devices on the channel which have been properly enabled.