UNIVERSAL SERIAL BUS MODULE
10.2.1 USB Protocol
Figure 10-2 shows the various transaction types supported by the MC68HC05JB3 USB module. The transactions are portrayed as error free. The effect of errors in the data flow are discussed later.
Figure 10-2. Supported Transaction Types per Endpoint
Each USB transaction is comprised of a series of packets. The MC68HC05JB3 USB module supports the packet types shown in Figure 10-3. Token packets are generated by the USB host and decoded by the USB device. Data and Handshake packets are both decoded and generated by the USB device depending on the type of transaction.
SETUP
IN OUT
DATA0/1
DATA0 ACK DATA1
DATA1
OUT ACK
OUT DATA0 ACK
ACK
DATA0/1 ENDPOINT 0 TRANSACTIONS:
Control Write
Control Read
No-Data Control
ENDPOINTS 1 & 2 TRANSACTIONS:
Interrupt
Bulk Transmit
IN ACK
KEY:
Unrelated Bus Traffic Host Generated Device Generated ACK
SETUP
OUT IN
DATA0/1
DATA0 ACK DATA1
DATA1
IN ACK
IN DATA0 ACK
ACK ACK
SETUP DATA0 ACK IN DATA1 ACK
DATA0/1
IN ACK
F re e sc a le S e m ic o n d u c to r, I
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Figure 10-3. Supported USB Packet Types
The following sections will give some detail on each segment used to form a complete USB transaction.
10.2.1.1 Sync Pattern
The NRZI (See Section 10.4.4.1) bit pattern shown in Figure 10-4 is used as a synchronization pattern and is prefixed to each packet. This pattern is equivalent to a data pattern of seven 0’s followed by a 1 (0x80).
Figure 10-4. Sync Pattern
The start of a packet (SOP) is signaled by the originating port by driving the D+
and D– lines from the idle state (also referred to as the “J” state) to the opposite logic level (also referred to as the “K” state). This switch in levels represents the first bit of the Sync field. Figure 10-5 shows the data signaling and voltage levels for the start of packet and the sync pattern.
Token Packet:
IN
OUT SYNC PID PID ADDR ENDP CRC5 EOP SETUP
Data Packet:
DATA0 SYNC PID PID DATA CRC5 EOP
DATA1 0 - 8 bytes
Handshake Packet:
ACK
NAK SYNC PID PID EOP STALL
SYNC PATTERN
PID0 PID1 NRZI Data Idle
Encoding
F re e sc a le S e m ic o n d u c to r, I
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Figure 10-5. SOP, Sync Signaling and Voltage Levels
10.2.1.2 Packet Identifier Field
The Packet Identifier field is an eight bit number comprised of the four bit packet identification (PID) and its complement. The field follows the sync pattern and determines the direction and type of transaction on the bus. Table 10-1 shows the PID values for the supported packet types.
Table 10-1. Supported Packet Identifiers
10.2.1.3 Address Field (ADDR)
The Address field is a seven bit number that is used to select a particular USB device. This field is compared to the lower seven bits of the UADDR register to determine if a given transaction is targeting the MC68HC05JB3 USB device.
PID Value PID Type
%1001 IN Token
%0001 OUT Token
%1101 SETUP Token
%0011 DATA0 Packet
%1011 DATA1 Packet
%0010 ACK Handshake
%1010 NAK Handshake
%1110 STALL Handshake
END OF SYNC FIRST BIT OF PACKET
BUS IDLE SOP VOH (min)
VSE (max) VSE (min) VOL (min) VSS
F re e sc a le S e m ic o n d u c to r, I
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10.2.1.4 Endpoint Field (ENDP)
The Endpoint field is a four bit number that is used to select a particular endpoint within a USB device. For the MC68HC05JB3, this will be a binary number between zero and two inclusive. Any other value will cause the transaction to be ignored.
10.2.1.5 Cyclic Redundancy Check (CRC)
Cyclic Redundancy Checks are used to verify the address and data stream of a USB transaction. This field is five bits wide for token packets and sixteen bits wide for data packets. CRCs are generated in the transmitter and sent on the USB data lines after both the endpoint field and the data field. Figure 10-6 shows how the five bit CRC value is calculated from the data stream and verified for the address and endpoint fields of a token packet. Figure 10-7 shows how the sixteen bit CRC value is calculated and either transmitted or verified for the data packet of a given transaction.
Figure 10-6. CRC Block Diagram for Address and Endpoint Fields
0 0 1 0 1
0 1 1 0 0 0
5
5
5
5 next bit
Data Stream
Update every bit time Reset to ones at SOP
Equal?
Good CRC Bad CRC
5
Y N
Expected Residual:
Generator Polynomial:
MUX 1 0
F re e sc a le S e m ic o n d u c to r, I
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Figure 10-7. CRC Block Diagram for Data Packets
10.2.1.6 End Of Packet (EOP)
The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The single-ended 0 state is indicated by both D+ and D– being below 0.8 V. EOP will be signaled by driving D+ and D– to the single-ended 0 state for two bit times followed by driving the lines to the idle state for one bit time. The transition from the single-ended 0 to the idle state defines the end of the packet. The idle state is asserted for one bit time and then both the D+ and D– output drivers are placed in their high-impedance state. The bus termination resistors hold the bus in the idle state. Figure 10-8 shows the data signaling and voltage levels for an end of packet transaction.
MUX
0 16
16
16
16 0 1 next bit
Input / Output
Update every bit time Reset to ones at SOP
Equal?
Good CRC Bad CRC
16
Y N
Expected Residual:
Generator Polynomial:
Data Stream
Output Data Stream
CRC16 Transmitted MSB first after final data byte.
TRANSMIT
RECEIVE
0 0 0 0 0
1 0 0 0 0 0 0 0 1 0 1
0 0 0 0 0
1 0 0 0 0 0 0 1 1 0 1
F re e sc a le S e m ic o n d u c to r, I
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Figure 10-8. EOP Transaction Voltage Levels
The width of the SE0 in the EOP is about two bit times. The EOP width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines.
Figure 10-9. EOP Width Timing 10.2.2 Reset Signaling
A reset is signaled on the bus by the presence of an extended SE0 at the USB data pins of a device. The reset signaling is specified to be present for a minimum of 10 ms. An active device (powered and not in the suspend state) seeing a single-ended zero on its USB data inputs for more than 2.5
µ
s may treat that signal as a reset, but must have interpreted the signaling as a reset within 5.5µ
s. For aLow speed device, an SE0 condition between 4 and 8 low speed bit times represents a valid USB reset.
A USB sourced reset will hold the MC68HC05JB3 in reset for the duration of the reset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will be set after the internal reset is removed (See Section 10.5.2 for more detail).
After a reset is removed, the device will be in the attached, but not yet addressed or configured state (refer to Section 9.1 of the USB specification). The device must be able to accept a device address via a SET_ADDRESS command (refer to section 9.4 of the USB specification) no later than 10 ms after the reset is removed.
BUS DRIVEN TO LAST BIT OF
BUS IDLE EOP
STROBE PACKET
IDLE STATE BUS FLOATS
VOH (min)
VSE (max) VSE (min) VOL (min) VSS
EOP WIDTH tPeriod
DIFFERENTIAL DATA LINES
DATA CROSSOVER
LEVEL
F re e sc a le S e m ic o n d u c to r, I
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Reset can wake a device from the suspended mode. A device may take up to 10ms to wake up from the suspended state.
10.2.3 Suspend
The MC68HC05JB3 supports suspend mode for low power. Suspend mode should be entered when the USB data lines are in the idle state for more than 3.0 ms. Entry into Suspend mode is controlled by the SUSPND bit in the USB Interrupt Register. Any low speed bus activity should keep the device out of the suspend state. Low speed devices are kept awake by periodic low speed EOP signals from the host. This is referred to as Low speed keep alive (refer to Section 11.2.5.1 of the USB specification).
Firmware should monitor the EOPF flag and enter suspend mode by setting the SUSPND bit if an EOP is not detected for 3 ms.
Per the USB specification, the MC68HC05JB3 is required to draw less than 500