SuperBrain II Users Manual Introduction
The SuperB rain II contains two Z80 microprocessors. uP1 is the main processor which executes all user programs from the 64K RAM main memory, while transparently managing the CRT Display processes. All user I/O is also connected to uP1. This I/O includes the Serial Ports, Interface Controller, Keyboard Encoder, Time/Date Clock, and the External Bus. uP2 performs all floppy disk control functions from instructions contained in the 2K Bootloader EPROM. Part of this same EPROM contains the Cold Bootloader for uP1, and is executed when a System Reset is performed. The Floppy Disk Control section also contains a 1 K x 8 RAM buffer used for temporary storage of disk read/write data. This buffer can be accessed by either uP1 or uP2, therefore, a protocol exists to prevent microprocessor contention for this buffer.
The 64 kilobyte main memory consists of thirty-two 16K x 1 bit dynamic RAMS. These are divided in four banks (0-3) with each bank containing 16 kilobytes of storage. The RAS-CAS timing sequence necessary for memory access is created by the memory timing generator.
The CRT-VIDEO CONTROLLER circuitry is divided into three main areas: The CRT controller which generates all the timing signals for data display; the character generator circuitry which produces the character font; and the attribute generation circuitry which provides the special video capabilities of blinking, underlining, half-intensity, and reverse video in addition to normal video display.
The capability exists to install an alternate character set EPROM as an option. This would allow the CRT controller to access either character set during normal operation.
The CRT controller generates all the timing necessary to display 24 rows of characters with 80 characters per row. Thus the screen can display a total of 1,920 characters. These characters are stored in the CRT refresh buffer which is the upper 2,048 bytes (2K) of main memory.
Because the CRT buffer is not a separate buffer and the processor must also use the same bus to access memory, this bus must be timeshared between the two. This is accomplished by the CRT controller performing a direct memory access (DMA) cycle which is done at the last scan line of each character row. Each character row is divided into ten scan lines, therefore, during the last scan line time, the controller takes control of the processor bus by generating a bus request. After acquiring the bus, it reads 80 characters from the CRT buffer and loads them into the 80 x 8 shift register. This data is then recirculated in the buffer for the next nine scan lines to produce one row of video characters. Therefore, there are twenty-four DMA cycles performed per vertical frame.
There are also twenty-five interrupts generated - one for each row scan and one extra during vertical blanking. During the first twenty-four, the processor sets or resets the video blanking depending on whether that row is displayed or not. During the vertical blanking interrupt, the address registers in the CRT controller are initialized to the correct top-of-page address and the cursor register is also updated.
The Interface Controller is basically three 8 bit I/O ports (8255). Through this device, the processor can obtain status bits from other devices and react to the status by setting/resetting individual bits in the 8255.
The Keyboard Encoder scans the keyboard for a key depreSSion, determines its position, and generates the correct ASCII code for the key. The processor is flagged by the 'Data Ready' signal via the Interface Controller. The character is then input by the processor.
The Time/Date clock is accessed directly by uP1 through an I/O address. The clock has a battery power supply and will maintain the correct time and date when the external power is removed.
6831010 1-11
SuperBrain II Users Manual Introduction
The clock is also available as a real time clock for the user's access.
There are also two RS232C serial interface ports. The main port is capable of synchronous or asynchronous operation. The aux port is a simplified port used for asynchronous operation only.
The baud rates .are variable from 50 baud to 9600 baud. The mode of operation of the main port and the baud rate of both ports are set up by the operating system and can be changed by using the "CONFIGUR" program.
As previously mentioned, uP1 has the capability of communicating with the RAM and ROM in the FLOPPY DISK CONTROLLER. Because the amount of main memory used is the maximum that the processor addressing can support, different 16K banks of main memory must be switched off line when communicating with the disk RAM or EPROM. In these cases Bank 0 (0000H-3FFFH) is switched out when communicating with the EPROM, and Bank 2 (8000H-BFFFH) when communicating with the RAM.
The FLOPPY DISK CONTROLLER performs all disk related 1/0 functions upon command from the main processor. These commands are:
* Restore to track 0
* Read sector
* Write sector
*
Write sector with verify* Format
The parameters associated with drive, side, track, and sector numbers are loaded, a status word is set at a specified location in the disk RAM. When uP2 receives this status, it sets the 'disk busy' status bit and performs the indicated function. Upon completion, it resets the 'busy' bit thus allowing the main processor (uP1) to retrieve data and status from the RAM.
1-12 6831010
C)