1 Answer "yes" to the "Wait for target ’80960 RESET’?" question.
2 Set the target system reset polarity by answering the "Target ’system reset’
polarity?" question.
3 Connect the emulator probe’s SYS_RESET line to the target system.
With most target systems, in order to synchronize the emulator with the same clock edge as the processor, it is necessary for the emulator to wait until a target 80960 RESET pulse occurs before releasing the processor from the reset state.
The answer to the "Wait for target ’80960 RESET’?" question controls how the 80960 processor in the emulator leaves the reset state.
If the "Wait for target ’80960 RESET’?" question is answered "yes", the 80960 processor in the emulator must detect a high level at the target system 80960 socket
Chapter 4: Configuring the Emulator Configuring the Emulator Pod
the emulator status will be "Awaiting target reset". Once this high level is detected, the emulator will enter the "Awaiting target run" state and wait for a low level to be detected. As soon as a low level is detected the processor will start to run.
If the "Wait for target ’80960 RESET’?" question is answered "no", the emulator only needs to detect a low level at the target system 80960 socket before the processor in the emulator will be allowed to run. If the emulator does not detect a low level, the processor will not be allowed to run, and the status will be "Awaiting target run". Regardless of the configuration, any time that the level at the target system 80960 socket is high, the processor in the emulator will remain in the reset condition, and the status will be "Awaiting target run".
Basically, "Waiting for target ’80960 RESET’?" requires the target system to transition the RESET line at the 80960 socket from a high level to a low level before the emulator will allow the processor to run. Otherwise, only a low level is required.
Normally, the emulator should be configured to wait for target 80960 RESET.
Probably one of two conditions exist in the target system that will require this configuration:
• First, the 80960 processor maintains an internal clock reference that is one-half the frequency of the CLK2 input. The internal clock is synchronized to the CLK2 input on the falling edge of the reset signal. Normally, the target system has hardware ,other than the 80960, that is sensitive to the synchronization between the CLK2 input and reset.
• The second condition that may exist in the target system is that the hardware operation is different at the time the processor comes out of reset than it is after some initialization code is executed. When the 80960 processor is plugged in the target system this is not a problem. However, when an emulator is plugged into the target system , the processor in the emulator can be reset from the target system OR the emulator hardware. When the processor in the emulator is reset by the emulation hardware the target system does not know that the processor is reset therefore startup problems can occur.
Chapter 4: Configuring the Emulator Configuring the Emulator Pod
target socket will be generated. When the break or run command is issued, SYS_RESET will be released, a low level at the target 80960 socket will be detected and the emulator and target system will maintain the correct synchronization.
If neither of the mentioned hardware conditions exist, then the emulator can be configured to NOT wait for the target 80960 RESET. In this case the SYS_RESET lead is normally not needed.
The "Target ’system reset’ polarity" controls the polarity of the SYS_RESET lead that comes from the two pin connector J2, on the emulator probe board. This lead can be connected to the target system so that the target system knows when the emulator reset command has been executed. When the reset command is executed, SYS_RESET is asserted. When the break, run, or init_processor command is executed, the SYS_RESET line is released.
This lead is provided so that the emulator can be used to reset all of the hardware in a target system. This may be necessary for some target systems whenever the 80960 processor is reset. The reset signal on the 80960 probe cannot be used to perform this function because it is not bi-directional and is only received by the emulator.
The SYS_RESET lead uses an open collector driver and will require a pull-up in the target system. The probe does not provide a pull-up resistor because the SYS_RESET lead is often connected to an RC network in the target system. The output driver device is a 74F38.
If the target system’s reset line is an active high, answer "high" to the "Target
’system reset’ polarity?" question. The pulse output on the SYS_RESET line will be an active high.
If the target system’s reset line is an active low, answer "low" to the "Target
’system reset’ polarity?" question. The pulse output on the SYS_RESET line will be an active low.
Target system power should be OFF when connecting the SYS_RESET line to the target system reset.
Chapter 4: Configuring the Emulator Configuring the Emulator Pod