Write transactions to the
STATUSregister are not used to store data but to change selected active bits to be inactive (=0). To change a bit to be inactive, the data value written for that bit (=1) with all other bits not being changed inactive (=0). Whenever DPE, SSE, RMA, RTA, STA or DPR is active in
STATUS, itwill cause the
PCIERRSTATbit in the
ERRORregister to be set and an interrupt to be generated unless
FAILDISor
POWRDNis active, or
INTENis inactive. The
STATUSregister is cleared when
PCIRST#is asserted. The
STATUSregister may be read or written at any time in Configuration space.
STATUS RIW
15 DPE 07 TFBTBC
14 SSE 06 UDF
13 RMA 05 66MHZ
12 RIA 04 CAP_LIST
11 STA 03 RSVD
10 DSTI 02 RSVD
09 DSTO 01 RSVD
08 DPR 00 RSVD
Bit Name Definition
15 (0) (r/w) DPE Detected Parity Error. Set active (=1) when an even-parity error is detected by a target during an Address phase or a Write Data phase (except for Special Cycles) and by the transaction master during a Read Data phase. DPE is set inactive during and after assertion of PCIRST# or by a write to the STATUS register with bit 15 set (=1). When the AIC-7890A/91 sets its DPE bit active with PERRESPEN and INTEN active and FAILDIS inactive, it will cause an interrupt to be generated to the host to handle the exception condition.
PERR# will also be asserted. Parity is monitored by the AIC-7890A/91 during PCI Write transactions (when the AIC-7890A/91 is a target) and PCI Read transactions (when t.~e AIC-7890A/91 is a master.)
14 (0) (r/w) SSE Signal System Error. Set active (=1) whenever an agent asserts SERR#. SSE is set inactive during and after assertion ofPCIRST# or by a write to the STATUS register with bit 14 set (=1). The AIC-7890A/91 sets its SSE bit active only when PERRESPEN and SERRESPEN are active for detected address parity errors. When SSE is active and FAILDIS is inactive and INTEN is active, it will cause an interrupt to be generated to the host to
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511683-00, Rev. B 8/17/98
Bit Name Definition
13 (0) (r/w) RMA Received Master Abort. Set active (=1) when an AIC-7890A/91 bus master generated transaction is terminated by the AIC-7890A/91 for no response from the intended target by the sixth (for SAC) or seventh (for DAC) PCLK after the AIC-7890A/91 asserted FRAME#. The AIC-7890A/91 will release the bus on the next PCLK and will not retry the transaction.
Software/fIrmware intervention is required for the AIC-7890A/91 to continue further master transactions.
RMA is set inactive during and after assertion of PCIRST# or by a write to the STATUS register with bit 13 set (=1). The AIC-7890A/91 will also set RMA active should the addressed target deassert DEVSEL# while the AIC-7890A/91 is asserting FRAME#, a PCI protocol violation.
Note: If R.\'1A is cleared with the aborted master transaction still waiting to complete, the
AIC-7890A/91 will retry the transaction To prevent this action, if desired, clear HDMAEN data channel, and CCSGEN and CCSBCEN of command channel before clearing RMA.The interrupt will remain active till cleared with CLRPARERR.
12 (0) (r/w) RTA Received Target Abort. Set active (=1) when the target of an AIC-7890A/91 bus generated transaction is terminated by the target, with a target -abort indication.
RTA is set inactive during and after assertion of PCIRST# or by a write to the STATUS register with bit 12 set (=1). When a target-abort indication is received, the AIC-7890A/91 will not retry the transaction, and software/fIrmware intervention is required for the AIC-7890A/91 to continue further master transactions.
Note: IfRTA is cleared with the AIC-7890A/91 still waiting to complete the aborted master transaction, the AIC-7890A/91 will retry the transaction. To prevent this action, if desired, clear HDMAEN before clearing RTA for data channel errors and/or clear bits CCSGEN or CCSCBEN for command channel errors. The interrupt will remain active till cleared with CLRPARERR.
11 (0) (r/w) STA Signal Target Abort. Set active (=1) by the target of a PCI bus transaction unable to respond due to a fatal error condition. STA is cleared during and after assertion of PCIRST# or by a write to the STATUS register with bit 11 set (= 1). The AIC-7890A/91 will indicate target -abort for:
511683-00, Rev. B 8/17/98 4-25
AIC-7890An891 Data Book
Bit Name Definition
• Incorrect data width
- must be 8 bits for Device space - must be 8 bits for ROM space write
• Value stored in base address registers for BASEADRI and EXROMBADR are the same and EXROMEN is active.
• SEEMS is active and an access is made to external SCB RAM space address.
• Accesses with POWRDN active except for Host only registers and Configuration registers.
• Address parity error detected (SSE = 1)with correct address compare (SERR# asserted) for current access.
• Accessing AIC-7890A/91's Device space registers while Sequencer is not paused.
Note: No valid data (no CBE is asserted for a Data phase) is not an error condition.
10-09 (I) (r) DST[1:0] Device Select Timing[1:0]. Value indicates the longest response time of a PCI device for assertion of DEVSEL#
for any bus transaction with valid values of Oh for fast (1 PCLK), Ih for medium (2 PCLKs), 2h for slow (3 PCLKs) with value 3h reserved. Respond time for the
AIC-7890A/91 is medium. DST[I:0] are fixed value read only bits.
08 (0) (r/w) DPR Data Parity Reported. When active (=1). indicates the master of a transaction, with its PERRESPEN bit active, has detected PERR# asserted or asserted PERR#. DPR is set inactive during and after assertion of PCIRST# or by a write to the STATUS register with bit 8 set (=1).
07 (I) (r) TFBTBC Target Fast Back-to-back Capable. When active (=1), indicates that the target is capable of accepting Fast PCI Back-to-back transactions even when t.l-J.e transactions are not to the same target. The AIC-7890A/91 as a target supports Fast Back-to-back transactions. TFBTBC is a read only bit.
06 (0) (r) UDF Always reads O.
05 (0) (r) 66MHZ Always reads O.
04 (1) (r) CAP_LIS When set to 1, indicates that the AIC-7890A/91 is T capable of Power Management functions.
03-00 (0) (r) RSVD Always reads O.