SHIFT CLASS INSTRUCTIONS

5.3 SHIFT CLASS INSTRUCTIONS

These instructions are used to shift the data bit by bit either in the A register or the Q register singly or together. The data can be shifted either left or right bit by bit. For these instructions the format appears below:

15 12 11 8 7 6 5 4 3 ⁰

I

0 0 0 0 1111

I I I I I ^C- I

1

\

V ^/

Shift Count

F=O F1=F

l=shlltleft __________________________ ^~ O=shift right

1 =shift A ---' l=shift Q - - - - -_ _ _ _ _ _ _ _ ^--1

Notice the shift count is five bits allowing a shift either way a maximum of 31 positions.

The upper bit of the shift count will a p pea r in the hex code as part of the second digit.

For example, a OF51 is an ARS

%,

instruction, not ARS 1.

(l

Left shifts are end around: the high order hit of the register is shifted around and into the low order bit of that register for single register shifts. For a double register shift, (Long Shift), the Q register is considered the most significant register and the A register the least significant register and on left shift s the high order bit of Q is shifted around into the low order bit of A. High bit of A is shifted left into the low order hit of Q.

Right shifts are end off with sign extension. Bits shifted off the right end are lost, and the sign bit of the register is extended from the left., For long right shifts, the low bit (Bit 0) of Q is shifted into the high bit (Bit 15) of A arid the sign (Bit 15) of Q is extended

from the left. .

The mnemonics for the instructions in this class are:

ARS QRS LRS ALS QLS LLS

A Right· Shift Q Right Shift

Long Right Shift (QA) A Left Shift

Q Left Shift

Long Left Shift (QA)

5-32

u

o

(--'1

I ,

l .•.... ,'

Example:

Location Opcode

I

ALS

Address 8 I

Comments

If the A register contained F302, execution of this instruction would shift the A register left 8 bits leaving 02F3. The high order bits of A moved end around into the low order bits of A.

I I

I I

LRS 8

If Q=8000 and A=AOFO, execution of this instruction extends the sign of Q to the right and the lower 8 bits of A would shift end off and be lost. Result is FF80 I in Q, and OOAO

?-n

A.

I I

5.3

LLS 40

I I

Illegal

J I

Maximum number of shifts allowed is 31,

Legal QRS 0

I I

I J

5.3. 1 Timing for Shift Class Instructions

The time for shift class instruction execution is:

For long shifts (QA together) 1. 1 + • 2 x shift count

Is effectively a no opera-tion

For single register shifts (Q or A) 1. 1 + • 1 x shift count

5-33

*

INTERREGISTER *

.

⁰¹

c:...:>

*

^{LX *}

.

I-'

* F=O Fl=8 PR AQM AQM *

* (P)=* * * * **** ** *** *** *

* ADDER CONTROLS ~

I +++ "+

^~~ DESTINATION REGISTERS *

*

^{'" ~~RIGIN REGISTERS *}

*

^'"

^~OPERAND

^TWO

*

*

+~"'OPERAND ONE *

* *

*

^TRANSFER TRANSFER COMPLIMENT SUM

*

*

^{40 CLR Or--A,Q,M 80 SET -O~A,Q,M 30 AAQ} (A)+(Q)~A, Q, M *

01

• *

^{AO TRA (A)~A,Q,M 60 TCA (A)} NOT r--A , Q, M 28 AAM (A)+(M) ~A, Q, M

*

~ ~

* 90 TRQ (Q)~A,Q,M 50 TCQ (Q)NOT ~A, Q, M 38 AAB B+(A) ~A, Q, M

*

*

^{88 TRM} (M)r--A, Q, M 48 TCM (M)NdT~A,Q,M

*

*

^{98 TRB B~A,Q,M 58 TCB B NOT~A,Q,M}

*

* *

*

EXCLUSIVE OR LOGICAL AND COMPLIMENT LOGICAL AND

*

*

^{70 EAQ} (A).3o'-(Q) ~A, Q, M BO LAQ (A)/\(Q)~A,Q,M FO CAQ «A) /\ (Q»NOT~A, Q, M

*

^{68 EAM} (A)~(M)~A, Q, M A8 LAM (A)/\(M)~A,Q,M E8 CAM «A)/\ (M»NOT~A, Q, M

*

^{78 EAB} B-'7"(A) ~A, Q, M B8 LAB B/\ (A)r*'A, Q, M F8 CAB (B/\ (A) )NOT~A, Q, M

*

* *

*

B=INCLUSIVE OR OF (M}AND(Q).

*

/l

^(~)

^("1

_,

5.4

l'''--

5.4 INTERREGISTER CLASS INSTRUCTIONS

./

This class of instructions performs arithmetic or logical manipulation with the contents of A, Q or M or any combination of the three. The format for this class of instruction is:

5.4

Either A, Q or M,or any combination of these can be specified as the destination reg-isters. These are listed in any order and s epa rat e d by commas in the address field.

Since M is the interrupt mask register, the interregister instruction with M as a desti-nation register must itself be protected if the protect switch on the programmer's panel is on. Otherwise, a protect fault will occur.

1 1 Complement Logical Product

Refer back to Section 5.1.2. 3 of this chapter for the truth tab I e s of the logical product and the exclusive OR. All the possible combinations of different instructions in this class using these two operands number 22. The mnemonics assigned with the instructions in

Transfer Complement A Transfer Complement M

Transfer Complement Logical Product A, M Transfer Complement Logical Product A, Q Transfer Complement Logical Product A, Q V M

5-36

-

^,

/

\ ... -.. ~,

C-")

Only affects overflow indicator--adds A and Q, puts result nowhere

The following is an example of how a subroutine can pick up parameters from the calling r 0 uti n e. How does the subroutine pick up the parameters? Does it pick up the actual argument or the address of the argument?

Calling Program:

Addresses of parameters fall directly beneath the call to the subroutine.

5-37

5.4

Subroutine: ^('

"

SUB 0 0 ^'---'

STA* SAVEA+l

STQ* SAVEQ+l

LDA- $FF

STA* SAVEI+l

LDA* SUB

EOR =N$8000

STA* SUB

LDA* (SUB)

STA* SUBAGI \'::,

RAO* SUB

LDA* (SUB)

STA* SUBAG2 '':-'J

RAO* SUB

LDA* (SUB)

(-"

STA* SUBAG3 ~

'LDA* SUB

INA I

AND =N$7FFF.

STA* SUB

SAVEl LDA

t

=NO

STA- $FF

SAVEQ LDQ =NO

SAVE A LDA =NO

JMP* (SUB)

SUBAGI BSS SUBAGl(l)

SUBAG2 BSS SUBAG2(1)

SUBAG3 BSS SUBAG3(1)

f ^{( '}

5-38

5.4

~ .~

U

^Problem:

How many numbers does the following r ⁰ uti n e sort? In what order? From what core locations?

SORT CLR A

STA- $FF

ENQ 1

BEGIN LDA+ $500, Q

SUB+ $500, I

SAP CHECK-*-l

LDA+ $500, Q

STA* TEMP+l

LDA+ $500,1

STA+ $500, Q

TEMP LDA =NO

STA+ $500,1

0

^{CHECK INQ 1}

TRQ A

EOR =N$lO

SAZ 1

JMP* BEGIN

LDA- $FF

INA 1

STA- $FF

EOR =N$F

SAZ EXIT-*-l

ENQ 1

ADQ- $FF

JMP* BEGIN

EXIT SLS

,..-,~

I

_{\ . ___ .i} ^I

5-39

.

C1 _~

*

REGISTER REFERENCE *

*

^{F70 Fl DELTA}

^*

*

^(P)=

* * * * * * * *

* * * * * * * *

*

* ,....r--~~~~r--~~~r--r-- r--~~ •• t+ ^{"~~ ~ ~r+~~r--}

^*

* t

ARITHMETIC

t

^INTERRUPT

t

^{PROTECT ~ I/O}

_*

* t t • ^{+ *}

* A ENA _ +-DELTA A 4 EIN* ENABLE 7 CPB CLEAR 2 INP I/O

r-A _*

*

^C ENQ ' +-DELTA Q 5 lIN INHIBIT 6 SPB SET 3 OUT (A)~I/O *

*

^{9 INA} +-DELTA+(A) ~A E EXI*EXIT 0 SLS SELECTIVE STOP

*

*

^{D INQ} +-DE LT A +(Q)r-"Q B NOP *

I ^*

*ONE INSTRUCTION DELAY

0 *

*

*

/ )

('

"

^{( - ,}

! \

5.5

"r ...•

G

5.5 REGISTER REFERENCE CLASS INSTRUCTIONS

o

,f)

\.. .. /

All the instructions in the class are one-word. The F field is always a zero and the Fl field will signify the particular instruction within this class. The format for the Register Reference Class of instructions is:

Fl Instruction

+

Code

---.J

The instructions within this class are:

Fl Clear Program Protect INTERREGISTER

Exit Interrupt State SHIFTS

5.5.1

Where applicable, these instructions should be used in place of storage reference class with con s tan t mode as these take only one word and 1. 1 microseconds to execute.

The value in the address field is p I ace d into D. by the assembler. The ENA 22 machine instruction equivalent is OA16.

5. 5. 2 Instructions SPB and CPB

These. instructions are used to either set or clear the protect bit (Bit 17) in mem-ory. For these instructions f:j, is not used. The address of the core lo cat ion which will have its protect bit either set or cleared must be in the Q register. If the program protect switch on the programmer panel is on, then these instructions must be protected. Otherwise, a program protect fault (interrupt on line 0, pro-tectfault indicator on panel) will occur and these instructions become no operations.

Example: Clear the protect bits in core from 1000 to 2000.

This particular routine is further simplified with the use of interregister c las s instructions.

Problem: The CLRPB subroutine clears protect bits on what core area?

Calling Program

G

interrupt -s y s t em. If the program protect switch on the programmer's panel is on, these instructions must be protected. Othe rw is e, a protect violation will occur. The interrupt system is inhibited immediately upon execution of the IIN in s t r u c t ion. However, for the EIN instruction one free instruction is allowed before the interrupt system becomes enabled.

Example:

This subroutine will operate on any level without interference from any other level since the whole subroutine functions with the in t err up t system off. Control is returned to the main program -before the interrupt system is activated through use of the one free instruction following the EIN.

5-43

5.5.3

For example, if an internal interrupt occurred on line 0, P and the overflow indi- ,--....

l

cator of 1 the inte$rrupted progra l

m wlOdUld havbe been saved in word 0 of thle trap for

lo-ine 0 (ocation 100). Contro wou have een transferred to word 1 ( 0 cat ion

$101). If word 1 contained a jump tothe Internal Interrupt Processor, that routine would be executed. It would determine the cause of interrupt (program pro t e c t violation or parity error) by using the appropriate instructions (skips). Then the routine could exit back to the interrupted program. It would do that by:

EXI 00

The delta in the EXI instruction should be the lower 8 bits of the word 0 trap lo-cation for the appropriate line. In this case, the 00 means the trap for line 0, at address $100.

$104 •

...

jump to proc.

>

^{line 0}

a P

v

_."

$100 exit through here

The EXI instruction (Exit Interrupt State) is use d to exit from an interrupt sub-routine. It restores the overflow indicator to its previous state, resets P of the interrupted program, and enables the interrupt system.

5.5.4 Instructions INP and OUT

The INP and OUT instructions are used for all input and output operations on the 1700. They are used to input or output data to or from the A register. They out-put function codes to the peripheral equipment from the A register, and they input s tat us conditions of the equipment to the A register. The Q register is used to address the desired equipment. A brief introduction to I/O using these instructions is contained in Chapter 7.

5.5.5 Instructions SLS and Nap

The SLS or selective stop ins t r u c t ion is dependent upon the positioning of the selective stop switch on the programmer's panel. If the selective stop switch is up, then the program will stop on this instruction. If the selective stop switch is not up, then this instruction is the sam e as a Nap or No Operation Instruction, where the computer simply steps past this instruction without performing any op-eration. If the computer stops, program execution will continue by momentarily

setting the RUN-STEP switch on the programmer's panel to the RUN pos ition. ( '

" • • • 0

5-44

o

Example:

START

Problem:

LDA NOP NOP

SLS

=N$1000

5.5.5

Put in for future expansion

"

Program stops i~ stop switch is up

Continues when run switch is hit or if stop switch is not up.

The following is a conversion routine which converts a positive or negative hexa-decimal number in the A register to the ASCII codes for the hexa-decimal number. It consists of a CONVRT subroutine and a main program CONTST which was used to check it out.

Study the program carefully, see how the conversion is done and how the param-eters are passed.

This should be considered a final examination over the 1700 instructions and their use.

5-45

5.5.5

0001 NAM CONVRT

0002 POOOO 0001 BSS SAVEQ(}}.SAVEI(l).SAVEA(l) POOOI 0001

C~

0042 P003C 0171

5.5.5

r- -,

\,-~,

QOOI NAM CONTST

0002 ENT CONTST

0003 EXT CONVRT

0004 POOOO 0000 CONTST 0 0

0005 POOOI COOO LOA =N$37CO

POO02 37CO

0006 POO03 5400 X RTJ CONVRT

POO04 7FFF X

0007 POOOS 6800 STA WRITE+6

POO06 0007

0008 POO07 54F4 WRITE RTJ- ($F4)

0009

poooa

OC01 NUM $OCOI

0010 POO09 OOOF P AOC COMPL

0011 POOOA 0000 NUM 0

0012 POOOB 18FC NUM $18FC Writes an

0013 POOOC 0003 NUM 3

0014 POOOO 0000 ADC 0

00}5 POOOE 14EA JMP- ($EA)

P EXIT

00}7 18FF NUM $18FF

0018 EXIT EXIT

0018 POOl} 54F4

QQIB

PQ012 OAgO

0019 END CONTST ,,---"

I ... -~.

I OOFF CONTST OOOOP WRITE 0007PCOMPL OOOFP EXIT 0011P

CONVRT 0004X

5-48

...

\

L J

---.. _\

" _-.---../ )

"' ...

,,-5.6 5.6 EXERCISES

5.6.1 Exercises - Constant Mode of Addressing

1. What is in the A and Q registers when location NEXT is reached?

a)

LDA =N$1FOC

ALS 3

LDQ =N277

LRS 12

EOR =N$0106

NEXT

b) LDA =N$7FFF

LDA =N6

MUI =N6

NEXT

c) LDQ =AAB See Appendix E for

LDA =AXY ASCII conversions.

AND =ACD

LLS 16

AND =AWZ

NEXT

5.6.2 Exercises - Absolute Mode of Addressing

1. Write code to increase the contents of Index Register I by 1016.

2. If C017 is in core 10 cat io n 3F, and 4016 is in core location 4017, where would program control be given for:

a) JMP- ($3F)

b) JMP- $3F

c) JMP+ ($3F)

3. What is wrong with these:

a) LDA- 0

b) LDA+ $7F3-$700

c) LDA+ (TEST)

5-49

5.6.3

5.6. 3 Exercises - Relative Mode of Addressing

1. Will these instructions address b a c k war d or forward, and how many locations

2. What modes of address are these assembly language instructions?

a)

3. Why is relative addressing never used to address into the communications region?

5.6.4 Exercises - Indexing 1. What is wrong with these:

5.6.4

a) LDQ =N$-l

I LDA- ($23), Q

"-/

_NEXT

b) LDQ =N$24

LDA- ($22), Q

NEXT

c) LDQ =N$l

LDA $23,Q

NEXT

3. What is wrong with this program:

NAM

START LDA =N$10

STA-

r

LDA+ $2000

LOOP SUB+ $2000, I

LDQ-

r

ADQ =N-1

SQZ DONE-*-l

JMP* LOOP

DONE

C··

_{, /} ^'I

5.6.5 Shift and Skip Instructions

Dans le document PROGRAMMING TRAINING (Page 88-107)