Series 4000 AT-Compatible Bus Timing Diagrams

This appendix contains timing diagrams for the 8-MHz, AT-compatible bus processes in the Series 4000.

Table A-l contains reference information for the cycle times shown in the timing diagrams contained in this chapter. Find the reference number in a diagram and refer to the table for the correct cycle times.

8-1

Series 4000 AT -Compatible Bus Timing Diagrams

Table B-1. Series 4000 AT-Compatible Bus Cycle Times Time (Nanoseconds)

Number Characteristic Minimum Maximum

1 CLOCK High to BUS CLOCK High 0 15

-Series 4000 AT -Compatible Bus Timing Diagrams

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Time (Nanoseconds)

Number Characteristic Minimum Maximum

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8-3 Series 4000 AT -Compatible Bus Timing Diagrams

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Figure B-2. Bus 16-Bit Memory Write Cycle

Series 4000 AT -Compatible Bus Timing Diagrams 8-4

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Figure 8-3. Bus 16-Bit I/O Read Cycle

8-5 Series 4000 AT -Compatible Bus Timing Diagrams

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Figure 8-4. Bus 16-Bit I/O Write Cycle

Series 4000 AT -Compatible Bus Timing Diagrams 8-6

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8-7 Series 4000 AT -Compatible Bus Timing Diagrams

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Figure B-6. Bus 8-Bit Memory Write Cycle

Series 4000 AT -Compatible Bus Timing Diagrams B-8

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8-9 Series 4000 AT-Compatible Bus Timing Diagrams

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Series 4000 AT -Compatible Bus Timing Diagrams

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Figure B-9. Bus DMA Cycles

8-11 Series 4000 AT -Compatible Bus Timing Diagrams

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56 ----31 . . . - .

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Series 4000 AT -Compatible Bus Timing Diagrams

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Figure B-1 O. Bus Refresh Cycle

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Figure B-11. External Mastership

8-13 Series 4000 AT -Compatible Bus Timing Diagrams

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8MHz

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Series 4000 AT -Compatible Bus Timing Diagrams 8-14

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8-15 Series 4000 AT -Compatible Bus Timing Diagrams

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Series 4000 AT -Compatible Bus TimIng Diagrams 8-16

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8-17 Series 4000 AT -Compatible Bus Timing Diagrams

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Series 4000 AT-Compatible Bus Timing Diagrams

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