3
Register Display
RD [[\o’++’|-|\o’==’][dname][/]]. . . [[\o’++’|-|\o’==’][reg1[-reg2]][/]]. . . The RD command is used to display the target state, that is, the register state associated with the target program (refer to the GO command). The
instruction pointed to by the target PC is disassembled and displayed also.
Internally, a register mask specifies which registers are displayed when the RD command is executed. At reset time, this mask is set to display the MPU registers. This register mask can be changed with the RD command. The optional arguments allow you to enable or disable the display of any register or group of registers. This is useful for showing only the registers of interest, minimizing unnecessary data on the screen; and also in saving screen space, which is reduced particularly when coprocessor registers are displayed.
The arguments are as follows:
Observe the following notes when specifying any arguments in the command line:
3. This is the first address that is searched for "BOOT", etc. and may be set by you to point to the ROMboot routine, so the search is faster. The default address is the start of the 147Bug EPROMs.
4. This disables the ROMboot function, but does not change any options chosen under RB.
\o’++’ is a qualifier indicating that a device or register range is to be added.
- is a qualifier indicating that a device or register range is to be removed, except when used between two register names. In this case, it indicates a register range.
\o’==’ is a qualifier indicating that a device or register range is to be set.
/ is a required delimiter between device names and register ranges.
dname is a device name. This is used to quickly enable or disable all the registers of a device. The available device names are:
MPUMicroprocessor unit FPCFloating-point coprocessor MMUMemory management unit reg1 is the first register in a range of registers.
reg2 is the last register in a range of registers.
1. The qualifier is applied to the next register range only.
2. If no qualifier is specified, a \o’++’ qualifier is assumed.
3. All device names should appear before any register names.
4. The command line arguments are parsed from left to right, with each field being processed after parsing, thus, the sequence in which qualifiers and registers are organized has an impact on the resultant register mask.
5. When specifying a register range, reg1 and reg2 do not have to be of the same class.
6. The register mask used by RD is also used by all exception handler routines, including the trace and breakpoint exception handlers.
The MPU registers in ordering sequence are:
Total: 26 registers. Note that A7 represents the active stack pointer, which leaves 25 different registers.
The FPC registers in ordering sequence are:
The MMU registers in ordering sequence are:
NUMBER OF TYPE OF
REGISTERS REGISTERS MNEMONICS
10 System Registers (PC,SR,USP,MSP,ISP,VBR,SFC
,DFC,CACR, CAAR)
8 Data Registers (D0-D7)
8 Address Registers (A0-A7)
NUMBER OF TYPE OF
REGISTERS REGISTERS MNEMONICS
3 System Registers (FPCR,FPSR,FPIAR)
8 Data Registers (FP0-FP7)
Register Display
3
Example 1:
147-Bug>RD
PC =00004000 SR =2700=TR:OFF_S._7_... VBR =00000000 USP =00005830 MSP =00005C18 ISP*=00006000 SFC =0=F0 CACR=0=D:.... I:... CAAR=00000000 DFC =0=F0 D0 =00000000 D1 =00000000 D2 =00000000 D3 =00000000 D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000 A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000 A4 =00000000 A5 =00000000 A6 =00000000 A7 =00006000 00004000 4AFC ILLEGAL
147-Bug>
Notes:
An asterisk (*) following a stack pointer name indicates that it is the active stack pointer.
The status register includes a mnemonic portion to help in reading it:
NUMBER OF TYPE OF
REGISTERS REGISTERS MNEMONICS
5 Address Translation/Control (CRP,SRP,TC,TT0,TT1)
1 Status (MMUSR)
Trace Bits: 0 0 TR:OFF Trace off
0 1 TR:CHG Trace on change
of flow
1 0 TR:ALL Trace all states
1 1 TR:INV Invalid mode
S, M Bits: The bit name appears (S,M) if the respective bit is set, otherwise a "." indicates that it is cleared.
Interrupt Mask: A number from 0 to 7 indicates the current processor priority level.
The source and destination function code registers (SFC, DFC) include a two character mnemonic:
The Cache Control Register (CACR) shows mnemonics for two bits: enable and freeze. The bit name (E, F) appears if the respective bit is set, otherwise a
"." indicates that it is cleared.
Example 2: To display only the MPU registers 147-Bug>RD =MMU
CRP =00000001_00000000 SRP =00000001_00000000 TC =00000000 TT0 =00000000 TT1 =00000000
MMUSR=0000=..._0
00004000 4AFC ILLEGAL 147-Bug>
The MMUSR register above includes a mnemonic portion, the bits are:
Condition Codes: The bit name appears (X,N,Z,V,C) if the respective bit is set, otherwise a "." indicates that it it cleared.
FUNCTION CODE MNEMONIC DESCRIPTION
0 F0 Undefined
1 UD User Data
2 UP User Program
3 F3 Undefined
4 F4 Undefined
5 SD Supervisor Data
6 SP Supervisor Program
7 CS CPU Space
B Bus Error bit 15
L Limit Violation bit 14
S Supervisor Only bit 13
W Write Protected bit 11
Register Display
3
Example 3: To display only the FPC registers.
147-Bug>RD =FPC
FPCR =00000000 FPSR =00000000-(CC=.... ) FPIAR=00000000 FP0 =0_7FFF_FFFFFFFFFFFFFFFF= 0.FFFFFFFFFFFFFFFF_E-0FFF FP1 =0_7FFF_FFFFFFFFFFFFFFFF= 0.FFFFFFFFFFFFFFFF_E-0FFF FP2 =0_7FFF_FFFFFFFFFFFFFFFF= 0.FFFFFFFFFFFFFFFF_E-0FFF FP3 =0_7FFF_FFFFFFFFFFFFFFFF= 0.FFFFFFFFFFFFFFFF_E-0FFF FP4 =0_7FFF_FFFFFFFFFFFFFFFF= 0.FFFFFFFFFFFFFFFF_E-0FFF FP5 =0_7FFF_FFFFFFFFFFFFFFFF= 0.FFFFFFFFFFFFFFFF_E-0FFF FP6 =0_7FFF_FFFFFFFFFFFFFFFF= 0.FFFFFFFFFFFFFFFF_E-0FFF FP7 =0_7FFF_FFFFFFFFFFFFFFFF= 0.FFFFFFFFFFFFFFFF_E-0FFF 00004000 4AFC ILLEGAL
147-Bug>
The floating point data registers are always displayed in extended precision and in scientific notation format. The floating point status register display includes a mnemonic portion for the condition codes. The bit name appears (N, X, I, NAN) if the respective bit is set, otherwise a "." indicates that it is cleared.
Example 4: To remove D3 through D5 and A2, and add FPSR and FP0, starting with the previous display.
147-Bug>RD MPU/-FPC/-D3-D5/-A2/FP0/FPSR
PC =00004000 SR =2700=TR:OFF_S._7_... VBR =00000000 USP =00005830 MSP =00005C18 ISP*=00006000 SFC =0=F0 CACR=0=D:.... I:... CAAR=00000000 DFC =0=F0 D0 =00000000 D1 =00000000 D2 =00000000 D6 =00000000 D7 =00000000 A0 =00000000 A1 =00000000 A3 =00000000 A4 =00000000 A5 =00000000 A6 =00000000 A7 =00006000 FPSR =00000000-(CC=.... )
FP0 =0_7FFF_FFFFFFFFFFFFFFFF= 0.FFFFFFFFFFFFFFFF_E-0FFF 00004000 4AFC ILLEGAL
147-Bug>
Example 5: To set the display to D6 and A3 only.
I Invalid bit 10
M Modified bit 9
T Transparent Access bit 6
N Number of Levels (3 bits) bits 2-0
147-Bug>RD =D6/A3
D6 =00000000 A3 =00000000 00013000 4AFC ILLEGAL 147-Bug>
Note that the above sequence sets the display to D6 only and then adds register A3 to the display.
Example 6: To restore all the MPU registers.
147-Bug>RD +MPU
PC =00004000 SR =2700=TR:OFF_S._7_... VBR =00000000 USP =00005830 MSP =00005C18 ISP*=00006000 SFC =0=F0 CACR=0=D:.... I:... CAAR=00000000 DFC =0=F0 D0 =00000000 D1 =00000000 D2 =00000000 D3 =00000000 D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000 A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000 A4 =00000000 A5 =00000000 A6 =00000000 A7 =00006000 00004000 4AFC ILLEGAL
147-Bug>
Note that an equivalent command would have been RD PC-A7.
Remote
REMOTE
The REMOTE command duplicates the remote (modem operation) functions available from the "system" mode menu command, entry number 4. It is accessible from either the "bug" or "system" mode (refer to MENU command in Appendix A for details on remote operation). The modem type, baud rate, and concurrent flag, are saved in the BBRAM that is part of the MK48T02 (RTC) and, remain in effect through any normal reset. If the MVME147 and the modem do not share the same power supply then, the selections remain in effect through power up, otherwise no guarantees are made as to the state of the modem.
N ote
The Reset and Abort option sets the "dual console"(concurrent) mode to the default condition (disabled), until enabled again by the REMOTE command.