ARITHMETIC PROCESSES Adder
The 1004 processor performs addition and sub-traction through' the use of a one-character serial adder. Information is moved one character at a time from the operands to the adder 1 be ginning with the least significant locations. One digit from Operand 1 is added to one digit from Operand 2, and the result digit is stored before the next pair of digits is added. Any carry generated by adding a pair of digits is de layed so that it enters the adder with the next pair of digits handled. The result of the addition of each digit-pair is stored in the location from which the Operand 2 digit was obtained. Subtraction is performed by adding the complement of Operand 1 to Operand 2.
Add AI gebrai c
When the ADD ALG process is performed, an X-bit in the LSL of each operand is recognized as a negative sign indication. The presence of an X-bit in the LSL of either operand conditions the ma-chine to treat this operand as a negative value.
The sum carries the true algebraic sign.
When a ne gative value is added to a smaller posi-tive number, the original result will be the com-plement of the true answer. The machine auto-matically recomplements this answer to give a true value result. Automatic recomplementing of a negative answer is prevented if, on the same step as the add order is given, NO RC (no recomple-ment) is signaled.
The adder operates at microsecond speed. Since no special intermediate accumulator is needed, values of any size can be accumulated.
Figure 2-12 graphically illustrates how the single-digit adder obtains the sum of two 3-single-digit fields.
The handling of sign is not shown.
The UNIVAC 1004 processor permits many very powerful processes to be profitably used by' an installation. The ability to address operands of any length and the use of a single-digit adder com-bine to supply one of these unique strengths.
If a number of numeric fields of the- same sign must be grouped for printing and/or accumulating, the user can accumulate all fields into their re-spective sums in ONE program step.
ADDITION
E XAMP L E: (0 P 1) + (OP 2)---+-OP2
DIGIT 1 (LSD) PHASE
OPERAND 1 OPERAND 2
C10 Cll C12 C13 C4 C5 C6 C7
/ r--.
R9
1 6 4 R12 3 6 .
;, _' ... J"'- I ./ J. ,./
I I
~ t
r -CARRY-
SUM0:
W
4 + 5 + 0 9
0
=
0 <
DIGIT 2 PHASE
OPERAND 1 OPERAND 2
C10 Cll C12 C13 C4 C5 C6 C7
I'
-....,
r'IR9
1 6 4 R12
I3
:... '.19
"- I I ' - - J I
-
l /+ +
-CARRY ~ SUM0:
6 6 0 2
w
+ +
-0
-0 <
I I
••••••••••••.•••••••••••••••••••••••••.••••••••••••••.•••••••••••••••••• : • • .t •••••••••••••••••••••••..•.•••••••.••••••••.••.••••
DIGIT 3 PHASE
OPERAND 1
C10 Cll C12 C13
r ...,
R9
1 6 4
\. 1 ....:..--v
I
OPERAND 1
C10 Cll C12 C13
~ ~
0:
W
1 + 3 +
0 0 <
i I I I
I CAfRY
II
I I I I I --!..-. CARRY
J -
SUM1 - - 5
R12
STORAGE AT END OF ADDITION
OPERAND 2
C4 C5 C6 C7 ....,
...
I2 9
.<
..
_...1. L.I
I
OPERAND 2
C4 C5 C6 C7
For example, a card form is used that contains program-med multiplication routine used with this machine.
This order will have frequent use in many
Subtraction can be performed with this order exact-ly as with Subtract Algebraic except that the least
TRANSFER
Data is transferred from one storage location to another by means of logical commands called
T RAN S FER. A variety of changes can be made in the information during transfer, depending upon which optional transfer hubs are signaled.
Trans fers are effected serially, from the source location of the information, Operand 1, to the destination location, Operand 2. Movement can be from the least significant location of Operand 1 to the least significant location of Operand 2; then from the next location to the left of the LSL of Operand 1 to the location to the left of the LSL of Operand 2, and so forth, until the transfer is com-plete. This method of· transfer is referred to as ASCENDING TRANSFER, and is initiated when any of the Ascending Transfer hubs of the connec-tion panel is signaled.
For example, if an ascending transfer is ordered by signalling the TRF hub on a step that defines Operand 1 as R2/C2 - R2/CS, four locations, and Operand 2 as RIO/C2 - RIO/C6, five locations, the transfer proceeds as follows:
1. Before the transfer step starts, storage ap-pears as:
CI C2 C3 C4 C5 C6 IR2
J 0 H NOPI
CI C2 C3 C4 C5 C6 C7 IRIO
/). /). /). /). /).OP2
2. After one character is transferred, storage appears as:
CI C2 C3 C4 C5 C6 I R2
J 0 H NOPI
CI C2 C3 C4 C5 C6 C7 IRIO
/). /). /). /). NOP2
3. After the second character is transferred, storage appears as:
CI C2 C3 C4 C5 C6
l R2
J 0 H NOP2
CI C2 C3 C4 C5 C6 C7 I RIO
/). /). /). H NOP2
4. After the ascending transfer is complete storage appears as:
CI C2 C3 C4 C5 C6 tR2
J 0 H NOPI
CI C2 C3 C4 C5 C6 C7 IRIO
/). J 0 H NOP2
At the end of the ascending transfer, any unused storage locations in Operand 2, to the L EFT of the most significant location, are space filled.
If Operand 2 contains data before the transfer, that data is destroyed and replaced by the trans-ferred data, and any unused locations in Operand 2 will contain spaces.
A transfer starting with the most significant loca-tion is referred to as aDESCENDING TRANSFER~
If the example given previously is executed as a descending transfer, it results, when completed, in storage as:
CI C2 C3 C4 C5 C6
I R2
J 0 H NOPI
CI C2 C3 C4 C5 C6 C7 IRIO
J 0 H N /).OP2
In a descending transfer, unused locations in Operand 2, to the RIGHT of the data transferred, are filled with spaces.
As previously mentioned, there are seven differ-ent transfer options which may be executed singly descending order to eliminate preceding zeros, but can be used in ascending order to
Zero suppression begins when the serial trans-fer of data to Operand 2 reaches the storage descending zero-suppression; the MSL of Operand 2 is reached in ascending character does not stop zero suppression.
The fact that a comma cannot be inserted stor-age locations of Operand 2 are accessed serial-ly from the least significant location to the
the code for an asterisk is used as the re-maining characters of Operand 1 are duplicated serially in Operand 2 locations without zone bits. The data in Operand 1 locations is not altered.
5b. DeB (Delete Zero Balance)
The Delete Zero Balance transfer" option may be performed in the Descending mode only. It appropriate Address Emitter hubs through Ad-dress Combines to D0B-ST and END.
Operand 2 after transfer
C7 C8 C9 CIO Cll CI2 CI3 CI4 CI5 CIG
Thus, if a storage location contains the code selected locations within Operand 2.
COMPRESS FEATURE OP 1 locations through Compress without performing an insert or a superimpose operation; however, the descending insert transfer, START Compress would be signaled from the fourth location, and END active compress operation. Compress can be started and ended any number of times during a single transfer according to program requirements. If a single location is to be deleted, START and END would be signaled pre-viously stated programming rules. The exceptions to these rules are:
Transfer With Overlapping Operands
Operand 1 and Operand 2 may be de fined as
An example of partially overlapping operands might be:
Operand I
C4 C5 C6 C7 C8 C9 CIa Cll Cl2
l
RIOperand 2
Or, the overlap might be:
Operand 1
C9 cm Cll CI2 CI3 C14 CI5 CI6 IRI2
Operand
2
Usually, when operand-overlap is specified, one of the transfer options used is Clear (CLR) al-through this is not a requirement. The examples gi ven later show the result of NOT using the Clear option.
There are, however, two requirements that must be met to obtain a result that is meaningful when transfer is done with partially overlapping operands.
1. When the MSL of Operand 1 is to the left of the MSL of Operand 2, the transfer execut-ed must be in the ASCENDING Mode.
2. When the MSL of Operand 1 is right of the MSL of Operand 2, the transfers executed must be in the DESCENDING Mode.
For example, given the operands illustrated be-low:
Operand 1
C4 C5 C6 C7 C8 C9 cm Cll CI2 IRIO
~ 9 7 1 3 6 ~ ~ ~Operand
2
In accordance with Rule 1, an ascending transfer is performed. The TRF option is ordered but the CLR option is not ordered. After execution, the res uIt appe ars in storage as:
Operand 1
C4 C5 C6 C7 C8 C9 ClO Cll CI2 IRIO
~ 9 7 ~ 9 7 1 3 6Operand
2
If, however, an ascending trans fer with the Clear option is ordered, the res uIt appears in storage as:
Operand 1
C4 C5 C6 C7 C8 C9 ClO Cll CI2 IRIO
~ ~ ~ ~ 9 7 1 3 6Operand
2
If the rules stated above are not followed and a descending transfer is ordered, the error that" re-sults is illustrated in Figure 2-14. Each line shows storage as it appears after each character is moved, beginning with the l\1SL since this is a descending transfer. Note that the following ex-ample demonstrates an ERR 0 R in programming and is included for illustration purposes only.
It is obvious that this result is not one that usual business problems could use. The first rule in transferring overlapping operands was not followed since the MSL of Operand-1,R10/C4, is to the left of the MSL of Operand 2, R10/C7. When this con-dition exists, the transfer MUST BE ASCENDING.
At the Start:
I digit moved st(J'age appears 2 digits moved st(J'age appears 3 digits moved st(J'age appears 4 digits moved st(J'age appears 5 digits moved
st~age appears 6 digits moved
Operand I
C4 'C5 C6 C7 C8 C9 CIO
cn
CI2storage results in ____ .--I._~-+---Io_..I.--"'-...I._...Io..-~
Operand 2 Figure 2-74. Incorrect Transfer Operation
When the MSL of Operand 1 is right of the MSL of Operand 2, storage appe ars
as:-Operand 1
C9 ClO Cll CI2 CI3 CI4 CI5 CI6 fRI2
~ ~ 4 1 3 5 2 7Operand
2
As stated in Rule 2, a descending transfer, TRF
The rules of transfer with partially overlapping operands must be observed. If an ascending Be-cause of specific programming considerations, it may be desirable to delete the information contained in Operand 1 locations during the transfer. When the Clear transfer option is used, Operand 1 locations are cleared to spaces.
Operand 1 and Operand 2 may be partially or completely overlapped during a transfer oper-ation. If a Clear transfer is ordered with over-lapping operands, only those locations of Oper-and 1 which are not overlapped by OperOper-and 2 are cleared to spaces.
For example, data in R4/C3 - R4/C10 is to be transferred to R4/C7 - R4/C14. In this instance, the operands partially overlap, and the data in the Operand 1 locations that are not overlapped has no value after transfer is completed. For
I
R4this operation, the CLR-Ascending Trans fer hub is signaled.
Before this transfer is started, storage appears as: operation. by limiting the res ult to only meaningful, useful digits.
Multiplication is done by first completing two data positioning steps - a procedure that has a counter-part in most computing systems. Once the two values have been positioned for the process, the two steps that actually perform multiplication be-gin.
The explanation given here will be more meaning-ful for most readers if continuous reference is made to the step-by-step example given in Figure 2-15. Three areas of storage are defined for use in multiplication. For convenience in this explana-tion, these areas are referred to as A, B, and C.
Determining the number of storage locations need-ed for each area is done with these rules:
(R/24)
.121311
:,t.I~It.It.It.It.It.It.It.i,
9Jt.J4J2J3JS' :.h!NSERTED ' 15 TRF 1*1* 1*l7JoII131112Ialslt.io~2
RESULT, 'LTEST • ' can be developed, the less significant digits will be dropped off.)
Two data-positioning steps are used to load values into the storage areas selected by the programmer
Transfer (Ascending) the multiplicand to area C. Use the Insert option of the transfer order.
Transfer (Ascending), using the Insert option of the transfer order. In this step Operand 1 take place almost simultaneously. Of necess ity these are described here individually.
a) Combined areas A and B are shifted one ficant locations. Therefore, the six most signi-ficant locations of area B are used for Operand 2. See Figure 2-15, lines 4, 5, and 6.
The mos t significant location of Operand 2 is, of course, a digit that was originally a part of the multiplier, area A. Shifting in Step 3 moved this
digit to area B. As the multiplication process the operands, Arithmetic Overflow will occur each time this step is performed. The routine is de-signed to utilize this fact, so the programmer should ignore Arithmetic Overflow when multiply-ing.)
The multiplication process continues through re-petitive addition and shifting until a sentinel (110000) is detected in C7 as the result of a trans-fer step. See Figure 2-15, line 21. When the sen-tinel is detected, multiplication is complete and the program is directed to proceed to the nex t locations defined by the programmer through connection panel wiring. The number of storage before starting the subroutine.
Continued reference to the detailed example, Fig-ure 2-16, printed on the foldout at the end of this
The Rowand Column designations are arbitrarily chosen; there are no limitations on the storage loc ations that may be used in any particular pro-gram. The areas are:
AREA CONTENTS
The number of storage locations equals:
The number of digits to the left of the decimal
The number of storage locations equals:
The· number of digits in the dividend
The number of storage locations equals:
The number of digits in the divisor (regardless of digit pos ition in relation to 'the decimal point);
PLUS - three (3);
Process: Insert transfer, ascending.
Ope ra n d 1: Storage locations containing the value
Process: Insert transfer, ascending.
o
per and 1: Storage locations containing the valueTest for arithmetic overflow:
If NO, go to Step 4,
If YES, ten divisor digits have been tested and all found to be zero.
Division cannot· be done; this situa-tion usually indicates an error. Go to a subroutine that correctly handles this error condition.
Process: Transfer, descending.
Ope ra nd 1: Area C storage locations MSL-4 through LSL.
Ope ra n d 2: Area C storage locations MSL-3 through LSL.
Test the MSL of Operand 2 (that is MSL-3 of Area C) for a zero:
If NO, go to Step 5; start division.
If YES, go to Step 3.
Dividing
Three additional steps are required for the actual division operation.
STEP 5 (TRIAL SUBTRACTION)
P roces s: Subtract Absolute; No Recomplement.
Operand 1: Area C.
P roc e s s: Superimpose transfer, descending.
Ope rand 1: All of Area A except the MSL, plus determination made by the comparator:
INPUT EDIT
If MINUS, exit from division sub-routine.
If PLUS, go to Step 8.
The editing of card input is largely a matter of rearranging information into a form suitable for machine processing. Several of the more common considerations of input editing are the recognition of control holes and the recognition of negative indicators. Each of these considerations is us ual-ly approached in the same fashion; that iSJ through
wir-DIVISION I DATA IS NOW ASSEMBLE,D FOR DIVISION.SHIFT COUNbT IS-RECORDED ORIPRiOPER : ALIGNMENT OF THE QUOTIENT WHEN DIVISION IS C MPLETED. i :
I PERTINENT STORAGE LjOCATIDNS NOW CONTAIN: I I '
!L\!f:1IL\If:1IA/L\!L\If:1r*IL\!L\IL\llI0 12/7, !91L\1f:11 3 / 1IA
~
; I I
ing, referenced by Wire Number to the differ-eOnt types of cards with significant control punches, and to ~se these punches to route the program in
S
W
aa bb cc dd ee ff
NS 0 0 0 0 0 0 0 o 0 0 0 0 0 0 0 0 0
S 0 0 0 0 0
c o o 546 0 0 0 NS
IN
IN
IN
OUT
a b c d 0 0 0
2 3 4
0 0 0 0 0 0
547 548
o 0 0 0 0 0
b d a b c
0 0 0
o 0 0 0 0 0 o 0
551 552
o 0 0 0 0
d a b c
6 7 8 9 10 11 12 13 14 15 16 17 18 19. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 2-17. Selector Pick-Up Wiring.
o
Z III
41 42 43 44 45 46 47 48 49 50 51 52
U1 o
a NS 0
c 0 NS 0 a
2 3 •
0 0 0 SI
~ c 0 0 d 0 0 0 0 0 0
S16 0 0 c ~
0 0
2
0 0 0 S2 0 0 0
b c 0 0 0 0
0 5
8 9 10 11 12 13 14 15 16 17 18 19 20 21 21 23 24 25 26 27 28 29 30 31 32 33
0 0 0 0 0 0 0
S7 S8
0 0 0 0 0 0 0 0
d b c d b c
0 0 0 0 0 0
0 0 S22
0 0 0 0 0 0
d b d
0 0 0
0 0 0 0 0 0
U 25 26 27 28 29
8 9 10 11 12 13 U 15 16 17 18 19 20 21 22 23 U 25 26 27 28 29 30 31 32 33 3. 35 36 37 38 39 .0 454647 5051 5253 S. 55
Note that the non-select side of Selector Sa is
The preceding example specified the possibility of only a 1- or a 2-punch in column 1. If this numbers shown merely indicate the identification of the specific value punched in column 1 of the true, the automatic translation of input information as the card is read causes the X-bit to be inserted
Address Emitter R3 IN, Address Combine 22 2 Address Emitter C1l IN, Address Combine 22 in mind when inserting or superimposing charac-ters or bits based on punches in cards. wiring described above accomplishes the selector pick-up during the read operation. Thus, the
2 3 4 5 6 7 8 9 10 11 12 13 U 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
o 0 0 0
I 2 3 5
M oPt
I I I I I I I
P opo
I I I I I I I
b _S a a a a a a a
51 52
~ a d 0 b a d a
a c c a
NS 0 a 0 0 0 0 0 0
0 a 0 a o a o 0 0 0
516 517 518
c 0 0 0 0 0 0 0 0 0 0 0 0
a ~ c ~ b c d b c d
NS 0 0 0 0 0 0 a 0
a a a
8 10 11
co 0 0 a a a 0 a a a
I 3 5 2~ 23 24 25 26 27 28 29
R 0 a 0 a a a a 0 0 0
II Co a 0 0 0
S 0 0 0 0 a 0 0 0 0
531 537
Co 0 0 0 0 0 0 a a 0 a 0 a 0 a 0
a b c d c d b c d a b c d a
p NS 0 0 0 0 0 a a 0 a 0 a a 0 0
q S 0 0 0 0 0 0 0 a 0 a 0
5.6 551 552
C 0 0 0 0 0 0 0 0 0 0 0 0
a b c d a d a b c b
s NS 0 a 0 0 0 0 0 0 0
aa bb cc dd
If
2 3 4 5 6 7 8 9 10 11 12 13 U 15 16 17 18 19 20 21 22 23 U 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 4S 46 4748495051 525354 55
0 0 0 0 0 0 0 0 0 0
535 536 537
0 0 0 0 0 0 0 0 0 0
b c d a b c d a b c
0 0 0 0 0 0 0 0 0 0
R
0 0 0 0 0 0 0 0 0 0
550 551 552
0 0 0 0 0 0 0 0 0 0
b d a b c d a b c
0 0 0 0 0 0 0 0
0 0 0 0
d a 0 0 0 0 0 0
d a 0 0
0 0
538
0 0
b c 0 0 0 0
553
0 0
b
I!I!I!I!l
36 I 37 I 38 I 39 I 40
IIIIIIIII
ri a. o Z III
o
Z III
0 0 0 0 0 0
540
0 0 0 0 a b c d a
0 0 0 0 0
0 0
555
0 0
d
S/. 7/2 9/1 C o G R T
l8 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Figure 2-20. Negative Sign Control Wiring.
w x
aa bb cc dd
ff
fastest method of including the sign bit is to
Several important considerations in editing for printout include the alignment of information into proper order for printing, suppression of non-signi-ficant zeros, insertion of symbols and punctuation, and conversion of a machine minus code to an ap-propriate printer symbol.
Alignment of in formation may involve rearrange-ment of fields or possibly only the insertion of
accumulate totals of several adjacent card fields in one step, for instance), it is seldom desirable to print this data in consecutive printing positions.
In each of the se ins tances the solution of the the insert step described above.
WIRE
NO. FROM TO
Address Emitter R6 IN, Address Combine 55 2 Address Emitter CIO IN, Address Comb ine 55 3 OUT, Address Combine 55 Character Generator Space
This WIrIng is illustrated with solid lines in different technique is used. This method makes. use of the Space Generate - Start and End hubs. The
3 4 5 6 7 8
o 0 0 0 0 0 ADDRESS - -
-o 0 0 0 0 0 20 21 22 23 24 25
o 0 0 0 0 0 GRAM SELECT
o 0 0 0 0 0 5 6 7 8 9 10
0180 0190 0200
ON OFF ON OFF ON OFF
35 36 37 38 39 40
9 0 0 26
0 0 11
0 0 ci a::
41 42
0 0 0
ri. ~ 0 z ~ 0 z ': III W III W 43 44 45 46 47
0 0 0 0
554
0 0 0 0
9/1 a b c d a
0 0 0 0 0
..: 0 z .= 0 Z O/X IIY alS lSI .. 7/2 011
III W WI III
48 49 50 51 52 53 54 55 56 57
F ;gure 2-27. W;r;ng fo I nserf a Space.
0 0 0 P
CTOR
0 0 0 0 0 0 0 Q
555 557
0 0 0 0 0 0 0 0
b c d a ~ d
0 0 0 0 S
U
V
x
y
z aa
bb cc dd eeC~ARACTER GENERATOR
0 0 0 0 0 0 0 0 0 ff
C 0 G R T $
•
58 59 60 61 62 63 64 65 66 67 68 69 70
these hubs. For example, data in locations R3/Cl
Address Emitter R7 IN,Address Combine 41 2 Address Emitter C5 IN, Address Comb ine 41 8 Address Emitter C12 IN,Address Combine44 9 OUT, Address Combine 44 Space Generate - Start 10 Address Emitter R7 IN, Address Comb ine 45 11 Address Emitter C13 IN,Address Combine45 12 OUT,Address Combine 45 Space Generate - End important consideration of output editing. The 1 004 pro c e s s 0 r provides two zero-suppress trans fer ins tructions that ,replace non-significant zeros with either spaces or asterisks at the op-tion of the programmer. The rules governing the operation of these processes are detailea in the section of this ch apter called "Transfer."
Removing non-significant zeros from totals is pro-bably the most frequent use of zero suppression in out-put, most applications require the elimination of of zeros preceding the mos t significant digit of a suppress zeros preceding the first significant digit of each of the totals. Since these totals are already located in the appropriate locations in print storage, the step to perform the zero-sup-pression specifies the same locations for Operand 1 and Operand 2.
0180 0190 0200 ON OFF ON OFF ON OFF
35 36 37 38 39 40
o a a
0 0
CTOR
0 0 0
o 3 O~ 0 0
H
<~---~---~----o 0 0 0 0 0 4 0 0 0 0 0 0 0 0
BIT ABSENT EMITTER S54 S55 557
o 0 0 0 0 0 0 0 0
a b c d a b c d a
0 0 0 0 0 0 0 0 0
0 0
b
CHARACTER GENERATOR 90
0 0 0 0 0 0 0 0
8/4 7/2 flIt C o G R T $ .
0
0 0 0 0
d
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Figure 2-23. Space Generate Wiring.
P
Q
s
u
vx
y
z
cc dd
ff
BEFORE ZERO·SUPP
-'-6 . -7 R 8
"""-- 9 _
AFTER
-C
2 3 4 5 6 7 8 9 10 11 12
--... /1' I
: - - : - _I. I ! I I I
TOTAL 1--~ TOTAL 2 t i
" , - -
---,
-~-
~o.
4 1 0 0 0 2 7 051
- _--1
Figure 2·24. Totals in Storage Before and After Zero-Suppression.
Step wiring is as follows:
P roces s: Zero-Suppress Space - Descending
a
per and 1; MSL R8/C3 LSL R8/C12 Operand 2: MSL R8/C3LSL R8/C12
aa bb cc dd
~~~~~~~~~~ __ ~~~~~~~~~~~ee ff
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 2-25. Zero-Suppress Wiring.
Additional wiring necessary to create the desired output is as follows (Figure 2-25):
FROM TO
Address Emitter RB IN, Address Combine 41 Address Emitter C3 IN, Address Combine 41 OUT, Address Combine 41 Zero-Suppress Start Address Emitter RB IN, Address Combine 42 Address Emitter C6 IN, Address Combine 42 OUT, Address Combine 42 Zero-Suppress End Address Emitter RB IN, Address Combine 43 Address Emitter C 7 IN, Address Combine 43 OUT, Address Combine 43 Zero-Suppress Start Address Emitter RB IN, Address Combine 44 Address Emitter C12 IN, Address Comb ine 44 OUT, Address Combine 44 Zero-Suppress End
Note that this com bination of wiring removes zeros
BE FOR E the mos t significant digit in each zero-suppress field, but leaves any zeros unaltered in the body of a field as in locations R8/C6 and R8/Cll in the example in Figure 2-24.
The replacing of zeros with asterisks is most fre-quently used in check-writing applications, where the asterisks serve the function of a built-in check-protector. The Zero-suppress Start and End hubs are wired from the OUT hubs of Address Combines as illustrated in the preceding example. The only difference would be the use of Zero-Suppress
The replacing of zeros with asterisks is most fre-quently used in check-writing applications, where the asterisks serve the function of a built-in check-protector. The Zero-suppress Start and End hubs are wired from the OUT hubs of Address Combines as illustrated in the preceding example. The only difference would be the use of Zero-Suppress