BIT PRESETTABLE REPEATABLE COUNTER, DOUBLE, USED IN AIP12 16 WORD 1 BIT MEMORV WITH COMMON CLEAR

css CSS CAT

DUAL 12 BIT PRESETTABLE REPEATABLE COUNTER, DOUBLE, USED IN AIP12 16 WORD 1 BIT MEMORV WITH COMMON CLEAR

CAT

11 15 12

CAT

12 15

ww Ww Ww

ww

00 SNT

DCB SNT ELlA FLIP:'FLOPS

M20~0

~12001 ::212l02 M2 12li2J 3 M202 H203 M21i'J4 H205 M21i'J6 M211l7 M208 H209 M21Z M2100 M21li'Jl M2il M212 M213 M214 M2i5 M216 M217 M2i8 M219 M220 M221 M222 M223 M224 M224"'JA M225 M225"'JA M226 M227 M228 M229 M230 M231 M232 M233 M234 M235

nAS CAT SSCAL SSCAL

CAT

CAT CAT CAT

css

CSS CAT 12

CAT 15 15

e

12 15 15 8 12 12 15 11 11 11 11 15 15 15 15

CAT 12 CAT 8 11 14

Re^R RF eER CER

DeB

JTN.

JTN CL.

DO L.H RI

CL.

JO JO JO Jo

STATUS MO/VR 5 1/72 '5 5/73 5 5 5/73 5 1/72 5 5/73 5 5 5 11/71 5

4 5 1 1 5 5 5 5 5 5 5 1 1

5/73 3 / 74 2/74 2/14

3 9174 2 6174 5 5 5 5 5 5 5 5 5 5 5 5 5 5 1 5 1 5 5 5 5 5 5 5 5 5 5

7172 5/73 7/72 5/73 5/73 5/13

5/13 5/73

OESCRIPTION

7 3~INPUTANO GATES, 74H, Kl10

NON~INVERTfNG M147

8 EN X 6 OUT MIXER. 74^H53, 74H62, KI10, DOU~LE

16~atT REED REL.AY REGISTER, 100V OR 0,5A, l~ WATTS, QUAD

NON~INVERTING Ml?l M162 WITH FAST

Ie's, H

4 ARITHMETIC L.OGIC, IN & OUT BUFF~RS, SN141S1, USEO IN f PP 12

2 L.OOK"AHEAD ELEMENTS (741Sa), USES W961 BOARD. USED WITH M190 OR M~5! ~80ARO 50s~~9.2)

a ..

INPUT PRIORITY ENCOOERS, 9J18 IC, 50~08912 BOARD

1/0 BUS MUX CONT fOR PDp9 P~RIPHERALS (ENAB~E BUS IN/OUT ~3V LoGIC), ~EE M104

18 BIT REGISTER W PARITy, DOUBLE'

2 4~8IT TRt·ST4TE 0 r~lP fLOP REGlSTERS, SINGL.E 5 2 74114 HEX FF ON W960 ETCH, SING~E 5

74174 HEx rF pLUs 1585 COMPARITOR ON W96~ ETCH, sINGLE 5 3 JK Frs, S, CL. C

a SET~RESET Frs, (Ml1;S GATES)

4 JK frs. CAN 00 SYNCHRONOUS elNARY COUNTING 5 0 Frs, ALL pINS AVAILABL.E

6 0 frS

6 INDEPOENOENT JK Frs

e BIT SHIrT & BUFF£R REGISTER, D FFS (NEVER MADt), 8 BIT UP/DOWN COUNTER

(NEVER MADE) 10 BIT eUFFER S~lFT REGISTER

TTL OUTPUT M6oULE, 16^w811 REGISTER, OPEN COLLECTOR TO ~854, SINGLE 6.' TTL. INPUT MODULE, 16eBIT REGISTER FROM H854, SINGLE 8,5

-6 BIT UP/DOWN COUNTER

6 BIT ~EFT~RIGHT SHIFT REG, LOAD 'ROM 2 SOURCES, (2~R2~2'~)

1 DECADE BCD UPIDOWN JAM COUNTER WITH PARALLEL READ IN 6 BIT ACCUMULATOR WITH 3 INPUTS

4 BITS OF 3 REGISTERS, COMMON ADDER PER

BIT,

COMMON CLOCK PER WORD 6 0 FF'S. CM2S6 WITHOUT CL.EAR JUM~ER C~OICE)

CLOCK REGISTER FoR PDP.~2.

4

elT COUNTER WITH SUFFER REGISTER ,QR PRE~Er OR REAOOUr

~4~DIRECTIONAL SHIrT REGISTER, 9 9ITS, 2 PAHALLEL L.OADS

? BIT SYNCHRONOUS COUNTER WITH JA~ & CLEAR PRESETS, Doua~~

TAPE REGISTER FOR PDP.12, 2 BITS, 6 REGISTERS, OOUBL.E REGISTER POR PDP~l" 4 81TS. MA & M8

e BITS WITH DATA PATHS rOR KAli, 2 LATCHES, ADOER, OOU8~~ 8,5 SYSTEM TESTED M224

PROCESSOR MEMORY FOR KA11, 16 91TS X 16 aIT~. DOUBLE a~5

SYSTEM TESTED M225

1 BIT AL.L REGISTERS (EXCEPT ACe) fOR PDP-15 ACCUMULATOR FOR POP~15, 9 8ITS

MARK TRACK DECODER fOR TC08,TC15

4 UNIT SELECTOR nRtVER, VP15~M, 4FFS WITH BUFFERED OUTPUT GATES BINARV/BCD/BINARy CONVERTER. 12 BITS, 5 MHi COUNT RATE

DUAL 12 BIT PRESETTABLE REPEATABLE COUNTER, DOUBLE, USED IN AIP12 16 WORD 1 BIT MEMORV WITH COMMON CLEAR

12 WORD SHIFT REGISTER WITH PARAL~EL LOAD, C~EAR, COMMON CLOCK 3 8 BIT REGISTERS, ADDER & ~/R SHIFT, KE11~A

3 12

BXT

REGISTERS. 2 STORAGE & 1 CTS FOR 1⁴/L. DOUBLE

MonEL.

NO M236 M237 M238 M239 M242 M241 M242 1'1243 1'1244 1'1245 1'1246 M247 M248 M249

1'1250 1'12500 1'1251 1'1252 1'1253 1'1254 1'1255 1'1259 1'1260 1'1261 1'1262 1'1266 M270 M271

M270~

PRUD DES

L PJ[ ENGR

~on

MOO

CAT 11 15 12 15 II 11 CAT

12 1;3 CAT 14

12 11 1~

la

12.

11 10 CAT CAT IPG 12 11/05-R fJC

Ww

80 DCB WW SU DCB AR

ATT 01 ATT ATT

ATT SNT OMT BO ATT DCB DCB EK DREW OAe EWB

ONE~SHOiS~ DELAYS

M~HJ2

1'13020 1'1304 M304 .. yA

M3k'!6 M3(1J7

M3(1J7~

1'1308 1'1309 1'13121

M310~YA

1'1311 1'1312 1'1321 1'1360

M36~",YB

1'1362 1'1363

1'1380

CAT CA"

12 TE MOO 12

10 14 CAT 8 15 15 10 C.AT

SSCAL lZ 10 I P G

MORO RI EG RC GP8 OREW SU AR AC ATT BLE SU SU

STATUS

MO/YR DESCRIPTION

5 5 5 5 5 5 5 5 S 5 5 5 5 5

12 8IT SYNCHRONOUS UP/DOWN COUNTER WITH PARA~LE~ LOAD, ETCH BD 50=089~1

3 DIGIT BCD SYNCHRONOUS UPlgOWN COUNTER WJTH PARALLEL LOAD, ETCH BD 5~o08931

2 4-BIT SYNC UP/OOWN CNTR WITH PARALLEL ~OAO, SEP UP & DOWN CLOCKS, ETCH BO 50.08912 (W~61)

3 4~BIT COUNTERS (8291'5) OR 74197,PARAL~EL LOAD, SING~E

x

5 6 SET~RESET rr's MADE 'ROM 74H 40 BUFFERS

1/72 6 0 Fr'S C74H14) WITH COMMON C~OC~

5/73 H EQUIVALENT TO 1'1202

1/72 8 D FF'S C74H74) WITH 2 COMMON CLOCKS, 4 BITS EACH

6 eKTS, EACH 3 INPUT MX W ~ATC~, ~ON~lNV, ENABLES 4 & 2. 3 TtMES, SIN~~E X 8.5 2 4~BIT SHIrT REGISTERS W PARALLE~ READ IN! USES BOARD 50~08912 (SEE W961)

1/12 5 0 F~IP-f'~OPS, ALL PINS BRQUGHT OUT, (74H7 .. )

-4/72

6

SET~RESET FF'S; c~OCKED TO

6 0 Fr's,

SINGLE

x 5"

8 BIT SHIrT RIGHT, PARA~LEL LOAD. ,0~08914 ETC~, 7495 lC'~

12 BIT BUf' REG WITH OPEN COL~ECTOR OUTPUT GATES, SINGLE

x

5 1/72 16 WORDS, 4·BIT MEMORY,

(r

903,), ~110

5 11/12 2 64~WORo 4-81T MOS 1ST IN 1ST OUT MEMORIES, SING~E 5, 50~9912' NEEDS -l2V 7 16 WORDS, 8.BIT MEMOAY (9033), M250 PINS INTENDED, Kt10

2 10/69 16 WORDs. 4 BITS (MOT 4005~.,Kl1~' M250, DOuBLE 5 1/72 16 WORDS. 12eBIT MEMORY, USES TI 7489

1 5/71 256 20^wBtT. 3 256 WORD 4~BIT RAM, ~20 NSEC CYC~E. QUAD X ~,5

5 2/14 256 X 12 BIT RAM (INTEL 31~.) • 8Vf'FER, DOUBLE 5

5 ASSOCIATIVE MEMORY, 2X8, SHIFT REG CAPABILITY, SING~E, 8,5, KT11

5 1/12 ASSOCIATIVE MEMORY, 4 WORDS, 12 81TS, KI10, 4102 Ie, FA1R~HILD, 35 NS MATCH TJM.E, DOUBL~

5 SLO SYN/RtSPONSYN STEPPING MOTOR TRANS~ATOR, 4 WINCINGS 5 rUJITSU/WARNER STEPPING MoTa R TRA~SLATOR, 5 WINDINGS 6 4/71 K2~6 WITH INPUT rlLTERS REMOVED

1 3/72 256 X 12 ROM, SN14187, R'1 0 • SING~[ 5 1 3/74 8K X 18 MOS ARRAY «TMS 403 0 ., QUAe 7

2 4/74 8X32 EeL BLASTABLE PROM (1~139), 4 LAyER sINGLE 5, 5010a7~ (w9611)

5 5 5 3 5 5 5 5 5 5

7/73

4/74

1/72 4/72 3/14 5 5/13 5 5 5 5 1 5 5 5

1/72 5/74 1/12 1/72 11/71

2 ON["SHOTS

2 ONE~SHOTS TO REP~ACE M3~2, MYSTERISIS ADDED TO PREVENT NOISE TRIGG[~ING

4 ONE~SHOTS, 100 NSEC ^OR 1 USEC O~~Y

1'1304 MODlrlED TO Bt 250 NS OR 2,5 USEC INTEGRATING ONE SHOT, 500 NSEC MI~

DUAL lNTEGRATING ONE.SHOT, ~sES FAIRCHILD 9~01'S' 5 US!C TO 500 MSEC DUAL. INTEGRATING ONE SHOT, ^~00NSEC TO 20 M5EC IN 5 STEPS

INTEGRATING ONE SHOT, EDGE OR PULSE TRIGGERED, CLoeK, POWER UP & DOWN POWER SEQUENCE FILTER (2 DE~AYS CIRCA 500 USEC) SINGLE 8,5

TAPPED DELAY LINE, 500 NS[C TOTAL. 50 NSEC TAPS, 2 PA'S,

Ie

LEVELS IN & OUT

M31,~W lTH F'I I NVrRTED & 2,3 USEc ~ONG

2 TA·PP·ED DELAY L I N£S, 250 NSEC EA c~, 25 NSEC STEPS

6 100 ~HM DELAYS, 2 AT 30 NS, 3 AT 50 NS, 1 VARIABLE 0 TO 40 NS, 74H4~ INPUTS M311 EXCEPT 1 DELAV LINE. 1 OUTPUT BUfFER CAN DRIVE 30 TTL H LOADS

VARIABL.E DELAY LINE, IC LEVELS IN, (I..lKE B36") M360 W MIN DELAY or 25 NSEC

DELAY, 25 TO 50 NSEC

DEL. AY 15 TO 80 N SEC, 1 N V E R T S SINGLE SHOTS. DR80

113

MODEL NO

PROn f)ES Llr-.E ENGR CLOCKS

M401 CAT M401"YA COM

"1401 .. Y8 SSCAL M402 15 M4t'l2-YA $SCAL M402 ... YB ^~SC:AL M4et3 CAT M404 CAT M405 CAT M405,.,yA COM M405-YB SSCAL

~4Ql50 COM

~'H~50';:'YA

M4051 TVP M41il1 MOO M410 ... yA 15 M4i5 12 M420 15 M<4201 PERIPH M43il! MOO M452 CAT M452 ... yA F'S M453 8 M454 11 M4540 11 M455

e

M499

alE:

BLE ELlA DPS oPS JB JB

Me

BLE 5S COM JG AR FA ELlA PM DeB FMS WH VB MC ER WH INPUT CONVERTERS M5000

M5005 M5006 M500 M501 M502 M503 M503 ... YA M504 M506 M506",yA M507 M508 M509 M5i0 M510 .. yA M511 M5i2 M513 M514 M5i5 M516

OC SSCAN SSCAN CAT CAT CAT 12 F'S 8 CAT css

CAT A 14 CAT 12

1'~

11 PERIPH 1 15

EWB OF OF' DCB

RI

ERK

EK JO AR DCB AW

w104

ET ET

Jo

STATUS ''''O/YR

5 1 1 5 3 3 5 5 5 1 1 5

2 5 1 5 5 5

5 5/74 5/14 1/73 1/73 3/72 4/72 5/14 5/74 1/14 71'14 5110

4/71 1 10111 5 2174 5 4 2/1.

'5 8113 1 11/711')

2 1 1 5 5 5 5

4114 9174 9114

'5 UJ/73 1 3172 5 2 5 5 5 5 6 5 1 1 5 5 5

9/69 5/13 4111 11/71 9114 9114

DESCRIPTION

VARIABI..E CL.OCK

M401 W WIDE OUTPuT PULSE H401 W 25 NSEC OUTPUT PULSE

REMOTE~Y VARIABLE C~OCK, USEs 5V ~HOTOMOO, 2 He TO 1 MHl R8 CHANG£O TO 680K; C1 CHANGEO TO

t

MfD (HALVES FREQUENCV) R8 CHANGED TO 680K, Cl CHANGED TO 3,9 MFO

VARIABLE C~OCK, 1 KH~ TO 50 KH~f 2 ONE·SHOTS. 74123

CRYSTA~ CLOCK, 2MHl TO 5 KHl, BINARY OR BCD COUNTDOWN cRYSTAL CLOCK, paS & NEG PULSE OUTPUTS, 5 KHl TO 10 MHl M40' W ~IDE OUTPuT PULSE

M405 W 25 NSEC OuTPUT PULSE

CRVSTAL CLOCK, 5KHl TO 5 MH~. NOT TUNABLE, NO CHOKES 1 5/74 M4B50 W wIOE OUTPUT PU~SE

B/E OMNIBUS M4B50, HANO~E END 'INGERS fOR D~a-'E (H866), QUAO RESONANT REED CLOCK

879 H~ M4Ul . 20 MH~ XTA~ CLOCK

PHASE LOCK CLOCK, RP09. RP15

PHASE ~OCK CLOCK PoR RS64, NOHINA~ 750 KC

MU~TIPLl£S INPUT PREQ BY ,001 T'Mt~ X TO THE .N POWER,X BETWEEN 0 & 1~, N BETWEEN ~ & J, COUBLE ~ '"

TELETYPE CLOCK, SQUARE WAVES AT 88B & ~20 Hi, POR M106, M~07

'.65 US M452 'OR PMK02 -M452 WITH VARIABLE PREQ

CRYSTAL. CLOCK W SIMULTANEOUS OUTPUTS OF ~8.8'19,2. 9,6,

4,a,

2.4,1.7~~ KHl 2,152 KHi, SINCL£ 8,5 e'OR PC1i-.A, DP11-A)

M454 W MORt FREQUENCIES AVAILABLE,

VARIABLE CLOCK, 2 RANGES, 4 • 20 ~S. 0,4 ~ 2 MS, BY JUMPER 100 KH2 CLOCK ^a PULLS MEM START I~ 8/E

4 CH EeL '0 T'L CONVERTER, MC~012'~ 501087 • ~AVER SlNG~~ 5 (W9611)

C~~, 36 CH OPTICAL COUPLED INpUT TO TT~, 5-1.2SV IN, QUAD

~SC, 36 CH 01" AMP ./e25V IN TO TT~, QUAO NEGATIVE BUS RfC£lvER (NEG EQUIV yo M5~0)

SCHMITT TRIGGER

NEGATIVE INPUT CONVERTER, 2 CHANNELS, 0 & .~y IN OlrrERENTJAL SCHMITT, 2 CHANNELS. PA IN EACH R[PLACEMC1709 WITH LH0024 TO MAKE rASTER, eb01 4 SCHMJTTS. 4 ONE.SHOTS

NEGATIVE INpUT CONvERTER, 6 CHANNELs. 0 & -~V IN M506 WJTH 470 INPUT R'S CHANGED TO 300 OHMS

NEG BUS TO POS BUS CONY, 6 CKTSi OPEN COLb aUT, GND IN • ~NO OUT NEG BUS TO POS BUS CONY, 6 CKTS. OPEN COLL OUT, GNO I~ ~ PkUS OUT

10 DIffERENTIAL aUs RECEIVERS (fAIR 9622) lJ0 OHM OlF'PERENTIAL TERMINATORS I/O BUS RECEIVER~ 8 CKTS, PaS BUS

M510 MOOI'IED TO ACCEPT RTL INPUTS WITH 1. VOLT THRESHOLD UNIBUS RECEIVER, 15 CKTS. SINGLE X 5, <4 GND, OS11, Ob10 16 SCHMITT CKTS W INPUT rIlTERS, SINGLE 5

10 OPTJCA~ ISoLATORS, TTL OYTPUT, SINGLE 5

TU10 TRANSCEIVER (FOR CONNECTlON TO TCSS, TC59, & TM10), SEE M5~9, DO~BLE

REAL TIME CLOCK, 12 VAC INPUT ON TABS, USES +11V & +5V POS INPUT RECEIVER, 6 CKTS, l,4y THRESHOLD, (M506 PINS)

MODEL PROf) DES STATUS

MO/YR DESCRIPTION ¹⁷⁵

NO L.INE ENGR M517

MS 18 M519 M520 M521 MS21 .. YA M522 M523 1'1530 M531 M563 MS64 MS65 M570 MS85 M586 M587 M58a MS89

alE F'E~IPH

Man

CAT

MS TYP TYP MOD PERIPH 13 10

css

11 11 CSS 14

Js AW

F"p JW DREW su SU AR SK MC

Me

BMW AR

5 5173 5 11/71 1 1/71

5 5 3 5 4 7 5 2 5 5 1

1~/72

8/73 4/74 7/69 7/72 1/72 2/14 1 4114 5 4114 5 2/74

;3 1/14 5 '11/12

M507 WITH AN ENABL.E INPUT

3 DIFFERENTIAL SCHMITTS & 8 BJT I~PUT REGlSTER (A5~3 C~TS), DS8~EA

TU10-C,"D BUS TRANSCEJ.V~R, SEE M5l4

pos sUS RECEIVER WITH STR08~. 6 C~ANNE~S, HIGH IMPEOANCE 4 CH K TO M CONVERTER W SCHMITT TRIGGER, INV & NON~INV OUTPUTS M521 W 3 CKT W 1 MS TIME CONSTANT, 1 CKT STND

2 INPUT CONVERTERS 0&~6V lt6^MA. 4~US, lCH .~5&0V, 2CH 0&5V C~AMP W rl~TE.R (FOR PHOTOCOM~) SING~E 5 SELEcTABLE RANCE INPUl CONVtRTER • SELECTAB~E LOAD RESISTORS & VOLT4G~, SINGLE 5

(NEVER BUILT). NEG BUS RECEIVER

-8 CHANNEL NEGATIVE SUS RECEIVER WITH NOISE FlLTERING (PIN COMP WIT~ M'0~) 4 XMTRS & 4 RCVRS, RS10, SING~E

x

1/0 BUS RECEIVER, NEG BUS, POS LOGIC, 8 CKTS, L.IGHT INPUT bOAD MEM BUS RECEIVER, NEG BUS, POS LOGIC, 8 CKTS

(NEVER MADE) EIA INPUT CONvERTER TO TTL OUT, REPLACES W57~, 5V INS!EAO OF 10 V, 4 CHANNE~S

4 CH CDC 1600 REcEIVERS, SING~E 5

1 CH ASYNC MoDEM D;11-SA (8,L~ 113A) ORIC_NATE ONLy, DBL

x

8.5 1 CM ASYNC MODEM DF11eBB (BeLL 11~B) ANSWER ONLY, DSL ~ 8,5 4 CH 01" SEND/REC FOR DMll (DM88l~, OM88~0J, SINGL.E x a.,

1 CH OPTICAL COUPLED 45 OHM 200 KC SEND & R~C, SlNC~E X 5W MATEpN-~OK

INPUT/OUTPUT CONVERTERS M590 cSS

M59~0 11 M5901 11 M5902 11 M5903 11 M5903;;'YA

11

M5904 11 M5905 css M5906 COM M5907 SSCAN M5908 COM M590S;'YA COM M591 11 M·592 UJ M593 r,SS

M593~YA CSS M594 11 M594 .. yA 11 M594 .. YB 11 M5940 10 .M5941 cSS

M5942 11 M5943 css M5944 M595 11 M596 11 M5960 11 M597 COM M598 COM M599 COM

PETERS 3 2110 DIFFERENTIAL SENO/RECEIVE, FOR MAR~ CENTURY INTERFACE, 2 eH Vs 4 3/74 16 eH TTL RECEIVER, D~~~, OOU~LE ~.5

Vs 4 5/13 16 CH EIA TRANSMITTER, OJ11, DOUB~E S.5

VB 4 2/14 16 CH 'ULL DUpLEx TTY TRANSCEIVER' DJ11, DOUBL.E 8,5 POT 4 9113 MASS BUS TERMINAL TRANSCEIV~R, OOUBLE 8,5

POT 4 2114 M5903 W TERMINATORS

POT '1/14 MASS BUS CONTROL TRANSCEIvER, DOU~LE 8,5

SPRY 1 1/14 16CH EJA~CCIT' TO TTL. ~6CH TTL TO EIA-COITT, MOOEM CONTROL DOUBLE 8,' RAC 4 9114 16 CH EIA8TT~. TTL.ttA, PRIORITy SOCKETS, 2 He,., OHil.AD, ~AE, OOUBL~ 8,5 Ow 2 411. OA30 SUS EXTENDER, 8 CM RECEIVE & TRANSMIT fUL.L DUpLEX O~ff, 1060 FT, QUAD

DR 1 4114 MULTIDROP TRANSCEIVER, 4V P~P lMHi DrPHASt INTO TERMINAT~O 15 OHM CABL£i 5SHY SENSITIVI!Y.OOUBLE 8.5 DR 1 9/74 56KB TRANSCEIV[R, OOUBLE 8,5

VB 5 5 CH EIA TO DEC. 4 eH DEC

fa

EIA, SINGLE,8,5 SU 5 1/12 1/0 DEVICE SELECT .USED WITH M7100t1074H

Ie's

KB 2 4/72 6 CH OJFFEREN'IAL RECEIVER, NAT SEMI 8820

Dans le document 18, 1-5 (Page 174-177)