Pin No.
MB87031 MB87031 Designator Function
25 69 SOBI7 Inputs for the SCSI data bus. Most significant bit (MSB) is SOBI7; least 66 72 SOBI6 significant bit (LSB) is SOBIO. SOBIP is an odd parity bit; parity
27 77 SOB05 II the bus driver is an open collector device, these signals should be
29 83 SOB04
70 85 SOB03 applied directly to the driver circuit. II the new bus driver is a 3-state 32 89 SOB02 device, these signals are used as data and SOB07 -SOBOO and 72 93 SOB01 SOBOP are used as drive-enable signals.
36 96 SOBOO
23 68 SOBOP
37 17 CS
Selection enable signal for accessing an intemalWiGter in SPC. When CSis active, input/output signals RD, ROO,
wr, ,
OP, AO-A3, and DO-D 7 are active.38 16
m
Input clock lor controlling internal operation and data transler speed 01 SPC.Input strobes used for reading out contents 01 internal register; strobes are effective only when CS is active low.
39 20 RD When ROO is active low, the contents 01 an internal register selected 40 21 ROO buy address inputs AO-A3 are placed on data bus lines 00-07 and OP.
For a data transler cycle in the program transler mode, the trailing edge 01 'AU is used as a timing signal to indicate the end 01 data read.
41 1 ORESP During a data transfer cycle in the DMA mode, DRESP is a response signal to the data transfer request signal DREQ.
The DRESP pin must be refreshed with an applied pulse after each byte of data is transferred to output operations, the falling edge of DRESP is used for sampling data on HDBO-HDB7 and HDBP bus lines; in input operations, the SPC holds data to be transferred onto HDBO-HOB7 and HIDBP until the falling edge of DRESP occurs.
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PIN DESCRIPTIONS
(Continued)Pin No.
MB87031 MB87031 Designator Function
51 33 07 Used for writing or reading data into or from an internal 50 32 06 register in SPC; these bus liens are 3-state and bidirec-49 31 05 tional. The (MSB) is 07; the LSB is ~O. OP is an odd parity
48 30 04 bit.
80 27 03
When the CS and 'RIm inputs are ac~ve Low, contents of the internal
79 26 02
43 25 01 register are output to the data bus (read operation). In operations other 42 24 DO than read, these bus lines are kept in a hgh-impedence state.
52 34 OP
44-47 35-38 80-83 Address input signals for selecting an internal register in the SPC. The MSB is A3; the LSB is AO.
When CS is active low, readlwrite is enabled and an inter-nal register is selected by these address inputs via data bus lines 00-07 and OP.
53 22 INTR Requests an interrupt to indicate completion of an SPC internal operation or the occurrence of an error.
Interrupt masking is allowed except for an interrupt caused by the RSTI input (reset condition of SCSI). When an inter-rupt is permitted, the INTR signal remains active until the interrupt is cleared.
56 27 SEll Used for receiving SCSI control signals; outputs of the 61 59 BSYI SCSI receiver can be directly connected. (Waveform dis-58 41 REOI tortion or any other disturbance should not occur in the 60 55 ACKI REOI and ACKI signals which are used as timing control
57 49 MSGI signals for sequencing data transfers.)
55 45 ClDI
54 43 1101
62 61 ATNI
59 63 RSTI
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PIN DESCRIPTIONS
(Continued)Pin No.
MB87031 MB87031 Designator Function
76 2 DREQ When executing a data transfer cycle in the DMA mode, DREO is used to indicate a request for data transfer be-tween the SPC and external buffer memory. In the DMA mode, routing of data is as shown below. Output Opera-tions:
From external buffer memory to HDBO-HDB7/HDBBP to SPC internal data buffer register (8 Bytes) to
SDBOO-SDB07/SDBOP to SCSI. Input Operations:
From SCSI to SDBI9-SDBI7/SDBIP to SPC internal data buffer register (8 bytes) to HDBO-HDB7/DHDBP to external buffer memory. In an output operation, DR EO becomes active to request a data transfer from the external buffer memory when the SPC internal data buffer register has free space available. In an input operation, DREO be-comes active to request a data transfer to the external buffer memory when the SPC internal buffer memory con-tains valid data.
77 18 WT Input strobe used for writing data into an SPC internal reg-ister; this signal is asserted only when CS is active Low.
On the trailing edge of WT, data placed on data bus lines DO-D7/DP is loaded into the internal register selected by address inputs AO-A3, except when all address lines are High (AO-A3 = H).
For a data transfer cycle in the program transfer mode, the trailing edge of WT is used as a timing signal to indicate a data-ready state.
78 19 WTG When WTG is active low, data appearing on data bus lines DO-D7/DP is output to HDBO-HDB7/HDBP if the following input conditions are satisfied.
CS=L
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ADDRESSING OF INTERNAL REGISTERS
Both the MB87030 and the MB87031 contain16 byte-wide registers that are externally accessible. These registers are used to control internal operations of the SPC and also to indicate processing/result status. A unique address, identified by address bits A3-AO, is assigned to each of the sixteen registers. These addresses are defined in Table 1.
(Note: The phase sense (PSNS) and SPC diagnostic (SDGC) registers have the same hexadecimal address;
however, depending upon whether a read or write command is executed, the registers provide two separate functions.)
Table 1. Internal Register Addressing
Chip Select (CS) Address Bits
Register Mnemonic Operation A3 A2 A1 AD
Interrupt Sense R
INTS 0 0 1 0 0
Reset Interrupt W
Phase Sense PSNS R
0 0 1 0 1
SPC Diagnostic Control SDGC W
SPC Status SSTS R
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Table 1. Internal Register Addressing (Continued)
Addr ••• Bits Register Mnemonic Operation Chip Select (CS) A3 A2 A1 AO
R
Transfer Counter High TCH 0 1 1 0 0
W R
Transfer Counter Middle TCM 0 1 1 0 1
.w
R
Transfer Counter low TCl 0 1 1 1 0
W R
External Buffer EXBF 0 1 1 1 1
W
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