31-16 RES Reserved locations. Written as ZEROs and read as undefined.
1~LADRF[31:16] Logical Address Filter, LADRF[31:16]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSRO has been set or a direct register write has been performed on this register.
Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit.
CSR10: Logical Address Filter 2 Bit Name
31-16 RES
Description
Reserved locations. Written as ZEROs and read as undefined.
1~LADRF[47:32] Logical Address Filter, LADRF[47:32]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSRO has been set or a direct register write has been performed on this register.
Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit.
CSR11: Logical Address Filter 3
Bit Name Description
31-16 RES Reserved locations. Written as ZEROs and read as undefined.
15-QLADRF[63:48] Logical Address Filter,
Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit.
CSR12: Physical Address Register 0 Bit Name
31-16 RES
1~PADR[15:0]
Description
Reserved locations. Written as ZEROs and read as undefined.
Physical Address Register, PADR[15:0]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSRO has been set or a direct register write has been performed on this register.
Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit.
CSR13: Physical Address Register 1 Bit Name Description
31-16 RES Reserved locations. Written as ZEROs and read as undefined.
1~PADR[31:16] Physical Address Register, PADR[31 : 16]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSRO has been set or a direct register write has been performed on this register.
Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit.
CSR14: Physical Address Register 2 Bit Name Description
31-16 RES Reserved locations. Written as ZEROs and read as undefined.
CSR15: Mode
Read/Write accessible only when either the STOP or the during the PCnet-PCIIi controller initialization routine with the cor-responding initialization block values. The host can also write directly to this register.
Reserved locations. Written as ZEROs and read as undefined.
Promiscuous Mode.
When PROM is set to ONE, all incoming receive frames are accepted.
Read/Write accessible only when either the STOP or the SPND bit is set.
Disable Receive Broadcast.
When set, this bit disables the PCnet-PCI II controller from receiving broadcast messages.
DRCVBC has no effect when PROM is set to ONE.
Read/Write accessible . only when either the STOP or the SPND bit is set. DRCVBC is cleared by H_RESET or S_RESET and not affected by STOP.
Disable Receive Physical Ad-dress. When set, the physical ad-dress detection (Station or node 10) of the PCnet-PCI II controller will be disabled. Frames ad-dressed to the node's individual physical address will not be rec-ognized. DRCVPA has no effect when PROM is set to ONE.
Table 23. Network Port Configuration
ASEL Link Status
ReadlWrite accessible only when either the STOP or the SPND bit is set.
Disable Link Status. When DLNKTST is set to ONE, moni-toring of Link Pulses is disabled.
When DLNKTST is cleared to ZERO, monitoring of Link Pulses is enabled. This bit only has meaning when the 10BASE-T network interface is selected.
ReadlWrite accessible only when either the STOP or the SPND bit is set.
Disable Automatic Polarity Cor-rection. When DAPC is set to ONE, the 10BASE-T receive po-larity reversal algorithm is dis-abled. When DAPC is cleared to ZERO, the polarity reversal algo-rithm is enabled.
This bit only has meaning when the 10BASE-T network interface is selected.
ReadlWrite accessible only when either the STOP or the SPND bit is set.
MENDEC Loopback Mode. See the description of the LOOP bit in CSR15.
ReadlWrite accessible only when either the STOP or the SPND bit is set.
Low Receive Threshold (T-MAU Mode only)
Transmit Mode Select (AUI Mode only)
Low Receive Threshold. When LRT is set to ONE, the internal twisted pair receive thresholds are reduced by 4.5 dB below the standard 10BASE-T value (approximately 3/5) and the unsquelch threshold for the RXD circuit will be 180
~AMD
PRELIMINARY post squelch threshold will be one half of the unsquelch threshold.This bit only has meaning when the 1 OBASE-T network interface is selected.
Read/Write accessible only when either the STOP or the transmit port is idle. When TSEL is cleared to ZERO, 00+ and DO- yield zero differential to op-erate transformer coupled loads (Ethernet 2 and 802.3). When TSEL is set to ONE, the 00+
idles at a higher value with re-spect to 00-, yielding· a logical HIGH state (Ethernet 1).
This bit only has meaning when the AUI network interface is selected.
Read/Write accessible only when either the STOP or the SPND bit is set. Cleared by H_RESET or S_RESET.
8-7PORTSEL[1 :0] Port Select bits allow for software controlled selection of the net-work medium.
GPSIEN (CSR124, bit 4) must be . set to ONE in addition to pro-gramming the PORTSEL bits in order to select the GPSI port as the active network port.
6 INTL
5 DRTY
4 FCOLL
Table 24. Loopback Configuration
LOOP INTL MENDECL Loopback Mode
0 X X Non-Ioopback
1 0 X Extemal Loopback
PORTSEL settings of AUI and 10BASE-T are ignored when the ASEL bit of BCR2 (bit 1) has been set to ONE.
Read/Write accessible only when either the STOP or' the de-scription of LOOP (CSR15, bit 2).
Read/Write accessible only when either the STOP or the SPND bit is set.
Disable Retry. When DRTY is set to ONE, PCnet-PCI " control-ler will attempt only one transmission. In this mode, the device will not protect the first 64 bytes of frame data in the trans-mit FIFO from being overwritten, because automatic re-transmis-sion will not be necessary. When DRTY is cleared to ZERO, the PCnet-PCI " controller 'will at-tempt 16 transmissions before signaling a retry error.
Read/Write accessible only when either the STOP or the SPND bit is set.
Force Collision. This bit allows the collision logic to be tested.
The PCnet-PCI " controller must be in internal loopback for FCOLL to be valid. If FCOLL is set to ONE, a collision will be forced during loopback transmis-sion attempts, which will result in a Retry Error. If FCOLL is cleared to ZERO, the Force Collision logic will be disabled. FCOLL is defined after the, initialization block is read.
3 DXMTFCS
2 LOOP
DTX
ReadIWrite accessible only when either the STOP or the SPND bit is set.
Disable Transmit CRC (FCS).
When DXMTFCS is cleared to ZERO, the transmitter will generate and append an FCS to the transmitted frame. When DXMTFCS is set to ONE, no FCS is generated or sent with the transmitted frame. DXMTFCS is overridden when ADD_FCS is set in TMD1.
If DXMTFCS is set and ADD_FCS is clear for a particular frame, no FCS will be generated.
The value of ADD_FCS is valid ADD_FCS bit in TMD1.
This bit is called DTCR in the C-LANCE (Am79C90).
ReadIWrite accessible only when either the STOP or the SPND bit is set.
Loopback Enable allows PCnet-PCI II controller to loopback is enabled. In combina-tion with INTL and MENDECL, various loop back modes are defined in the Loopback Configuration table.
Read/Write accessible only when either the STOP or the SPND bit is set. LOOP is cleared by H_RESET or S_RESET and is unaffected by setting the STOP bit.
Disable Transmit. When DTX is set to ONE, the PCnet-PCIII con-troller will not access the transmit descriptor ring and therefore no transmissions are attempted.
When DTX is cleared to ZERO, TXON (CSRO, bit4) issettoONE after STRT (CSRO, bit 1) has been set to ONE.
ReadIWrite accessible only when either the STOP or the SPND bit is set.
°
DRX Disable Receiver. When DRX is set to ONE, the PCnet-PCIII con-troller will not access the receive descriptor ring and therefore allReadiWrite accessible only when either the STOP or the SPND bit is set.
CSR16: Initialization Block Address Lower