Bus commands indicate to the target the type of transaction the master is requesting. Bus commands are encoded on the C_BE/(3-0) lines during the address phase. PCI bus com-mand encoding and types appear in Table 2-1.
Table 2-1: PCI Bus Com.m.ands and Encoding
0001 Special Cycle 0010 1/0 Read 0011 1/0 Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved
1010 Configuration Read 1011 Configuration Write 1100 Memory Read
Mul-tiple
1101 Dual Address Cycle 1110 Memory Read Line
1111 Memory Write and Invalidate The SYM53C876 does not respond to this mand as a slave and it never generates this com-mand as a master.
Special Cycle Conulland
The SYM53C876 does not respond to this mand as a slave and it never generates this com-mand as a master.
I/O Read Conulland
The 110 Read command is used to read data from an agent mapped in 110 address space. All 32 address bits are decoded.
I/O Write Conunand
The 110 Write command is used to write data to an agent mapped in 110 address space. All 32 address bits are decoded.
Reserved Conullands
The SYM53C876 does not respond to reserved commands as a slave, and it never generates these commands as a master.
Mem.ory Read Com.m.and
The Memory Read command reads data from an agent mapped in the Memory Address Space.
The target is free to do an anticipatory read for this command only if it can guarantee that such a read has no side effects.
Mem.ory Write Com.m.and
The Memory Write command writes data to an agent mapped in the Memory Address Space.
When the target returns "ready", it assumes responsibility for the coherency (which includes ordering) of the subject data.
Configuration Read Conunand
The Configuration Read command reads the con-figuration space of each agent. An agent is
selected during a configuration access when its IDSEL signal is asserted and AD(l-O) are 00.
During the address phase of a configuration cycle, AD(7-2) address one of the 64 dword registers (where byte enables address of the bytes within each dword) in the configuration space of each device and AD(31-11) are logical don't cares to the selected agent. AD(l0-8) indicate which device of a multi-function agent is being addressed.
Configuration Write Connnand The Configuration Write command transfers data to the configuration space of each agent.
An agent is selected when its IDSEL signal is asserted and AD(l-O) are 00. During the address phase of a configuration cycle, the AD(7-2) lines address the 64 dword registers
(where byte enables address of the bytes within each dword) in the configuration space of each device, and AD(31-11) are logical don't cares to the selected agent. AD(lO-S) indicate which device of a multi-function agent is addressed.
Mem.ory Read Multiple Com.m.and This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnect-ing. The SYM53CS76 supports PCI Read Multiple functionality and issues Read Multi-ple commands on the PCI bus when the Read Multiple Mode is enabled. This mode is enabled by setting bit 2 of the DMODE regis-ter (ERMP). If cache mode is enabled, a Read Multiple command is issued on all read cycles, except op code fetches, when the fol-lowing conditions are met:
1. The CLSE bit (Cache Line Size Enable, DCNTL, bit 7) and the ERMP bit (Enable Read Multiple, DMODE, bit 2) are set.
2. The Cache Line Size register for each function contains a legal burst size value (2,4, S, 16,32,64, or 12S) and that value is less than or equal to the DMODE burst size.
3. The number of bytes to transfer at the time a cache boundary is reached is at least twice the full cache line size.
4. The chip is aligned to a cache line boundary.
When these conditions are met, the chip issues a Read Multiple command instead of a Memory Read during all PCI read cycles.
Burst Size Selection
The Read Multiple command reads in multi-ple cache lines of data in a single bus owner-ship. The number of cache lines to read is a multiple of the cache line size as allowed for in Revision 2.1 of the PCI specification. The logic selects the largest multiple of the cache line size based on the amount of data to trans-fer, with the maximum allowable burst size determined from the DMODE burst size bits, and the CTEST5, bit 2.
Dual Address Cycles Com.m.and The SYM53CS76 does not respond to this command as a slave, and it never generates this command as a master.
Mem.ory Read Line Connnand This command is identical to the Memory Read command, except that it additionally indicates that the master intends to fetch a complete cache line. This command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some perfor-mance advantage by reading up to a cache line boundary rather than a single memory cycle.
The Read Line function that exists in the pre-vious SYM53CSXX chips is modified in the SYM53CS76 to reflect the PCI Cache Line Size register specifications. The functionality of the Enable Read Line bit (DMODE regis-ter, bit 3) is modified to more resemble the Write and Invalidate mode in terms of condi-tions that must be met before a Read Line command is issued. However, the Read Line option operates exactly like the previous SYM53CSXX chips when cache mode is dis-abled by a CLSE bit reset or when certain conditions exist in the chip (explained below).
If cache mode is disabled, Read Line commands are issued on every read data transfer, except op code fetches, as in previous SYM53C8XX chips.
If cache mode is enabled, a Read Line command is issued on all read cycles, except op code fetches, when the following conditions are met:
1. The CLSE (Cache Line Size Enable,
DCNTL, bit 7) and ERL (Enable Read Line, DMODE, bit 3) bits are set.
2. The Cache Line Size register for each
function must contain a legal burst size value (2,4,8, 16,32,64, or 128) and that value is less than or equal to the DMODE burst size.
3. The number of bytes to be transferred at the time a cache boundary is reached is equal to or greater than the DMODE burst size.
4. The chip is aligned to a cache line boundary.
When these conditions are met, the chip issues a Read Line command instead of a Memory Read during all PCI read cycles. Otherwise, it issues a normal Memory Read command.
Read Multiple with Read Line Enabled When both the Read Multiple and Read Line modes are enabled, the Read Line command is not issued if the above conditions are met.
Instead, a Read Multiple command is issued, even though the conditions for Read Line are met.
If the Read Multiple mode is enabled and the Read Line mode is disabled, Read Multiple com-mands are issued if the Read Multiple conditions are met.
Mem.ory Write and Invalidate Com.m.and The Memory Write and Invalidate command is identical to the Memory Write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the mas-ter intends to write all bytes within the addressed cache line in a single PCI transaction unless inter-rupted by the target. This command requires implementation of the PCI Cache Line Size regis-ter at address OCh in the PCI Configuration
Space. The SYM53C876 enables Memory Write and Invalidate cycles when bit 0 in the CTEST3 register (WRIE) and bit 4 in the PCI Command register (WIE) are set. When the following condi-tions are met, Memory Write and Invalidate com-mands are issued:
1. The CLSE bit (Cache Line Size Enable, DCNTL, bit 7), WRIE bit (Write and Invalid Enable, CTEST3, bit 0), and PCI
configuration Command register, bit 4 are set.
2. The Cache Line Size register for each
function contains a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the DMODE burst size.
3. The chip has enough bytes in the DMA FIFO to complete at least one full cache line burst.
4. The chip is aligned to a cache line boundary.
When these conditions are met, the SYM53C876 issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles.
Multiple Cache Line Transfers
The Write and Invalidate command can write multiple cache lines of data in a single bus owner-ship. The chip issues a burst transfer as soon as it reaches a cache line boundary. The size of the transfer is not automatically the cache line size, but rather a multiple of the cache line size as allowed for in Revision 2.1 of the PCI specifica-tion. The logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size determined from the DMODE burst size bits, and CTEST5, bit 2. Ifmultiple cache line size trans-fers are not desired, set the DMODE burst size to exactly the cache line size, and the chip only issues single cache line transfers.
After each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, no larger than the DMODE burst size. The most likely scenario of this scheme is that the chip selects the DMODE
burst size after alignment and issues bursts of this size. The burst size is, in effect, throttled down toward the end of a long Memory Move or Block Move transfer until only the cache line size burst size is left. The chip finishes the transfer with this burst size.
Latency
In accordance with the PCI specification, the chip's latency timer is ignored when issuing a Write and Invalidate command such that when a latency time-out occurs, the SYM53C876 continues to transfer up to a cache line boundary. At that point, the chip relinquishes the bus and finishes the transfer at a later time using another bus ownership. If the chip is transferring multiple cache lines, it continues to transfer until the next cache boundary is reached.
PCI Target Retry
During a Write and Invalidate transfer, if the target device issues a retry (STOP with no TRDY, indicating that no data was trans-ferred), the chip relinquishes the bus and immediately tries to finish the transfer on another bus ownership. The chip issues another Write and Invalidate command on the next ownership, in accordance with the PCI specification.
PCI Target Disconnect
During a Write and Invalidate transfer, if the target device issues a disconnect the
SYM53C876 relinquishes the bus and imme-diately tries to finish the transfer on another bus ownership. The chip does not issue another Write and Invalidate command on the next ownership unless the address is aligned.