Lithography mask design for processing on InP die 53

mask design. Several lithography mask layers are required to realize an SOA. These mask layers include structures to pattern SOAs, alignment markers for overlay of subsequent lithographic steps, and a number of test structures to assess the quality of each step during processing. Figure 3.2 shows the schematic of the photomask for the SOA processing on the InP die. It is 11×14 mm²in size.

There are four different designs of SOAs in the photomask. These designs have four different lengths 700µm, 900µm, 1.1 mm and 1.4 mm. Each design is arranged in a 50x5 formation. Therefore, in total there are 250 SOAs of each length. The gap between adjacent coupons in both directions is 24µm. The coupons themselves are 45µm wide. The alignment mark-ers are crosses and vernier structures. The latter are used for fine alignment of consecutive lithographic layers. In particular, it is useful to place multi-ple copies of similar markers, in case if some of them are no longer usable during the complex fabrication process. The test structures on the right-hand side include rectangular boxes (e.g. to measure etch progress), TLM structures to measure electrical characteristics and fine features to asses de-velopment time of the photoresist after exposure.

3.3.2 SOA processing on the III-V source wafer

The SOAs are fabricated on an InP wafer. The epitaxial layer structure is grown by metal-organic vapour-phase epitaxy (MOVPE). The InP die of 15 × 19 mm² is first cleaved. The detailed process flow is depicted in

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Design 1

Design 2 Design 3

Design 4

Test structures Alignment

markers

Alignment markers

Figure 3.2: Schematic of a complete photomask for SOA processing on an InP die.

n-metal

TP alignment markers III-V mesa

p-metal coupon mesa 1

coupon mesa 2

Figure 3.3: Schematic of different layers for SOA processing on InP.

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AMPLIFIERS 55

a) Epitaxial layer stack

b) Sacrificial layer removal

Epitaxial layer stack

c) PECVD SiNx deposition d) SOA mesa etching

e) QW patterning etching

f) n-metal deposition g) SiNx and BCB

passivation h) p-metal deposition

i) BCB etch-back j) Release layer etch k) Encapsulation l) Released SOA coupon

m) Laminating stamp to SOA on source n) Stamp picking SOA o) Laminating SOA against PIC p) Applying shear to detach SOA

q) Stamp moving upwards PDMS stamp Glass

PDMS stamp Glass

PDMS stamp Glass

PDMS stamp Glass

r) Transfer printed SOA on PIC PDMS stamp

Glass

s) Removing encapsulation t) DVS-BCB planarization u) via opening v) Metallization

Processing on theInP substrateTransfer printingProcessing on the SOI

AlInAs InGaAs

InP QWs SiNx BCB Resist MetalSilicon

Tethers break

Figure 3.4: The complete process flow of SOA device fabrication which includes patterning on the source InP substrate, micro-transfer-printing, and final

processing steps on the SOI target substrate.

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Fig. 3.4 and various lithographic layers for the fabrication of the SOA are shown in Fig. 3.3. There are five different lithography steps for patterning the III-V mesa along with alignment markers for micro-transfer printing, n-metal deposition, p-metal deposition, coupon mesa 1 and coupon mesa 2. The fabrication process starts by removing the100nm InP sacrificial layer with pure HCl (Fig. 3.4(b)). A PECVD hard mask of 10 nm SiO₂ and 320nm SiN is then deposited (Fig. 3.4(c)). The hard mask is then patterned using i-line UV lithography to define the SOA mesa and III-V adiabatic taper structures. The photomask is centered on the cleaved die.

This leaves some gap between the structures and the edge bead produced during various lithography processing steps. ICP etching is used to etch the InGaAs and p-InP cladding layer. The dry etch process stops when the active region is exposed. Subsequently, p-InP is anisotropically etched in 1 : 1 HCl: H2O for less than a minute. This creates an inwards angled side-wall of the p-cladding when the mesa is oriented along the [01 -1] di-rection (Fig. 3.4(d)). Surface oxides on the active region are removed by dipping in1 : 1 : 20H₂SO₄:H₂O₂:H₂O and1 : 10BHF:H₂O. Next, a layer of200nm SiNx is deposited at270^oCto protect the side-walls of the SOA mesa. The SiNx layer also acts as a hard mask for the patterning of the AlGaInAs QWs. The QWs are partially etched using ICP and partially in 1 : 1 : 20H3PO4:H2O2:H2O (Fig. 3.4(e)) to stop on the n-InP. After the QW etching, Ni/Ge/Au contacts are formed on the n-InP through a lift-off process (Fig. 3.4(f)). The sample is again passivated first with SiNx and then planarized with DVS-BCB. In the following step DVS-BCB and SiNx are etched to expose the p-InGaAs contact layer for Ti/Au metal deposi-tion (Fig. 3.4(h)). The coupon boundaries are then formed by etching back the DVS-BCB and InP using a dry-etching process (Fig. 3.4(i)). The ex-posed release layer is then patterned using1 : 1 : 20 H3PO4:H2O2:H2O (Fig. 3.4(j)). The etching stops at the InP substrate. Afterwards, ICP is used to etch into the substrate so that tethers can anchor to the substrate.

At this moment, the sample is also dipped in 1 : 1 HCl: H2O for few seconds to have a cleaner surface and better adhesion of the tethers to the InP substrate. A thick photoresist of3.5µm is spin-coated on the sample and patterned to encapsulate the device and to form tethers that will hold the device after the under-etching of the release layer. An aqueous FeCl3

solution at7^oCis used to under-etch the AlInAs release layer. It takes 2 hours to etch a45µm wide coupon. The coupons at this point stand on the resist anchors (tethers). These coupons are fabricated in a dense array with a vertical pitch of90µm on the InP substrate. The top view of patterned and released coupons is illustrated in Fig. 3.5. The SOA coupons discussed herein are45µm wide and1.4mm in length.

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Figure 3.5: (top) Microscope top image of an array of SOA devices patterned and released on the native InP substrate, (bottom) Zoomed-in microscope image of

two SOA coupons.

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