LATCHED READ CYCLE WE= HIGH - MEMORY DATA BOOK

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tAA for an address change. Also OE may be used to maintain DO open.

OPERATION READ MODE

The MK4118 is in the READ MODE whenever the Write Enable control input (WE) is in the high state. The state of the 8 data I/O signals is controlled by the Chip Select (CS) and Output Enable (OE) control signals. The READ MODE memory cycle may be either STATIC (ripple-through) or LATCHED, depending on user control ofthe Latch Input Signal

iL).

STATIC READ CYCLE

In the STATIC READ CYCLE mode of operation, the MK4118 provides a fast address ripple-through access of data from 8 of 8192 locations in the static storage array. Thus, the unique address specified by the 10 Address Inputs(An)definewhich 1 of 1024 bytes of data is to be accessed. The STATIC READ CYCLE is defined by WE

= L =

High.

A transition on any of the 10 address inputs will disable the 8 Data Output Drivers after tAZ. Valid Data will be available to the 8 Data Output Drivers within tAA after all address input signals are stable, and the data will be output under control of the Chip Select (CS) and Output Enable (OE) signals.

LATCHED READ CYCLE

The LATCHED READ CYCLE is also defined by the Write

Enable control input (WE) being in the high state, and it is synchronized by proper control of the Latch

iL)

input.

As the Latch control input

iL)

is taken low, Address (An) and Chip Select (CS) inputs that are stable for the specified set-up and hold times are latched internally.

Data out corresponding to the latched address will be supplied to the Data Output drivers. The output drivers will be enabled to drive the Output Data Bus under control of the Output Enable (OE) and latched Chip Select (CS) inputs.

Taking the latch input high begins another read cycle for the memory locations specified by the address then appearing on the Address Input (An). Returning the latch control to the low state latches the new Address and Chip Select inputs internally for the remainder of the LATCHED READ CYCLE.

NOTE: If the 'LATCH' function is not used pin 19 (T) must be tied high (VIH min).

WRITE MODE

The MK4118 is in the WRITE MODE whenever the Write Enable (WE) and Chip Select (CS) control inputs are in the low state. The status of the 8 output buffers during a write cycle is explained below.

159

WRITE MODE (Cont'd)

The WRITE cycle is initiated by the WE pulse going low provided that CS is also low. The leading edge of the WE pulse is used to latch the status ofthe address bus. CS if active (low) will also be latched. NOTE: WE is gated by CS. If ES' goes low after 'WE, the Write Cycle will be initiated by CS, and all timing will be referenced to that edge. CS and the Addresses will then be latched, and the cycle must be terminated by WE going high. The output bus if not already disabled will go to the high Z state tW11 after WE. The latch signal, if at a logic high, will have no impact on the WRITE cycle. If latch is brought from a logic high to low prior to WE going active then the address inputs and CS will be latched.

NOTE: The Latch control (T) will latch CS independent

of the state, whereas WE will latch CS only when in the low state. Once latched, ES' and the address inputs may be removed after the required hold times have been met.

Data in must be valid tDSW prior to the low-to-high transition ofWl:. The Data in lines must remain stable for tOHW after WE goes inactive. The write control of the MK4118 disables the data out buffers during the write cycle; however, output enable (O'E) should be used to disable the data out buffers to prevent bus contention between the input data and data that would be output upon completion of the write cycle.

CERAMIC DUAL-IN-LiNE HERMETIC PACKAGING (P)

24 PIN _ _ _ _ _ 1 20v' 015 _ _ _ _ -1

PLASTIC DUAL-IN LINE PACKAGING (N) 24 PIN

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010'002~~--FEATURES

o

Address Activated™ interface combines benefits of Edge Activated™ and fully static

o

High performance

The MK4801 uses Mostek's SCALED POLY 5™ process and advanced circuit design techniques to package 8192 bits of static RAM on a single chip comparable in size to previous 4K designs. Mostek's Address Activated™ circuit design technique is utilized to achieve high performance, low power, and easy user implementation. The device has a VIH

=

2.1 V, VIL

=

0.8V, VOH

=

2.4V, VOL

=

0.4V making it totally compatible with all TTL family devices.

The MK4801 is designed for all wide word high speed memory applications. The MK4801 presents the user a BLOCK DIAGRAM

o 24-pin - ROM/PROM compatible pin configuration

o

CS, OE, and LATCH functions for flexible system operation

high density cost effective alternative to bipolar and previous generation N-MOS fast memory. The 4801 features a fast CS (50% of Address Access) function to permit memory expansion without impacting system access time. A fast OE (50% of access time) is included to permit data interleaving for enhanced system performance. The MK4801 features a flexible latch function to permit latching of the address and CS status at the users option. The latch function may be bypassed by merely tying the latch pin to VCC. Common data and address bus operation may be performed at the system level by utilizing the MK4801 's

T

and OE functions.

Dans le document MEMORY DATA BOOK (Page 189-192)