The two programs ]KDCBO & ]KDDBO are desined to detect and report logic laults in the F·II MMU and FPP c11ip set (because part 01 the FP microcode is in the MMU chip). The program prints the total number 01 passes completed.
The test assumes that the basic CPU is laultless, to make sure run ]KDBDO CPU test.
OPERA TING PROCEDURES .R ]KDDBO
The program prints its name. and SWR = 000000 NEW
SWITCH SETTINGS :
SW15 = halt on error loop on current test inhibit all error type outs inhibit T·bit trapping inhibit iterations ring bell on error loop on error SW14=
SWI3=
SW12=
SWII = SWlO=
SW09=
SWOB=
SWOG=
SW05=
SW04=
SW03=
SW02=
loop on subtest specilied in SW <06:00>
selects subtest selects subtest selects subtes' selects subtest selects subtest
1·34
11/24 JKDEBO
11/24 CPU-BOARD M7133 GO-NOGO TEST ABSTRACT:
This program is a GO·NOGO test lor tlle PDP 11124 CPU board. It tests the CPU including EIS. the MMU. tlle FPP. the LTC and both SLU's. It does not contain the capabilities 01 scope looping. error recovery or printing 01 error in/ormation. Error halts do indicate wllich device lailed to allow the technician to determine which diagnostic to use to fix tile board or who; field replaceable unit may lix the board. The second SLU must have TURN·AROUND connector installed.
OPERA TING PROCEDURES
.R }KDEBO
II you want to change SWITCHES .
halt CPU. change loc 176. restart like @20OG.
The progrom just halts in case oj an error!
First pass runtime (worst case) 45 seconds SWITCH SETTINGS :
SWl5
=
not used SW07=
I not used SWOG= 1 not usedSW05
=
I program reserved· progrom will set if CIS chip present SW04=
1 inhibit testing oj SLU2SW03 == I inhibit testing oj LTC SW02== 1 inhibit testing oj SLUl SWOl=
SWOO=
inhibit testing FPP instruction set
inhibit testing oj memory management unit
11/24 JKDFBO
11/24 SLU & LTC (M7133) DIAGNOSTIC ABSTRACT:
This program tests both serial line units (SLU's) and the line time clock (LTC) on the CPU (M7133) module. Its main purpose is to provide scope looping lor repair personnel. Error type-outs identily a lunction being done and lailed and to what logical portion 01 the board it lailed on. The test needs a TURN-AROUND connector installed on SLU2.
OPERA TING PROCEDURES : .R ]KDFBO
This will start the test at 200 (normal start) Start address 204 will execute the ECHO test
An " ... is printed at the beginning 01 the test. The ECHO test reads a character Irom the terminal ,writes that character to the temlinal and reports any error.
Start address 210 is the terminal output test. Depressing any character at the terminal halts the test.
SWR = 000000 NEW SWITCH SETTINGS:
SW15
=
halt on error SW14=SWI3=
SW12=
scope loop
inhibit error typeout SWll= 1 not used
SW1O= 1 inhibit error l1ags test SW09= loop on error
SWOB= not used
SW07= disable SLU2 data test SWOG= inhibit LTC tests
SW05
=
inhibit all SLU tests (both SLUS) SW04=
inhibit SLUl testingSW03 = 1 inhibit SLU2 te::;ting
1·36
11/24 JKDHBO
KEfll-B CIS DIAGNOSTIC ABSTRACT:
Tllis program verilies tIle KEf'll-BA (CIS commercial instruction set) option with both memory management enabled and disabled. It allows the user to check out any combination 01 CIS chips. In virtually all cases, lault isolation is to the CIS chip level. The CIS option consists 01 six MOS-LSI control chips cOIi;oiiled iil three 40-pin hybrid carriers. .411 CIS instructions are chip partitioned, i. e. all the code lor a particular instruction is contained on a particular control c11ip. TIle exception is that all CIS instructions must pass throug the first CIS chip (control chip DC303-004) before reaching their destination chip. To run this test the first CIS chip (DC303-004) must be installed.
I have never seen the 3 40-pin llybrid chips separat, rather 1 have seen all 6 chips on one big ceramic hybrid.
OPERATING PROCEDURES
.R ]KDHBO
The test print : C]KDHBO KEf'll B CIS DIAGNOSTIC SWR = 000000 NEW
SWITCH SETTINGS :
SW15
=
1 halt on error SW14= I scope loopSW 13 = 1 inhibit error typeout SWI2= I not used
SWll=
SWlO=
SW09=
SW08=
inhibit subtest iteration not used
not used not used
SW07 = Mem. Management always disabled SW06 = Mem. Management always disabled SW05 = test CIS control chip 9 (DC303-009) SW04 = test CIS control chip 8 (DC303-008) SW03= test CIS control chip 7 (DC303-007) SW02
=
test CIS con trol chip 6 (DC303-006) SWOI=
test CIS control chip 5 (DC303-005) SWOO= I test CIS control chip 4 (DC303-004)if SW < 05:00> are all zero (delault mode) then the diagnostic will test all six CIS chips.
11/23 + JKDIBO
KDFlI-B SLU & LTC (M8189) DIAGNOSTIC ABSTRACT;
This program tests both :;erial line unit:; (SLU's) and the line time clock (LTC) on the CPU (M8189) module. Its main purpose i:; to provide scope looping lor repair personnel. Error type-outs identity a lunction being done and lailed and to what logical portion 01 the board it failed on. The test need:; a TURN-AROUND connector installed on SLU2.
OPERATING PROCEDURES;
.R ]KDIBo
This will start tIle te:;t at 200 (normal :;tart) Start address 204 will execute the ECHO te:;t
An "*,, is printed at the beginning 01 the te:;t. rIle f.'CIlO te:;t reads a character from the terminal ,write:; that character to the terminal and reports any error.
Start address 210 is the terminal output te:;t Depre:;:;ing any character at the terminal halts the te:;t
SWR
=
000000 NEW SWITCH SETTINGS :SW15= halt on elTor SW14 = scope loop
SW 13 = inhibit error typeout SW12=
not used
inhibit error 11ags te:;t loop on error
not used
disable SIU2 data te:;t inhibit LTC tests SWll=
SWlO=
SW09=
SWD8=
SWD7=
SW06=
SWD5=
SWD4=
SW03=
inhibit all SLU te:;ts (both SLUS) inhibit SLUI te:;ting
inhibit SLU2 te:;ting
.-3U
11/23 + .JKDJBO
information. Error halts do indicate wllich device Jailed to allow the technician to determine which diagnostic to use to fix the board or what field replaceable unit may fix tlle board. The second SLU must have tum around connector installed. This program is set to do minimum testing unless action is taken via the SoJtware switcll register (memory loco 176). Bits 1. 6. 7-10 have been set up such that the program will bypass certain tests unless the switch register bit is set.error reporting looks like
"FAILED DURING CPU TESTS"
SWITCH SETTINGS : test parity error detection use the Q22-BUSEXER
inhibit testing oj memory management unit