IAPX 286 BASE ARCHITECTURE

2.5.2 Memory-Mapped 1/0

I/O devices also may be placed in the iAPX 286 memory address space. So long as the devices respond like memory components, they are indistinguishable to the processor.

Memory-mapped I/O provides additional programming flexibility. Any instruction that references memory may be used to access an I/O port located in the memory space. For example, the MOV instruction can transfer data between any register and a port; and the AND, OR, and TEST instructions may be used to manipulate bits in the internal regis-ters of a device (see figure 2-14). Memory-mapped I/O performed via the full instruc-tion set maintains the full complement of addressing modes for selecting the desired I/O device.

Memory-mapped I/O, like any other memory reference, is subject to access protection and control when executing in protected mode.

2.6 INTERRUPTS AND EXCEPTIONS The iAPX 286 architecture supports several mechanisms for interrupting program

execu-MEMORY ADDRESS SPACE

tion. Internal interrupts are synchronous events that are the responses of the CPU to certain events detected during the execution of an instruction. External intenupts are asynchronous events typically triggered by external devices needing attention. The iAPX 286 supports both mask able (controlled by the IF flag) and non-maskable interrupts. They cause the processor to temporarily suspend its present program execution in order to service the requesting device. The major distinction between these two kinds of interrupts is their origin: an internal interrupt is always repro-ducible by re-executing with the program and data that caused the interrupt, whereas an external interrupt is generally independent of the currently executing task.

Interrupts 0-31 are reserved by Intel.

Application programmers will normally not be concerned with servicing external interrupts.

More information on external interrupts for system programmers may be found in Chapter 5, section 5.2, "Interrupt Handling for Real Address Mode," and in Chapter 9, "Inter-rupts, Traps and Faults for Protected Virtual Address Mode."

I 0 DEVICE 1

INTERNAL REGISTER

~-~====== ~IL.- __

I 0 DEVICE 2

INTERNAL REGISTER

....

--~I-- = ^{= = = = ~L...I}

Figure 2·14. Memory-Mapped 1/0

iAPX 286 BASE ARCHITECTURE

Table 2-4. iAPX 286 Interrupt Vector Assignments (Real Address Mode)

Interupt Function

Number

Divide error exception 0

Single step interrupt 1

NMI interrupt 2

Breakpoint interrupt 3

INTO detected overflow exception 4 BOUND range exceeded exception 5

Invalid opcode exception 6

Processor extension not available exception 7 Interrupt table limit too small exception 8

Processor extension segment overrun 9 interrupt

Reserved 10-12

Segment overrun exception 13

Reserved 14, 15

Processor extension error interrupt 16

Reserved 17-31

User defined 32-255

In Real Address Mode, the application programmer is affected by two kinds of inter-nal interrupts. (Interinter-nal interrupts are the

2-24

Related Return Address Before Instruction Instructions

Causing Exception?

DIV,IDIV Yes

All All INT

INTO No

BOUND Yes

Any undefined Yes

opcode

ESC or WAIT Yes

INT vector is not Yes within table limit

ESC with memory No

operand extending beyond offset FFFF(H)

Word memory Yes

reference with offset = FFFF(H) or an attempt to execute past the end of a segment

ESC or WAIT

result of executing an instruction which causes the interrupt.) One type of interrupt is called an exception because the interrupt only occurs

if a particular fault condition exists. The other type of interrupt generates the interrupt every time the instruction is executed.

The exceptions are: divide error, INTO detected overflow, bounds check, segment overrun, invalid operation code, and proces-sor extension error (see table 2-4). A divide error exception results when the instructions DIY or IDlY are executed with a zero denominator; otherwise, the quotient will be too large for the destination operand (see section 3.3.4 for a discussion of DIY and IDlY). An overflow exception results when the INTO instruction is executed and the OF flag is set (after an arithmetic operation that set the overflow (OF) flag). (See section 3.6.3,

"Software Generated Interrupts," for a discussion of INTO.) A bounds check excep-tion results when the BOUND instrucexcep-tion is executed and the array index it checks falls outside the bounds of the array. (See section 4.2 for a discussion of the BOUND instruc-tion.) The segment overrun exception occurs when a word memory reference is attempted which extends beyond the end of a segment.

An invalid operation code exception occurs if an attempt is made to execute an undefined instruction operation code. A processor

extension error is generated when a processor extension detects an illegal operation. Refer to Chapter 5 for a more complete description of these exception conditions.

The instruction INT generates an internal interrupt whenever it is executed. The effects of this interrupt (and the effects of all inter-rupts) is determined by the interrupt handler routines provided by the application program or as part of the system software (provided by system programmers). See Chapter 5 for more on this topic. The INT instruction itself is discussed in section 3.6.3.

In Protected Mode, many more fault condi-tions are detected and result in internal inter-rupts. Protected Mode interrupts and faults are discussed in Chapter 10.

2.7 HIERARCHY OF INSTRUCTION SETS For descriptive purposes, the iAPX 286 instruction set is partitioned into three distinct subsets: the Basic Instruction Set, the Extended Instruction Set, and the System Control Instruction Set. The "hierarchy" of instruction sets defined by this partitioning helps to clarify the relationships between the various processors in the iAPX 86 family (see figure 2-15).

Figure 2-15. Hierachy of Instructions