High Speed CMOS Electrically Erasable PROM

PRELIMINARY DATA SHEET

• 10,000 Cycles/Byte Minimum

• 10 Year Data Retention

• On-Chip Timer and Latches

• Automatic Byte Erase Before Write

• Fast Byte Write: 5 ms/Byte

• High Speed Address/Data Latching

• 50 ms Chip Erase

• 5 V

±

• Power Up/Down Protection Circuitry

• DATA Polling of Data Bit 7

• JEDEC Approved Byte Wide Pinout

• 38C16: 2816A Pin Compatible

• 38C32: 28C64 Pin Compatible

• Military and Extended Temperature Range Available.

Pin Names

Ao-A3 ADDRESSES - COLUMN A4_Al1[1[ ROW ADDRESSES

CE CHIP ENABLE

SEEQ's 3BC16/32 are high speed 2Kx B/4Kx B Elec-trically Erasable Programmable Read Only Memories (EEPROM), manufactured using SEEQ's advanced 1_ 25 micron CMOS process_

The 3BC16/32 are ideal for high speed applications which require non-volatility and in-system reprogram-mability. The endurance, the number of times a byte may be written, is specified at 10,000 cycles per byte minimum. The high endurance is accomplished using

A7

PLASTIC LEADED CHIP CARRIER TOPVIEW

cations where writes are frequent is increased because of the DO-cell. The 35 ns maximum access time meets the requirements of many of today's high performance processors. The 38C16132 have an internal timer which automatically times out the write time. The on-chip timer, along with the input latches, frees the microprocessor for other tasks during the write time.

DATA polling can be used to determine the end of a write cycle. All inputs are TTL compatible for both write and read modes.

Data retention is specified to be greater than 10 years.

The 38C16 and 38C32 are both available in CERAMIC DIP, PLASTIC DIPand PLCCpackages.

24 pin versions of both 38C16 and 38C32 intended for bipolar PROM replacement are also available (36C16/36C32). All parts are available in commer-cial as well as military temperature ranges.

Device Operation

A read is started by presenting the addresses of the desired byte to the address inputs. Once the address is stable, CE is brought to a TTL low in order to enable the chip. The WE pin must be at a TTL high during the entire read cycle. The output drivers are made active by bringing output enable (OE) to a TTL low. DurJng read, the address, CE, OE, and I/O latches are transparent.

NOTES:

1. Chip erase is an optional mode.

2. VH - High Voltage.

Write

To write into a particularlocation, addresses must be valid and a TTL low is applied to the write ena-ble (WE) pin of a selected (CE low) device. This initiates a write cycle. During a write cycle, all inputs except for data are latched on the falling edge of WE (or CE, whichever one occurred last).

Write enable needs to be at a TTL low only for the specified twp time. Data is latched on the rising edge of WE (or CE, which ever one occurred first).

An automatic byte erase is performed before data is written.

DATA Polling

The EEPROM has

a

a

a

During the internal write cycle, the complement of the data bit 7 is presented at output 7 when a read is performed. Once the write cycle is finished, the true data is presented at the outputs. A software routine can be used to "poll", i.e. read the output, for true or complemented data bit 7. The polling cycle specifications are the same as for a read cycle. During data polling, the addresses are don't care.

Chip Erase

Certain applications may require all bytes to be erased simultaneously. This feature, which requires high voltage, is optional and timing specifications are available from SEEQ.

Power Up/Down Considerations

Protection against false write during Vee power up/down is provided through on chip circuitry.

Writing is prevented under anyone of the following conditions:

1. Vee is less than VW1 V. _

1. A high to low Write Enable (WE) transition has not occurred when the Vee supply is between VW1 V and Vee with CE low and OE high.

Absolute Maximum Rating

Temperature

Storage . . . .. - 65°e to + 150⁰e Under Bias. . . . .. - 10⁰

e

e

All Inputs and Outputs

with Respect to Ground . . . .. -3. V to + 7 V D.

e.

Recommended Operating Conditions

38C16 38C32

I

I

Endurance and Data Retention

Symb()1 Parameter Value

N Minimum Endurance 10,000

TOR Data Retention >10

38C16/38C32

PRELIMINARY DATA SHEET

COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Units Condition

Cycles/Byte M I L-STD 883 Test Method 1033 Years MIL-STD 883 Test

Method 1008

DC Operating Characteristics

Symbol Parameter Min. Max. Unit Test Condition

CE=OE=VIL;

Icc Vee Active Current 80 mA Address Inputs = 20M Hz

1/0=OmA CE=VIH;

ISB Standby Vee Current 40 mA All 1/0 open;

All other inputs TTL don't care;

liN Input Leakage Current 1 pA 0.1V> =VIN< = Vee Max.

lOUT Output Leakage Current 10 pA VouT=Vee Max.

VIL Input Low Voltage -0.5 0.8 V

VIH Input High Voltage 2 6.5 V Vee Min.

VOL Output Low Voltage 0.45 V IOL = 2.1 mA, Vee = Vee Min.

VOH Output High Voltage 2.4 V IOH = - 400 pA, Vce Min.

VWI^[1] Write Inhibit Voltage 3.8 V

VeL^[1] Input Undershoot Voltage -3 V VIN undershoot pulse width < 10ns

NOTES:

1. Characterized. Not tested.

'--- SeeQ

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MD4000291B 1-79