Obtained STD]
Explanation:
~ The appropriate ALD is obtained:
~ When P in the ALET is zero (and the ALET is not zero or one), the DUALD in the DUCT is obtained.
When P in the ALET is one, the PSALD in the primary ASTE is obtained.
r.J 2
Information, which may include the ALD-source origin, ALET, ALO, and EAX, is used to search
LJ
the ALB. This information, along with information from the ALE, ASTE, and ATE, may be placed in the ALB.r:l
The appropriate STD is obtained:~ When the ALET is zero, the PSTD in CR 1 is obtained.
When the ALET is one, the SSTD in CR 7 is obtained.
When the ALET is larger than one:
If a match exists, the STD from the ALB is used.
If no match exists, tables from real storage are fetched. The resulting STD from the ASTE ;s obtained, and entries may be formed in the ALB.
Figure 5-9. Access-Register Translation
Chapter 5. Program Execution
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Selecting the Access-List-Entry Token When one of access registers 1-15 is designated, or for the access register designated by the R 1 field of TEST ACCESS, access-register translation uses the access-list-entry token (ALET) that is in the access register. When access register 0 is designated, except for TEST ACCESS, an ALET having the value 00000000 hex is used, and the contents of access register 0 are not examined.
Obtaining the Primary or Secondary Segment-Table Designation
When the ALET being translated is 00000000 hex, the primary segment-table designation in control register 1 is obtained. When the ALET is 00000001 hex, the secondary segment-table designation in control register 7 is obtained. In each of these two cases, access-register translation is completed.
Checking the First Byte of the ALET When the ALET being translated is other than 00000000 or 00000001 hex, bits 0-6 of the ALET are checked for being all zeros. If bits 0-6 are not all zeros, an ALET-specification exception is recog-nized, and the operation is suppressed.
Obtaining the Effective Access-List Designation
The primary-list bit, bit 7, in the ALET is used to perform a lookup to obtain the effective access-list designation. When· bit 7 is zero, the effective ALD is the dispatchable-unit ALD located in bytes 16-19 of the dispatchable-unit control table (DUCT).
When bit 7 is one, the effective ALD is the primary-space ALD located in bytes 16-19 of the primary ASN-second-table entry (primary ASTE).
When bit 7 is zero, the real address of the dispatchable-unit ALD is obtained by appending six zeros on the right to the DUCT origin, bits 1-25 of control register 2, and adding 16. The addition cannot cause a carry into bit position O. The result is a 3 I-bit real address.
When bit 7 is one, the real address of the primary-space ALD is obtained by appending six zeros on the right to the primary-ASTE origin, bits 1-25 of control register 5, and adding 16. The addition cannot cause a carry into bit position O. The result is a 3l-bit real address.
The obtained 3l-bit real address is used to fetch the effective ALD -- either the dispatchable-unit ALD or the primary-space ALD, depending on bit 7 of the ALET. The fetch of the effective ALD appears to be 5-44 ESAj370 Principles of Operation
word-concurrent, as observed by other CPUs, and is not subject to protection. When the storage address that is generated for fetching the effective ALD refers to a location which is not available in the configuration, an addressing exception is recog-nized, and the operation is suppressed. When the primary-space ALD is fetched, bit 0, the ASX-invalid bit, and bits 30, 31, and 60-63 in the primary ASTE are ignored.
Access-List Lookup
A lookup in the effective access list is performed.
The effective access list is the dispatchable-unit access list if bit 7 of the ALET is zero, or it is the primary -space access list if bit 7 is one.
The access-list-entry-number (ALEN) portion of the ALET is used to select an entry in the effective access list. If the format-O ALD is implemented, the real address of the access-list entry is obtained by appending seven zeros on the right to bits 1-24 of the effective ALD and adding the ALEN to this value. If the format-l ALD is implemented, the real address of the access-list entry is obtained by appending eight zeros on the right to bits 1-23 of the effective ALD and adding the ALEN to this value. For these additions, the ALEN is extended with four rightmost zeros and II leftmost zeros. In either case, a carry, if any, into bit position 0 is ignored, and the result is a 31-bit real address.
As part of the access-list-lookup process if the format-O ALD is implemented, the leftmost 13 bits of the ALEN are compared against the effective access-list length, bits 25-31 of the effective ALD, to establish whether the addressed entry is within the access list. For this comparison, the access-list length is extended with six leftmost zeros. If the value formed from the access-list length is less than the value in the 13 leftmost bits of the ALEN, an ALEN-translation exception is recognized, and the operation is nullified. If the format-l ALD is imple-mented, the leftmost 12 bits of the ALEN are com-pared against bits 24-31 of the effective ALD. For this comparison, the access-list length is extended with four leftmost zeros. If the value formed from the access-list length is less than the value in the 12 leftmost bits of the ALEN, an ALEN-translation exception is recognized, and the operation is nulli-fied.
The 16-byte access-list entry is fetched by using the real address. The fetch of the entry appears to be word-concurrent as observed by other cpus, with the leftmost word fetched frrst. The order in which
the remaining three words are fetched is unpredict-able. The fetch access is not subject to protection.
When the storage address that is generated for fetching the access-list entry refers to a location which is not available in the configuration, an addressing exception is recognized, and the opera-tion is suppressed.
Bit 0 of the access-list entry indicates whether the access-list entry specifies an address space by desig-nating an ASN-second-table entry. This bit is inspected, and, if it is one, an ALEN-translation exception is recognized, and the operation is nulli-fied.
When bit 0 is zero, the access-list-entry sequence number (ALESN) in bit positions 8-15 of the access-list entry is compared against the ALES N in the ALET to determine whether the ALET designates the conceptually correct access-list entry. Inequality causes an ALE-sequence exception to be recognized and the operation to be nullified.
Locating the ASN-Second-Table Entry The ASN-second-table-entry (ASTE) address in the access-list entry is used to locate the ASTE. Bits 65-89 of the access-list entry, with six zeros appended on the right, fonn the 31-bit real address of the ASTE.
The 64-byte ASTE is fetched by using the real address. The fetch of the entry appears to be word-concurrent as observed by other cpus, with the left-most word fetched frrst. The order in which the remaining words are fetched is unpredictable. The fetch access is not subject to protection. When the storage address that is generated for fetching the ASTE refers to a location which is not available in the configuration, an addressing exception is recog-nized, and the operation is suppressed.
Bit 0 of the ASTE indicates whether the ASTE speci-fies an address space. This bit is inspected, and, if it is one, an ASTE-validity exception is recognized, and the operation is nullified.
When bit 0 is zero, the ASTE sequence number (ASTESN) in bit positions 160-191 of the ASTE is compared against the ASTESN in bit positions 96-127 of the access-list entry to determine whether the addressing capability represented by the access-list entry has been revoked. Inequality causes an ASTE-sequence exception to be recognized and the operation to be nullified.
Authorizing the Use of the Access-List Entry
The private bit, bit 7, in the access-list entry is used to determine whether the program is authorized to use the access-list entry. The access-list-entry authorization index (ALEAX) in bit positions 16-31 of the access-list entry, the extended authorization index (EAX) in bit positions 0-15 of control register 8, and the authority table designated by the ASTE may also be used.
When the private bit is zero, the program is author-ized, and the authorization step of access-register translation is completed.
When the private bit is one but the ALEAX is equal to the EAX, the program is authorized, and the authorization step of access-register translation is completed.
When the private bit is one and the ALEAX is not equal to the EAX, bits 30,31, and 60-63 of the ASTE must be zeros; otherwise, an ASN-translation-specification exception is recognized, and the opera-tion is suppressed.
When the private bit is one and the ALEAX is not equal to the EAX, a process called the extended-authorization process is perfonned. Extended authorization uses the EAX to select an entry in the authority table designated by the ASTE, and it tests the secondary -authority bit in the selected entry for being one. The program is authorized if the tested bit is one.
Extended authorization is the same as the sec-ondary-AsN-authorization process described in the section "ASN Authorization" in Chapter 3,
"Storage," except as follows:
• The EAX in control register 8 is used instead of the authorization index (AX) in control register 4.
• When the value in bit positions 0-11 of the EAX is greater than the authority-table length (ATL) in the ASTE, an extended-authority excep-tion is recognized instead of a secondary-authority exception. The operation is nullified if the extended-authority exception is recog-nized.
When the private bit is one, the ALEAX is not equal to the EAX, and the secondary bit in the authority-table entry selected by the EAX is not one, an extended-authority exception is recognized, and the operation is nullified.
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Obtaining the Segment-Table
Designation from the ASN-Second-Table Entry
When the ALET being translated is other than 00000000 . or 0000000 I hex and no exception is recognized in the steps described above, access-register translation obtains the segment-table desig-nation from bit positions 65-95 of the ASTE. Bit 64 of the ASTE, the space-switch-event control, is ignored.
Recognition of Exceptions During Access-Register Translation
The exceptions which can be encountered during the access-register-translation process and their pri-0rity are shown in the section "Access Exceptions"
in Chapter 6, "Interruptions."
Programming Note: When updating an access-list entry or ASN -second-table entry, the program should change the entry from invalid to valid (set bit 0 of the entry to zero) as the last step of the updating. This ensures, because the leftmost word is fetched fIrst, that words of a partially updated entry will not be fetched.