fcmpu (Floating Compare Unordered) Instruction
Purpose
Compares the contents of two Floating Point registers.
Syntax
fcmpu BF,FRA,FRB
63 BF
I II I
FRAFRB o
o 6 9 11 16 21 31
Description
The fcmpu instruction compares the 64-bit double precision floating point operand in Floating Point Register FRA to the 64-bit double precision floating point operand in Floating Point Register FRB. The Floating Point Condition Code Field (FPCC) of the Floating Point Status and Control Register (FPSCR) is set to reflect the value of the operand FRA with respect to operand FRB. The value BF determines which field in the Condition Register receives the four FPCC bits.
• If one of the operands is either a Quiet NaN or a Signaling NaN, the Floating Point Condition Code is set to reflect unordered (FU).
• If one of the operands is a Signaling NaN, then the Floating Point Invalid Operation Exception bit VXSNAN of the Floating Point Status and Control Register is set.
The fcmpu instruction has one syntax form and always affects the FT, FG, FE and FU and VXSNAN bits in the Floating Point Status and Control Register (FPSCR).
Parameters
Examples
BF Specifies field in the Condition Register that receives the four FPCC bits.
FRA Specifies source Floating Point register.
FRB Specifies source Floating Point register.
1. To compare the contents of FPR 5 and FPR 4:
# Assume FPR 5 holds OxC053 4000 0000 0000.
# Assume FPR 4 holds Ox400C 0000 0000 0000.
# Assume CR
=
0 and FPSCR=
O.fcmpu 6,4,5
# CR now contains OxOOOO 0040.
# FPSCR now contains OxOOOO 4000.
Chapter 5. Instruction Set
5-71
fcmpu
Implementation Specifics
This instruction is part of Application Development Toolkit in AIX Base.
Related Information
Understanding Floating Point Compare Instructions on page 1-14.
5-72
Assembler Language Referencefd
fd (Floating Divide) Instruction
Purpose Syntax
Divides one 64-bit double precision floating point operand by another.
fd
The fd instruction divides the 64-bit double precision floating point operand in Floating Point Register FRA by the 64-bit double precision floating point operand in Floating Point Register FRB. No remainder is preserved. The result is rounded under control of the Floating Point Rounding Control Field RN of the Floating Point Status and Control Register (FPSCR) and is placed in the target Floating Point register FRT.
The floating point division operation is based on exponent subtraction and division of the two sig n ificands.
• If an operand is a denormalized number, then it is prenormalized before the operation is begun.
The Floating Point Result Flags field of the Floating Point Status and Control Register is set to the class and sign of the result except for Invalid Operation Exceptions when the Floating Point Invalid Operation Exception Enable bit is 1.
The fd instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.
Syntax Floating Point Status and Record Condition
form Control Register bit (Rc) Register Field 1
fd C,FL,FG,FE,FU,FR,FI,OX,UX, 0 None
ZX,XX,VXSNAN,VXIDI,VXZDZ
fd. C,FL,FG,FE,FU,FR,FI,OX,UX, FX,FEX,VX,OX
ZX,XX,VXSNAN,VXIDI,VXZDZ
The two syntax forms of the fd instruction always affect the Floating Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating Point Exception (FX), Floating Point Enabled Exception (FEX), Floating Point Invalid Operation Exception (VX), and Floating Point Overflow Exception (OX) bits in Condition Register Field 1.
Chapter 5. Instruction Set
5-73
fd
Parameters
Examples
FRT Specifies target Floating Point register for operation.
FRA Specifies source Floating Point register containing the dividend.
FRB Specifies source Floating Point register containing the divisor.
1. To divide the contents of FPR 4 by the contents of FPR 5, place the result in FPR 6, and set the Floating Point Status and Control Register to reflect the result of the operation:
# Assume FPR 4 contains OxC053 4000 0000 0000.
# Assume FPR 5 contains Ox400C 0000 0000 0000.
# Assume RM
=
0 and FPSCR=
O.£d 6,4,5
# FPR 6 now contains OxC036 0000 0000 0000.
# FPSCR now contains OxOOOO 8000.
2. To divide the contents of FPR 4 by the contents of FPR 5, place the result in FPR 6, and set Condition Register Field 1 and the Floating Point Status and Control Register to reflect the result of the operation:
# Assume FPR 4 contains OxC053 4000 0000 0000.
# Assume FPR 5 contains Ox400C 0000 0000 0000.
# Assume RM
=
0 and FPSCR=
O.£d. 6,4,5
# FPR 6 now contains OxC036 0000 0000 0000.
# FPSCR now contains OxOOOO 8000.
# CR contains OxOOOO 0000.
Implementation Specifics
This instruction is part of Application Development Toolkit in AIX Base.
Related Information
Understanding Floating Point Arithmetic Instructions on page 1-14.
Understanding The Floating Point Status and Control Register on page 1-12.
5-74
Assembler Language Referencefm
fm (Floating Multiply) Instruction
Purpose Syntax
Multiplies two 64-bit double precision floating point operands.
fm
The fm instruction multiplies the 64-bit double precision floating point operand in Floating Point Register FRA by the 64-bit double precision floating point operand in Floating Point Register FRC. The result is rounded under control of the Floating Point Rounding Control Field RN of the Floating Point Status and Control Register and is placed in the target Floating Point Register FRT.
Multiplication of two floating point numbers is based on exponent addition and multiplication of the two significands.
• If an operand is a denormalized number then it is prenormalized before the operation is begun.
The Floating Point Result Flags field of the Floating Point Status and Control Register is set to the class and sign of the result except for Invalid Operation Exceptions when the Floating Point Invalid Operation Exception Enable bit is 1.
The fm instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.
Syntax Floating Point Status and Record Condition
form Control Register bit (Rc) Reg ister Field 1
fm C,FL,FG,FE,FU,FR,FI,OX,UX, 0 None
XX,VXSNAN,VXIMZ
fm. C,FL,FG,FE,FU,FR,FI,QX,UX, FX,FEX,VX,OX
XX,VXSNAN,VXIMZ
The two syntax forms of the fm instruction always affect the Floating Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating Point Exception (FX), Floating Point Enabled Exception (FEX), Floating Point Invalid Operation Exception (VX), and Floating Point Overflow Exception (OX) bits in Condition Register Field 1.
Chapter 5. Instruction Set
5-75
fm
Parameters
Examples
FRT Specifies target Floating Point register for operation.
FRA Specifies source Floating Point register for operation.
FRC Specifies source Floating Point register for operation.
1. To multiply the contents of FPR 4 and FPR 5, place the result in FPR 6, and set the Floating Point Status and Control Register to reflect the result of the operation:
# Assume FPR 4 contains OxC053 4000 0000 0000.
# Assume FPR 5 contains Ox400C 0000 0000 0000.
# Assume RM
=
0 and FPSCR=
O.fm 6,4,5
# FPR 6 now contains OxC070 D800 0000 0000.
# FPSCR now contains OxOOOO 8000.
2. To multiply the contents of FPR 4 and FPR 25, place the result in FPR 6, and set Condition Register Field 1 and the Floating Point Status and Control Register to reflect the result of the operation:
# Assume FPR 4 contains OxC053 4000 0000 0000.
# Assume FPR 25 contains OxFFFF FFFF FFFF FFFF.
# Assume RM
=
0, FPSCR=
0, and CR=
O.fm. 6,4,25
# FPR 6 now contains OxFFFF FFFF FFFF FFFF.
# FPSCR now contains Ox0001 1000.
# CR now contains OxOOOO 0000.
Implementation Specifics
This instruction is part of Application Development Toolkit in AIX Base.
Related Information
Understanding Floating Point Arithmetic Instructions on page 1-14.
Understanding The Floating Point Status and Control Register on page 1-12.