ENTERING CHANNEL INFORMATION INTO THE RAM

The on-board channel-list is 8-bits wide to allow the user to select anyone of 64 channels (0 to 63) which requires a 6-bit -field, and associate with that channel a code for the programmable gain amplifier (PGH

=

1,2,4,8) which requires a 2-bit field. An 8-bit entry in the channel-list is organized as indicated in Figure 7-1:

MSB LSB

4 3 2

I ^I

PG Bits Selects One of 64 Channels

FIGURE 7-1: FORMAT OF CHANNEL-LIST ENTRIES

The bits select one of four possible gains. If a PG option is not installed, these bits are ignored. Gain selection is done according to Table 7-1.

CHANNEL-LIST PROGRAMMING

ENTERING CHANNEL INFORMATION INTO THE RAM

TABLE 7-1: CHANNEL-LIST GAIN SELECTION PG BIT 7 PG BIT 6 PGH GAIN

0 0 1

0 1 2

1 0 4

1 1 8

I

Each page of the channel-list is independent of the other three. Each has to be individually programmed by the user to the required sampling scheme. During actual conversion operations, only one of the four pages as selected by the two-bit field of the ADCSR is accessed through the pointer logic. The user can program and read back for verification the contents of the channel-list RAM by following the programming sequence given in the ensuing two sections.

7.3.1 WRITING INTO THE CHANNEL-LIST RAM

Following initialization, you must first select which one of four pages in the channel-list is to be operated on by writing a two bit naae select code into bits 2 and 1 of rhp Anr.~R_

Then the c~a~nel~lisf p~i~ter-io~i~-m~st-~; s;t ~~ t~~-re~~i~;~

starting address and be told of the desired ending address.

The pointer logic points to the first location in RAM that is to be loaded. The RAM accepts data for entry in the following manner:

1. Write a 005 into the high byte of the ADCSR.

2. Write the sequence of channel numbers into the low byte of the CLPR.

Note that the pointer will be incremented after each write operation to the low byte of the CLPR. Thus sequential writes to the low byte of the CLPR will place data sequentially in the channel-list. This incrementing operation will proceed until the value of the pointer becomes equal to the value held in the final address register. A write operation performed after this condition will set the pointer back to its initial value and the channel-list buffer will be overwritten.

programming sequence:

CHANNEL-LIST PROGRAMMINC ENTERING CHANNEL INFORMATION INTO THE RA~

MOV #2400, @#ADCSR MOVB #1, @#CLPR MOVB #3, @#CLPR MOVB ~ @#CLPR MOVB #7, @#CLPR

This example selects page 0 of the RAM and forces a list programming operation. Then the odd channel numbers are stored sequentially into the channel-list.

7.3.2 READING THE CHANNEL-LIST RAM

For diagnostic testing, and verification purposes the contents of the channel-list RAM may have to be read. To perform read operations the program must first set the pointer logic to the desired starting address and specify the required final address. Then the following sequence is required:

1. Write 004 into the high byte of the ADCSR.

2. Read the channel-list entries successively from the CLPR low byte. Note that when the CLPR is read in this mode, for diagnostic purposes, the high byte of the register will contain the address of the channel-list entry that is being read while the low byte will contain the contents. The pointer will be incremented after each read operation.

Hence successive reads will allow the program to read successive entries of the RAM. The pointer logic is active during this operation. Therefore, when the pointer increments to the final address register, it will be reset back to the starting address.

programming sequence:

MOV #2000, @#ADCSR MOV @#CLPR, RO MOV @#CLPR, RI MOV @#CLPR, R2

CHANNEL-LIST PROGRAMMING

ENTERING CHANNEL INFORMATION INTO THE RAM

This example selects page

a

^{for readback purposes and then}

takes three successive entries from the list and places them in registers RO, R1, and R2.

7.3.3 MULTIPLEXER PRELOAD AND LOGIC ENABLE

After the pointer logic has been programmed and the Channel-list RAM has been loaded with appropriate data the program must set the pointer logic for an active cycle. Part of this activation involves issuing a load command to the actual multiplexer and then enabling the logic for AID conversion operations. The following sequence is required for this:

1. Write 006 to the high byte of the ADCSR.

2. Perform a write operation to the low byte of the CLPR.

Note that the data written is not critical as only the write operation is required.

3. Write 000 to the high byte of the ADCSR

Programming sequence:

MOVB #6, @#ADCSR + 1 MOVB fO; ^@#CLPR

MOVB #0, @#ADCSR + 1

After this operation you must access only bits 14 and 15 of the high byte of the ADCSR to ensure that the channel-list is not disturbed.

CHAPTER 8

PROGRAMMING EXAMPLES

8.1 INTRODUCTION

This chapter presents five programs that describe how the DT3362 series board should be programmed for certain non-DMA operations or DMA transfers via the Q-bus. The programs are not intended to solve any particular application problem but have been written such that key programming issues are demonstrated. Programs 1 and 2 illustrate non-DMA operations, while programs 2, 3, and 5 illustrate DMA transfer operations.

A brief summary precedes the listing of each program. All example programs have been written as subroutines so that you can test them by calling them from your main program. Note again that these example programs are given for illustration only and should not be used for diagnostics.

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