PARAMETER TEST CONDITIONS MIN Typt MAX UNIT
VOH High-level output voltage 10H = -150 /lA, VCC = 4.75 V 2.2 V
VOL low-level output voltage IOl = 2 mA, VCC = 5.25 V 0.45 V
II Input current VI = 0 to 5.25 V ±10 /lA
10ZH
Off-state output current, high-level
CE at 2.2 V,
voltage applied VO=4V 15 /lA
Off-state output current, low-level
-Vo = 0.45 V -50 /lA
IOZl
voltage applied CE at 2.2 V,
VCC = 5.25 V,
I
TA = 25°C 60ICC Supply current from VCC mA
10 = 0 mA
1
TA = O°C 70Ci Input capacitance VI = 0 V,
f= 1 MHz
TA = 25°C,
4 8 pF
Co Output capacitance Va = 0 V, TA = 25°C,
10 15 pF
f= 1 MHz t All tYpical values are at Vce = 5 V, T A = 25°C.
TEXAS INSTRUMENTS
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POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
II
67
II
68
TMS 4043 JL. NL; TMS 4043-1 JL, NL; TMS 4043-2 JL. NL 256-WORD BY 4-BIT STATIC RANDOM-ACCESS MEMORIES
switching characteristics over recommended supply voltage range, T A = O°C to 70°C, 1 Series 74 TTL load, CL = 100 pF
TMS4043 TMS 4043-1 TMS 4043-2
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta(ad) Access time from address 1000 650 450 ns
ta(cr) Access time from chip enable 800 500 350 ns
tOV(ad) Previous output data valid after address change 40 40 40 ns
tpxz Output disable time from chip enable (see Note 3) 0 200 0 150 0 150 ns
tpxz Output disable time from read/write (see Note 3) 200 200 200 ns
NOTE 3: This parameter defines the delay for the I/O bus to enter the input mode.
read cycle timing
ADDRESS,AO-A7
~I~·_~-_-_-_-_-_-_-_-_-_-_~-_-_-_-_-_-_-_t_c_(rd_)
__---~~I
--w
ADDRESS VALID\if
-.i0
J1''----I I
CHIP ENABLE, CE
<X><XXX><A
ztOO<XXX)"""""~'--"-j.--
ta(CE)--.J
tDV(!dlI.. ~I
INPUT/OUTPUT,I/01-1/04
I I
I"
ta(adl---I~~I r--
tpxz-+I
---...:.I---l~
DATA VALID>--write cycle timing
ADDRESS, AO-A7
I..
tc(wr) ~I---~~~II
/ . \'-______________________________________
ADDRESS VALID~~II .1:\
'-______ _READ/WRITE, R/W
CHIP ENABLE, CE
INPUT/OUTPUT,I/01-1/04
I
j+- tsuldal-JI.. ~Ltpxz I+---
thldal--.j\/V\/VVVV\l\lW ~
~ DATA VALID .~
NOT E: For measuring timing requirements and characteristics, VI H = 2.2 V, V I L = 0.65 V, tr = tf = 20 ns and all timing points are 50% points.
TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
PRINTED IN U.S A 57E
TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.
575
MOS LSI
TMS 4050 Jl, Nl; TMS 4050-1 Jl, Nl; TMS 4050-2 Jl, Nl 4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
• 4096 x 1 Organization
• 18-Pin 300-Mil Package Configuration
• Multiplexed Data Input/Output
BULLETIN NO. DL-S 7512242, FEBRUARY 1975-REVISED MAY 1975
18-PIN CERAMIC AND PLASTIC DUAL-IN-L1NE PACKAGES
(Top VIEW)
• 3 Performance Ranges:
READ, vBB 18 VSS
READ OR MODIFY
ACCESS WRITE WRITE I/O 17 A11
TIME CYCLE CYCLE
(MAX) (MIN) (MIN) AO 16 A10
TMS 4050 300 ns 470 ns 730 ns A1 15 A9
TMS 4050-1 250 ns 430 ns 660 ns
TMS 4050-2 200 ns 400 ns 600 ns A2 14 A8
• Full TTL Compatibility on All Inputs
(No Pull-up Resistors Needed)
R/W 13 A7• Registers for Addresses Provided on Chip
CE 12 A6• Open-Drain Output Buffer
• Single Low-Capacitance Clock
A3 11 A5• Low-Power Dissipation
A4 10 V DD
- 420 mW Operating (Typical) - 0.1 mW Standby (Typical)
• N-Channel Silicon-Gate Technology description
The TMS 4050 series is composed of high-speed dynamic 4096-bit MOS random-access memories, organized as 4096 one-bit words. N-channel silicon-gate technology is employed to optimize the speed/power/density trade-off. Three performance options are offered: 300 ns access for the TMS 4050, 250 ns access for the TMS 4050-1, and 200 ns for TMS 4050-2. These options allow the system designer to more closely match the memory performance to the capability of the arithmetic processor.
All inputs except the chip enable are fully TTL-compatible and require no pull-up resistors. The input buffers allow a minimum 200 mV noise margin when driven by a series 74 TTL device. The TTL-compatible open-drain buffer is guaranteed to drive 1 series 74 TTL gate. The low capacitance of the address and control inputs precludes the need for specialized drivers. The TMS 4050 series uses only one clock (chip enable) to simplify system design. The low-capacitance chip-enable input requires a positive voltage swing (12 volts), which can be driven by a variety of widely available drivers. The data input and output are multiplexed to facilitate compatibility with a common bus system.
A 121ine address is available, which minimizes external control logic and optimizes system performance.
The typical power dissipation of these RAM's is 420 mW active and 0.1 mW standby. To retain data only 6 mW average power is required, which includes the power consumed to refresh the contents of the memory.
The TMS 4050 series is offered in both 18-pin ceramic (JL suffix) and plastic (NL suffix) dual-in-line packages. The series is guaranteed for operation from O°C to 70o
e.
Packages are designed for insertion in mounting hole rows on 300-mil centers.operation
chip enable (CE)
A single external clock input is required. All read, write, and read, modify write operations take place when the chip enable input is high. When the chip enable is low, the memory is in the low-power standby mode and is not selected. No read/write operations can take place during the standby mode because the chip is deselected and is automatically precharging.
PRELIMINARY DATA SHEET:
Supplementary data may be
published at a later date.
TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
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69
II
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TMS 4050 JL, NL; TMS 4050-1 JL, NL; TMS 4050-2 JL, NL 4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
operation (continued)
mode select (RjijiJ)The read or write mode is selected through the read/write (R/W) input. A logic high on the
Riw
input selects the read mode and a logic low selects the write mode. The read/write terminal can be driven from standard TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected and the data output is disabled when the write mode is selected.address (AO-A 11)
All addresses must be stable on or before the rising edge of the chip-enable pulse. All address inputs can be driven from standard TTL circuits without pull-up resistors. Address registers are provided on chip to reduce overhead and simplify system design.
data input/output (I/O)
Data input and output are multiplexed on a common input/output terminal, which is controlled by the